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Messages from 47625

Article: 47625
Subject: Re: design multiplier
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 01 Oct 2002 08:25:58 +0100
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> writes:

> ... an all digital analog ...

I like it :-)

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 47626
Subject: Re: Rounting of non-global IO pad to a GCLKIOB site.
From: "Ho Wong" <s354411@student.uq.edu.au>
Date: Tue, 1 Oct 2002 17:53:50 +1000
Links: << >>  << T >>  << A >>
So is there a way at all to clock this process without having to use the
bufg? And is it possible to short the two pins together? (current non-global
to a global one)
"Dali" <dadicool@ifrance.com> wrote in message
news:3D98E4DF.3010100@ifrance.com...
> It doesn't work that way. In order to take advantage of the clock tree
> brovided by the BUFG primitive you need to use an IBUFG instead of an
> IBUF. So a normal IO pins does not do the job.
>
> For further details, look at the Xilinx Handbook.
>
> Dali
>
> Ho Wong wrote:
> > Hello. I'm using a pin to drive a process but the thing is that it's
already
> > been soldered onto a normal IO pin. I've been trawling through past
posts
> > and newsgroups and I still haven't found a answer yet. I'm just a
beginner
> > to fpgas so i'm not very familiar with the low level logics. I tried
doing
> > PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN
has
> > illegal connection  Would it be possible to short my normal IO to one of
the
> > dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE
> > Webpack.
> >
> >
>
>



Article: 47627
Subject: SPDE problems
From: paul.lee@sli-institute.ac.uk (Paul)
Date: 1 Oct 2002 02:01:14 -0700
Links: << >>  << T >>  << A >>
Hi folks

I'm currently routing a design into a QuickRAM using SPDE. 

To set the pin locations, I use a .sc file and define the pin location
of an input from my design but when SPDE is run, the pin placement is
ignored.
The error message that comes up is "  Invalid fixed placement ioH1 for
gate STM_IN_p ignored  ".
In the .sc file, I just written "   postprop stm_in ql_placement =
"ioH1";    " as shown in the SPDE manual.

I use synplify to set up the pin location and it seem to have taken in
the information by analysing the .qdf file that was generated.
In the .qdf file, one of the lines is written as "  gate STM_IN_p
master Q_INPAD cell ioH1 end  " which kind of suggest the constraint
files was correct and that SPDE has taken in the information. Only
when SPDE is run, the file seem to be ignored.

The device I'm using is QuickRAM 4090 PB456. I have also changed the
location to H23 which is not used when running the SPDE without the
pin constraints.

How can I resolve the problem?

Regards

Paul

Article: 47628
Subject: Re: Search help about architecture of STARTUP?
From: "Ulises Hernandez" <ulises@britain.agilent.com>
Date: Tue, 1 Oct 2002 10:21:34 +0100
Links: << >>  << T >>  << A >>
Hi Cisa,

I have heard more than once that is not recommended to use the STARTUP block
in Virtex devices. The main reason was that is very slow propagating through
the device, if you are using a 10KHz clock you won't miss any clock pulses
but with a 50MHz clock you will.
The good thing is that it uses dedicated resources (that is why we can't see
it in FPGA Editor) and therefore you get it for nothing.

If I had to use an external reset I wouldn't connect it to the GSR, just
writing the VHDL/Verilog properly will make the synthesis/P&R tool :o) to
allocate low skew routing resources for it (this is just my opinion and it
depends for aeach design)

Regards.

Ulises Hernandez
ECS Technology Ltd.
www.ecs-tech.com


"Cisa" <jjyy@hotmail.com> wrote in message news:ee794a5.-1@WebX.sUN8CHnE...
> I instantiate a STARTUP_VIRTEX template in my verilog design,and use the
input signal GSR to reset my FFs.When I view my routed design in FPGA Editor
of ISE,I can see the input signals of STARTUP,but I can't see the output
signal of STARTUP to reset my FFs.
> Is it a right implementation result?
> Can you give me a detailed explanation of architecture about STARTUP
module in virtex?And what is the right method to instantiate a
STARTUP_VIRTEX in unimsims library?



Article: 47629
Subject: Re: FFT in FPGA?
From: "Paul Baxter" <pauljnospambaxter@hotnospammail.com>
Date: Tue, 1 Oct 2002 10:27:14 +0100
Links: << >>  << T >>  << A >>

Ray came up with some excellent advice as usual (and his company could
probably do your FPGA design far quicker than others as they have the cores,
knowledge etc.), however with the speeds you are talking about are you sure
that a DSP-based software solution wouldn't be better, less complex to
design and more than adequate for the data rates you mention.

Rays designs at many 10s of megahertz definitely need FPGA but for sonabuoy
processing I found that DSP was much more efficient and easily adaptable.

Just an opinion.

Paul





Article: 47630
(removed)


Article: 47631
Subject: re: SPDE problems
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Tue, 1 Oct 2002 10:28:04 +0100
Links: << >>  << T >>  << A >>
> -----Original Message-----
> From: Paul [mailto:paul.lee@sli-institute.ac.uk]
> Subject: SPDE problems

> I'm currently routing a design into a QuickRAM using SPDE. 
> To set the pin locations, I use a .sc file and define the pin location
> of an input from my design but when SPDE is run, the pin placement is
> ignored.
> The error message that comes up is "  Invalid fixed placement ioH1 for
> gate STM_IN_p ignored  ".
> In the .sc file, I just written "   postprop stm_in ql_placement =3D
> "ioH1";    " as shown in the SPDE manual.
[...]
> How can I resolve the problem?

I don't have the data to hand, but it must be either
(a) a bug in the P&R tool related to that package (very
    unlikely, but always possible)
(b) you've chosen a pin that isn't appropriate for the
    input port (for example, maybe you picked a power pin).

To get closer I suggest the following sanity check:

- remove your pin constraint from this signal
- run P&R and see what pin SpDE selects automatically - 
  if this fails, there's something goofy in your design
- set up a new constraint, specifying exactly the same pin 
  that SpDE chose automatically in the previous run
- run the job again - it should work OK

If the second run fails, it's pretty sure you have a buggy
tool and the nice guys at QuickLogic probably want to know
about it.  If my suggested procedure works, though, it's
likely your choice of pin H1 for this signal is inappropriate.
Possible reasons:
- paper data sheet is wrong and misled you into choosing an
  inappropriate pin (this has happened to me before now) -
  take a look at the pad schematic in the chip viewer, to see
  the definitive version of what it really is
- you chose the right pad for what you THINK the signal is 
  doing, but your HDL code is unexpectedly specifying a 
  driver on what you think is an input pad - or something
  like that
- finger trouble/snafu
- doubtless some more possibilities I haven't thought of

Good luck
-- 
Jonathan Bromley
HDL Consultant

DOULOS - Developing Design Know-how
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Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 =
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are not the views of Doulos Ltd., unless specifically stated.


Article: 47632
Subject: Re: TCP/IP in FPGA
From: "geeko" <jibin@ushustech.com>
Date: Tue, 1 Oct 2002 15:06:54 +0530
Links: << >>  << T >>  << A >>
hay
 iam not looking for such a solution TCP/IP in hardware is it feasible


"Janusz Raniszewski" <rniski@man.koszalin.pl> wrote in message
news:3D994313.F5AB54AD@man.koszalin.pl...
> > What are the chances of implementing a TCP/IP stack using VHDL anybody
do
> > anything similar.Can the Spartan FPGA be used to hold the design
>
> Hello,
> It is simple. You may implement some microcontroller core and ,,,,,, :-)
> JanuszR
>



Article: 47633
Subject: Re: Anyone knows of a example FPGA design which reads and writes a SmartMedia card?
From: "Tony Burch" <tony@burched.com.au>
Date: Tue, 1 Oct 2002 20:06:36 +1000
Links: << >>  << T >>  << A >>
Hi Karl,

If your wav files were written to the SM card from
a PC SmartMedia reader/writer, then your FPGA
will also need to handle the file-system aspects,
in addition to being able to read the raw sectors of
the SM card.

I did a google search, as you probably also did,
and it didn't turn up a system example.  But something
that I came across recently may be a good starting
point.  June, July, August and September 2002 issues
of Circuit Cellar Magazine presented articles, written
by Jeff Bachiochi, on using SmartMedia in an embedded
system.  In this case the PIC18F452 is used.

The articles deal with details of SmartMedia
and a Windows/DOS-Compatible
files system, which enables exchanging embedded data
with PC applications.  All of these articles are available
in electronic form for purchase from the Circuit Cellar
Website.   They are US$1.50 each.
http://www.circuitcellar.com/magazine/tocarchive.asp

One possible way to proceed with your implementation
is to put a micro core in your FPGA, which could
handle the SmartMedia interface.  15K gates is
enough to instantiate a micro.  Or simply design
a state machine to handle the interface.

Of course, if you're not locked into SmartMedia,
using Compact Flash cards may be an
alternative for you.  BurchED has an FPGA to Compact
Flash plug-on module, for this kind of application
http://www.burched.biz/b5compactflash.html

Hope that helps:)

Best regards
Tony Burch
http://www.BurchED.biz
FPGA boards for System-On-Chip prototyping and education
* * 10% off the normal price of all products, sale now on * *

"Karl" <Far@East.Design> wrote in message
news:3d994da5$1@news.starhub.net.sg...
> Anyone knows of a example FPGA design which reads and writes a SmartMedia
> card?
> What are the stuff I need to read on the net, my design is simple, I want
to
> read the .wav
> files from a SM card and feed this data into a speaker. My board will have
a
> 15K gate
> vertex chip and a PWM digital to analog converter and amplifier, plus a
> fixture which
> connect up the SM card (stripped from a broken SM reader).




Article: 47634
Subject: Re: Nios interrupt latency?
From: "Matjaz Finc" <matjaz.finc@fe.uni-lj.si>
Date: Tue, 1 Oct 2002 12:09:40 +0200
Links: << >>  << T >>  << A >>
Tri simulating with Modelsim. In a simple 32 bit configuration (512
registers) it takes around 75 clk cycles to switch.

Matjaz

"Peter Sommerfeld" <peter@vtecna.com> wrote in message
news:amvoa0$566$1@avvidasystems.com...
> Does anyone have the ISR switch and release times for Nios? Ideally for
Nios
> 2.1?
>
> -- Pete
>
>



Article: 47635
Subject: Re: Search help about architecture of STARTUP?
From: Cisa <jjyy@hotmail.com>
Date: Tue, 1 Oct 2002 03:28:57 -0700
Links: << >>  << T >>  << A >>
Indeed,the reason I use STARTUP
in my verilog desing is that I can't get my virtex-e device to work
after configuration.As for the phenomenon,the DONE pin and INIT pin of the device both goes high.
And I suspect that the STARTUP sequence after the configuration is not completed.So I add a STRATUP module in my verilog design.
Who can give me any advice about the
configuration process and the corresponding code desing?
Another question,What is the function of clk declared in STARTUP_VIRTEX module?3x!!!

Article: 47636
Subject: Re: Anyone knows of a example FPGA design which reads and writes a SmartMedia card?
From: "Karl" <Far@East.Design>
Date: Tue, 1 Oct 2002 18:30:21 +0800
Links: << >>  << T >>  << A >>
Thank you Tony.
I am a electronics hobbyist.
I visited your website, it's pretty cool though. But I wonder where you have
found out a good
PCB software? I used CadStar from Zuken, but it didn't seem very
user-friendly.





"Tony Burch" <tony@burched.com.au> wrote in message
news:3d9973a3$0$30861$afc38c87@news.optusnet.com.au...
> Hi Karl,
>
> If your wav files were written to the SM card from
> a PC SmartMedia reader/writer, then your FPGA
> will also need to handle the file-system aspects,
> in addition to being able to read the raw sectors of
> the SM card.
>
> I did a google search, as you probably also did,
> and it didn't turn up a system example.  But something
> that I came across recently may be a good starting
> point.  June, July, August and September 2002 issues
> of Circuit Cellar Magazine presented articles, written
> by Jeff Bachiochi, on using SmartMedia in an embedded
> system.  In this case the PIC18F452 is used.
>
> The articles deal with details of SmartMedia
> and a Windows/DOS-Compatible
> files system, which enables exchanging embedded data
> with PC applications.  All of these articles are available
> in electronic form for purchase from the Circuit Cellar
> Website.   They are US$1.50 each.
> http://www.circuitcellar.com/magazine/tocarchive.asp
>
> One possible way to proceed with your implementation
> is to put a micro core in your FPGA, which could
> handle the SmartMedia interface.  15K gates is
> enough to instantiate a micro.  Or simply design
> a state machine to handle the interface.
>
> Of course, if you're not locked into SmartMedia,
> using Compact Flash cards may be an
> alternative for you.  BurchED has an FPGA to Compact
> Flash plug-on module, for this kind of application
> http://www.burched.biz/b5compactflash.html
>
> Hope that helps:)
>
> Best regards
> Tony Burch
> http://www.BurchED.biz
> FPGA boards for System-On-Chip prototyping and education
> * * 10% off the normal price of all products, sale now on * *
>
> "Karl" <Far@East.Design> wrote in message
> news:3d994da5$1@news.starhub.net.sg...
> > Anyone knows of a example FPGA design which reads and writes a
SmartMedia
> > card?
> > What are the stuff I need to read on the net, my design is simple, I
want
> to
> > read the .wav
> > files from a SM card and feed this data into a speaker. My board will
have
> a
> > 15K gate
> > vertex chip and a PWM digital to analog converter and amplifier, plus a
> > fixture which
> > connect up the SM card (stripped from a broken SM reader).
>
>
>



Article: 47637
(removed)


Article: 47638
Subject: Re: Getting started
From: russelmann@hotmail.com (Rudolf Usselmann)
Date: 1 Oct 2002 04:35:24 -0700
Links: << >>  << T >>  << A >>
"Blackie Beard" <BlackBeard@FearlessImmortalWretch.com> wrote in message news:<YHRl9.7422$1F3.6383@nwrddc02.gnilink.net>...
> For your own board manufacture, there was some Iron-on
> stuff that only works for traces over 20 mil., or so.  Then
> there's them cool machines that use a router, my last
> company had that.  But you can't do fine traces with that
> either.  Better to just bite the bullet.  There are prototype
> shops you can just email your gerbers to, 2-3 day turn,
> low quantity.
> 
> For MIPS core, you aren't going to get that for free, me

Oh yeah ?!  Well, think again, and then kindly follow this
link: www.OpenCores.org    :^P

You shall find TWO (!) MIPS cores (Plasma & Yellow Star) and
many, many other FREE IP Cores !

Cheers,
rudi
----------------------------------------------
www.asics.ws - Solutions for your ASIC needs -

> thinks!  But you can sometimes buy a test chip for around
> $10-20, and build the SoC interconnects using an FPGA.
> You'll probably need at least 400K equiv gates.  That
> won't be cheap either.  Good luck, and reply if you find
> something interesting.
> 
> 
> "RCU" <nemesis@icequake.no_spam.net> wrote in message
> news:pan.2002.09.30.02.18.12.141498@icequake.no_spam.net...
> >
> > > For Layout, I found that I liked the Eagle for Windows free
> > > layout program.  You can make boards up to a certain size,
> > > which is OK for a lot of stuff.  Something like 3x4 inches?
> >
> > What about the actual physical manufacturing of a board?  I see lots of
> > homebrew-available kits (Press N Peel, et al), and a few homebrewn
> > methods:
> > http://www.netcomuk.co.uk/~wwl/pcbs.html
> >
> > for example.
> >
> > > For FPGA, it depends on size.  What is your first design
> > > going to be?
> >
> > I have no idea. :)  I thought it would be fun to implement a MIPS core or
> > something similar.  If that turns out to be too complex for the bits I can
> > afford, then I might play with implementing old hardware anew, such as a
> > portable Super NES, or something along those lines.
> >
> > I don't think anything I would want to do is anywhere near, say, a CPU
> > produced even in the last 5 years.  I just want flexibility for
> > experimentation.  If that makes any sense.
> >
> > Thanks!
> >

Article: 47639
Subject: Re: SOC interconexion
From: russelmann@hotmail.com (Rudolf Usselmann)
Date: 1 Oct 2002 04:57:24 -0700
Links: << >>  << T >>  << A >>
"news.terra.es" <securez@teleline.es> wrote in message news:<QRVl9.310521$sI1.2734123@telenews.teleline.es>...
> I have a MC68VZ328 system interfacet to a Acex 1K30 device, i have a doubt,
> the processor are a 32bit but the system bus are 16bit, i want to include
> the a core int the FPGA for ide interface, but the whisbone slave core for
> ide have 32bit registers, and SEL_i need to be 1111 32bit data, it's posible
> to cahnge the master controler to drive this 32 bit data from he 16 bit bus
> of the system┐?
> 
> Any help will be apreciated.


I assume you are using the OCIDEC from www.opencores.org.
You can easily modify the 32 bit wishbone interface to
be 16 bits only. It's such a simple core should be very
easy.

Cheers,
rudi
----------------------------------------------
www.asics.ws - Solutions for your ASIC needs -

Article: 47640
Subject: Re: FFT in FPGA?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 01 Oct 2002 11:57:51 GMT
Links: << >>  << T >>  << A >>
I agree with Paul in principle.  As I've stated before, if a process can be
handled by a single DSP we usually recommend using that over an FPGA simply
because the design talent is cheaper and easier to find.

Paul Baxter wrote:

> Ray came up with some excellent advice as usual (and his company could
> probably do your FPGA design far quicker than others as they have the cores,
> knowledge etc.), however with the speeds you are talking about are you sure
> that a DSP-based software solution wouldn't be better, less complex to
> design and more than adequate for the data rates you mention.
>
> Rays designs at many 10s of megahertz definitely need FPGA but for sonabuoy
> processing I found that DSP was much more efficient and easily adaptable.
>
> Just an opinion.
>
> Paul

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 47641
Subject: Re: Configuration:Startup
From: Ray Andraka <ray@andraka.com>
Date: Tue, 01 Oct 2002 11:59:40 GMT
Links: << >>  << T >>  << A >>
No, it is not.  Are you giving it enough cclks after programming completes?  If you are using JTAG, make sure you set the
configuration to use the JTAG clock or it will do this.

Cisa wrote:

> I have configured a virtex-e device,
> and DONE goes high,INIT also goes high .That indicates that configuration has finished,but the device can't start to work.
> I suspect the virtex-e does not finish the STARTUP sequence.
> Is it necessary to instantiate a STARTUP_VIRTEX module in my verilog design for STARTUP sequence?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 47642
(removed)


Article: 47643
(removed)


Article: 47644
Subject: Re: DFT , Design For Test HELPPPPP
From: thomas@stanka-web.de (Thomas Stanka)
Date: 1 Oct 2002 06:08:34 -0700
Links: << >>  << T >>  << A >>
X-Post without folowup isn't the best choice to spread your lack of
wisdom :)
X-Post to caf und clv without followup

"Djohn" <deepucjohn@yahoo.com> wrote:
>   I am now designing a Uart chip for study purposes. Now I am almost over
> with my design and VHDL Coding .  I would like to integrate the DFT strategy
> in the chip .

Interesting excercise. But I have problem with _the_ DFT strategy.

> 2) I have a fair good knowledge of JTAG . So If I integrate a JTAG circuitry
> in the chip (the tap controller , data registers  and instruction
> registers), will it become  DFT compatible?

Answer your self: will the design be testable with this cirquit?
If you just forgot to mention boundary scan, it might be the first
step to DFT.
DFT=Design For Testability, not design to fake test.
 
> 3) What exactly is BIST ? How is it implemented ? Any online  tutorials or
> good links ...

BIST=Build in Self Test, any logic on chip, that tests your cirquit
without external hardware is BIST.

> 4) What is ATPG ? how is it implemented? Any online  tutorials .......

Automatic Test Pattern Gerneration. Typical a Programm that generates
testpattern for your cirquit.
 
> 6) A comparison between these strategies? any links also welcome

www.google.com is your best friend.

Buzzwords:
- atpg
- bist
- dft
- marchtest (for RAM)
- boundary scan
- scanchains
- scantest
- LFSR 

For ATPG you could start at the homepage of synopsys or cadence

I think you should start with some books concerning DFT, because it
might be too complex reading all the papers concerning these themes
without knowing where to start and where to go along.
If you have more detailed questions, you might get more answers here.

bye Thomas

Article: 47645
Subject: Re: FFT in FPGA?
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Tue, 1 Oct 2002 10:13:18 -0400
Links: << >>  << T >>  << A >>
Paul,
    I am not surprised to here your response.  I wondered myself about
whether the FPGA was overkill.  The reason for the FPGA is that the
particular student is realy interested in dsp in FPGA.  His area of interest
is not signal processing algorythms but rather hardware based DSP.  He is,
therefore, more interested in the FPGA based approach.  As you can imagine,
working in an academic environment is a little different than working in
industry.   I suspect that this system is somewhere between radar and
sonobouys.  By the way, who do you do sonobouys for?  In the late 1970's to
early 1980's, I used to work for Spartan Corporation (in Jackson, MI) doing
bouys and other similar things.

Thanks,
Theron Hicks

"Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message
news:3d996a27$0$8510$cc9e4d1f@news.dial.pipex.com...
>
> Ray came up with some excellent advice as usual (and his company could
> probably do your FPGA design far quicker than others as they have the
cores,
> knowledge etc.), however with the speeds you are talking about are you
sure
> that a DSP-based software solution wouldn't be better, less complex to
> design and more than adequate for the data rates you mention.
>
> Rays designs at many 10s of megahertz definitely need FPGA but for
sonabuoy
> processing I found that DSP was much more efficient and easily adaptable.
>
> Just an opinion.
>
> Paul
>
>
>
>



Article: 47646
Subject: Re: Unused pins in Apex20KE
From: Richard Damon <Richard_Damon@hotmail.com>
Date: Tue, 01 Oct 2002 10:34:56 -0400
Links: << >>  << T >>  << A >>
"Blackie Beard" <BlackBeard@FearlessImmortalWretch.com> wrote:

>One of the stupidest things about Altera Quartus S/W (at least the
>first versions, I don't know about later ones) was that hidden about
>4 submenus down, was the setting for what to do with unused pins,
>the default choice; "As Outputs Driving Ground".  What if you have
>the board made first, with the I/O in place, and want to add the
>various interface blocks of the design in incrementally?  You can
>get some real hot chips.  You must know about this setting, and
>find it and change it to "As Tri-State Inputs", and remember to do
>so with any design revisions, or your prototype is toast.  I tried to
>tell Altera, but to no avail.
>

The problem with "As Tri-State Inputs" is that this makes every unused pin a
floating input and subject to noise injection and excessive poser consumption
unless you connect them on the board to a valid signal level. A better solution
in my experience is to add at the beginning all of the pin definitions even if
that module is not used (after all you know what pin they are going to since the
board is built.)


-- 
richard_damon@iname.com (Redirector to my current best Mailbox)
rdamon@beltronicsInspection.com (Work Adddress)
Richad_Damon@msn.com (Just for Fun)

Article: 47647
Subject: iMPACT in WebPACK 5.1
From: "Jan Pech" <j.pech@noSPAMieee.org>
Date: Tue, 1 Oct 2002 16:42:55 +0200
Links: << >>  << T >>  << A >>
Hi all,

After installing ISE WebPACK 5.1 I can configure devices only when I run the
iMPACT as an administrator in win2k. I'm using parallel cable and I haven't
found parallel port driver as in all previous versions of WebPACK.
Is it possible to configure devices from iMPACT using parallel cable when I
run it as normal - non privileged - user under windows 2000?

Thanks a lot,
Jan
_________________________
     j.pech _AT_ ieee.org
     http://fpga.f2g.net




Article: 47648
Subject: Re: TCP/IP in FPGA
From: hmurray@suespammers.org (Hal Murray)
Date: Tue, 01 Oct 2002 16:19:22 -0000
Links: << >>  << T >>  << A >>
[suggest software]
> iam not looking for such a solution TCP/IP in hardware is it feasible

Look at the source code for a TCP stack.  It's a huge state machine.
Just take a page or two of code and try to convert that to hardware.

I haven't seen any reports of doing TCP in hardware, but I could
easily have missed something.  (But somebody would probably mention
it here.)

As an example, consider just routing, a small part of the TCP/IP stack.
High end routers do some of the table lookup in hardware, but they
normally drop back to software for the hard/rare cases.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 47649
Subject: Where can i buy xilinx fpga online?
From: henrique@bmrio.com.br (Henrique)
Date: 1 Oct 2002 09:51:14 -0700
Links: << >>  << T >>  << A >>
Where can i buy xilinx fpga online?
Tanks Henrique.



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