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The XC4000E and later (XC4000XLA, Spartan, Virtex, etc.) all allow initialization of RAM. See Answer 178 on xilinx.com. Ray Andraka wrote: > IIRC, the 'problem' in the 4000 series only applied when using the > async mode for the RAMs. It has been quite a while tho, so I could be > suffering memory loss. In any event, Virtex works fine with initial > values. Typically, I use SRL16s instead of RAMs except for the very > rare instance where I can't make the SRL16 do what I need. -- Marc Baker Xilinx ApplicationsArticle: 52676
Peter Alfke wrote: > This might save you some time and effort: > > Software Manuals > http://toolbox.xilinx.com/docsan/xilinx4/manuals.htm And just replace the "4" with a "5" for v5.x. Or start from the top at http://www.xilinx.com/support/software_manuals.htm to select your favorite version and format. -- Marc Baker Xilinx ApplicationsArticle: 52677
sri_valli_design@hotmail.com (Valli) wrote in message news:<d9acfecb.0302180820.a6b5174@posting.google.com>... > hi, > > Leonardo is giving different Flop count, if I target same > design(arround 10K gate) to ASIC technology and FPGA technology. > > Please let me what could be the possible reasons! Could it be smart enough to duplicate logic (or not) depending on the situation and timing requirements? MarcArticle: 52678
I got this message from the static timing analyzer of xilinx ISE.
Apparently, I have 3 hold violations. One of them has the following
information. How do you solve this? Thank you and hope to hear from
you soon.
Hold Violations: Default period analysis
--------------------------------------------------------------------------------
Hold Violation: -8.816ns (data path - positive clock skew)
Source: inst_id_ex_inst_block_im8_out_2
Destination: u_shift_mux_reg_out_sig_2
Data Path Delay: 8.315ns (Levels of Logic = 4)
Positive Clock Skew: 17.131ns
Source Clock: inst_clk_out_inst_block_I_cp15clk_11 falling
Destination Clock: inst_clk_out_inst_block_I_cp15clk_13 falling
Timing Improvement Wizard
Data Path: inst_id_ex_inst_block_im8_out_2 to
u_shift_mux_reg_out_sig_2
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.772 inst_id_ex_inst_block_im8_out_2
net (fanout=1) 0.357 inst_id_ex_inst_block_im8_out_2
Tilo 0.398 u_bmux_Mmux_b_out_sig_inst_lut3_225
net (fanout=3) 0.658
u_bmux_Mmux_b_out_sig_xstmacro_int_tempname303
Tif5 0.752
u_bmux_Mmux_b_out_sig_xstmacro_int_tempname303_rt
u_bmux_Mmux_b_out_sig_inst_mux_f5_100
net (fanout=20) 4.781
u_bmux_Mmux_b_out_sig_xstmacro_int_tempname304
Tcki (-Th) -0.597 u_shift_mux_I_shift_sig_2_1
u_shift_mux_reg_out_sig_2
---------------------------- ------------------------------
Total 8.315ns (2.519ns logic, 5.796ns route)
(30.3% logic, 69.7% route)
Article: 52679Hello! I'm trying to interface my project to a gigabit ethernet transceiver (DP83820) but alas, the interface is only PCI. Has anyone ever tried doing this sort of quick-hack PCI interface, just to talk to a single PCI peripheral? What timing constraints become less of an issue in this situation? Might anyone know of any example code for this sort of thing? Any general suggestions? Thanks, SteveArticle: 52680
Hi there, Currently we are using a board with a Virtex XCV600 and a XC18V04 in system programmable configuration PROM. The XC18V04 (4-MBit) comes in a VQ44 package. As we want to upgrade to a Virtex XCV800 we need a larger configuration device. Referring to the Xilinx documentation we need an additional device for this purpose. However we don't want to change the board layout. Does anyone know if there is a pin compatible configuration PROM in the give package with a greater memory size ? Or even know another solution ? Any help is much appreciated. Best wishes, Lars. -- GnuPG public key: http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.keyArticle: 52681
What is gate boosting? what are the pros and cons of the technology? Does is it being used in any FPGA device?Article: 52682
If you can use OTP device, Xilinx has XC17V08 (8 Mbits) and XC17V16 (16Mbits). If you want reprogrammable, you can look at Xilinx System ACE in which they have an MPM module which integrates an AMD flash memory, which can give 16, 32 and 64 Mbits of configuration memory in a single chip. Here's the link http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=system_ace "Lars Unger" <larsu@ida.ing.tu-bs.de> wrote in message news:Pine.LNX.4.50.0302191204270.27548-100000@wichtel.ida.ing.tu-bs.de... > Hi there, > > Currently we are using a board with a Virtex XCV600 and a XC18V04 in system > programmable configuration PROM. The XC18V04 (4-MBit) comes in a VQ44 package. > As we want to upgrade to a Virtex XCV800 we need a larger configuration device. > Referring to the Xilinx documentation we need an additional device for this > purpose. However we don't want to change the board layout. > > Does anyone know if there is a pin compatible configuration PROM in the give > package with a greater memory size ? Or even know another solution ? > > Any help is much appreciated. > > Best wishes, > Lars. > -- > GnuPG public key: > http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.keyArticle: 52683
Ken <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote: > Timing summary: > --------------- > > Timing errors: 0 Score: 0 > > Constraints cover 57440 paths, 0 nets, and 6107 connections (99.9% coverage) > > Design statistics: > Minimum period: 11.156ns (Maximum frequency: 89.638MHz) > Maximum path delay from/to any node: 11.156ns > > So, no timing errors - fair enough. > > However, the tools report the maximum frequency as being about 89MHz with > this number being derived from the "Maximum delay" of the TS_CLKEN timing > constraint. > > Given that both the timing constraints TS_CLK and TS_CLKEN were met with 0 > errors, I would have expected the tools to report the maximum frequency as > 150MHz and give some sort of qualifying statement with respect to the logic > that will only meet timing when clock enabled at 75MHz... > > Anyway, here are the questions: > > (1) > Do my UCF constraints look ok for my purposes? Generally. Here's a couple of suggestions. Firstly, wildcards should work so you should be able to use "clken*" instead of listing them all; that will make the design a bit more future-proof in case some are deleted or added (at the synthesiser's whim). Secondly you may need to add some constraints for the paths between non-enabled FFs and enabled FFs, and vice-versa. By default they will be constrained to the full clock period (not the half-speed clock) which might be OK for your application. > (2) > The Xilinx constraints editor found a whole load of clken signal instances > and I figured I would need to group them all - is this correct? Yes. Probably your synthesiser generated the extra signals to reduce fanout. > (3) > If my constraints are correct, does the fact that timing analysis reports 0 > errors and a maximum clock freq of less than 150MHz mean that I will be ok > to clock this design at 150MHz and it will work ok (i..e the 75MHz enabled > logic will work ok along with the 150MHz logic) or am I missing something? > > (4) > Why is the CLK signal being reported in the "Src Rise" to "Dest Rise" box > above as being 11.156 ns when it should be 6.463 ns as reported above that? > > (5) > If there are no timing violations, surely my maximum frequency is 150MHz? I think you're expecting too much from the timing summary! I never even read it in my designs. Once you have a few clock domains or clock enable domains it isn't useful. In your case, those paths really won't go any better than 11.156 ns - but that's fine because you're running them at 75 MHz, not 150 MHz. The tool isn't smart enough to work out what rate your divider is producing. Others might disagree but I suggest ignore the timing summary. Only the constraint coverage information is useful. > (6) > In the .PCF file, it seems like all of the signals in the design are grouped > under both the TIMEGRP "CLKEN" group and the TIMEGRP "CLK" group. Is this > what you would expect? Yes. Those CLKEN flip flops are still using CLK so they are still in the CLK group. I think your constraints are fine - it should work. BTW you should add some margin to your period constraint for clock jitter. Your clock is 150 MHz on average but the instantaneous period will vary. Instead of 6.66 ns consider using 6.5 or better. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 52684
Hi Kolja,
Thank you for your answer. I am using a TQFP-144 package and the clock
frequency will be 8 Mhz. Do you think that a 2-layer PCB will work, or 4
layers are necessary for correct circuit operation?
Stamatis
"Kolja Sulimma" <kolja@bnl.gov> wrote in message
news:25c81abf.0302181322.7584e4d4@posting.google.com...
> > Hi all,
> > I am designing a PCB using an XC2S100 FPGA. Does anyone know where I
can
> > find design considerations for this PCB, such powering, bypass
capasitors,
> > etc. Is there something special I must pay attention to?
>
> What kind of package do you use?
>
> If you do a two layer board you must be very careful with your power
> routing. Usually you have three power supply rails and only one layer
> to connect them to the FPGA. With four layers live is simple.
>
> The amount of bypass capacitors necessary varies with the amount of
> simultenous switching going on and the slew rates selected for the
> outputs. Usually you do not need one capacitors per power/ground pair.
> But there are people who suggest that you should, and if your
> application is more demanding with respect to transient power, you
> should folow theire advice.
> Surely every power and ground pin should have a very short connection
> to a capacitor and the capacitor should have a small SMD outline and a
> low ESR dielectricum.
>
> I remember seeing Xilinx application notes on PCB design. At least for
> the ball grid packages there are detailed guidelines.
>
> Kolja Sulimma
Article: 52685I'm trying to rebuild an old ABEL file and I don't seem to be able to get any of the tools - abl2pld, abl2edif, etc - to produce an output netlist. They all fail from 2.1i to 4.1i. What I *do* get is a warning message saying that the tools can't find some file called Xabel.msg Anyone got any ideas ? I'm really stuck & don't want to have to re-write in Verilog.Article: 52686
Kolja Sulimma wrote: >>Do you know of any interface chips for Cardbus? The usual >>suspects (National/Zilog/etc) have all discontinued what >>they had.All I can find are ASICS for Ethernet and the like. > > > AFAIK CardBus is very similar to PCI so you should be able to modify a > PCI-Core to build a CardBus Card. > > The 16-Bit PCCard interface is extremly simple and should fit into a > smaller CPLD. You could use this if you want to reconfigure your FPGA > dynamically. > > Kolja Sulimma Thats more or less what I plan to do now. Thanks to everyone for your help. Kind regards, IwoArticle: 52687
Hamish, Thanks for your reply. > > (1) > > Do my UCF constraints look ok for my purposes? > > Generally. Here's a couple of suggestions. Firstly, wildcards should > work so you should be able to use "clken*" instead of listing them all; > that will make the design a bit more future-proof in case some are > deleted or added (at the synthesiser's whim). OK - that is a good idea. > Secondly you may need to add some constraints for the paths between > non-enabled FFs and enabled FFs, and vice-versa. By default they will be > constrained to the full clock period (not the half-speed clock) which > might be OK for your application. I think I will leave doing that until I run into problems! > > (3) > > If my constraints are correct, does the fact that timing analysis reports 0 > > errors and a maximum clock freq of less than 150MHz mean that I will be ok > > to clock this design at 150MHz and it will work ok (i..e the 75MHz enabled > > logic will work ok along with the 150MHz logic) or am I missing something? > > > > (4) > > Why is the CLK signal being reported in the "Src Rise" to "Dest Rise" box > > above as being 11.156 ns when it should be 6.463 ns as reported above that? > > > > (5) > > If there are no timing violations, surely my maximum frequency is 150MHz? > > I think you're expecting too much from the timing summary! I never even > read it in my designs. Once you have a few clock domains or clock enable > domains it isn't useful. In your case, those paths really won't go any > better than 11.156 ns - but that's fine because you're running them at > 75 MHz, not 150 MHz. The tool isn't smart enough to work out what rate > your divider is producing. > > Others might disagree but I suggest ignore the timing summary. Only the > constraint coverage information is useful. OK - so because my contraints gave 99.9% coverage with 0 timing errors - I can assume that the design will work with the 150MHz master clock and the 75MHz enabled paths? > I think your constraints are fine - it should work. Cool. > > BTW you should add some margin to your period constraint for clock > jitter. Your clock is 150 MHz on average but the instantaneous period > will vary. Instead of 6.66 ns consider using 6.5 or better. Willdo. Thanks for your time, KenArticle: 52688
Ken Chapman <chapman@xilinx.com> wrote in message news:<3E50FD4B.D3CEF9DB@xilinx.com>...
> Dear Akshay,
>
> I would be very concerned about precision.
>
> > output<=2*8127*y(2)/8192-y(3);
>
<snipped>
Hello Again,
My model simulates well in modelsim giving me exact response. As
Mr. Chapman suggested i modified the precision and the simulation
(both in modelsim and matlab) yields expected output (sine wave). I
changed the variable to store a variable of 1^27 length and then pick
the 13 MSB's. is there a bug out there, which i have overlooked
totally ? (This is my very is among my very first experience with vhdl
adn fpga's.). I did some basic stuff with my board (The Xtreme dsp
board) like square wave,triangular wave and that works out well (again
as expected). The sine wave generation works great on a dsp etc.
thanx,
regards,
akshay.
Article: 52689Hi I have downloaded the file xapp209.zip from your web site about an hardware crc implementation. Could someone can explain me how the xor equations are generated ? I compare the crc results with some soft crc, and i don't have the same crc. Your help will be very appreciated. Cheers DominiqueArticle: 52690
We are going to be using an fpga in a future product, and are trying to decide which family to use. The most likely candidates seem to be Xilinx Spartan or Altera Cyclone. The application will involve a error checking and correcting for a communications link, plus a few other bits of control logic. There is nothing too complex in it, nor do we need very high speed (we are talking 100 kHz max), but it is more than I would like to fit into a small microcontroller, which would be the alternative solution. We also need a microcontroller on the board for a few other functions, so it could be very interesting to look at soft cpus. Speed is not really an issue, but temperature is - we would like components rated as high a temperature as possible. The price of the chips themselves is not a major issue, since we would only be looking at a few systems, but the price of development kits (simple demo card, programming cabel, basic developement tools) is correspondingly more relevant - especially since we will probably need two sets. I have had some experiance using a cpld (Mach 4), and would prefer to work in VHDL, with Verilog as a second choice. If we go for an embedded cpu, then I am quite happy working with gcc and gdb ports, as long as I can get some basic debugging access to the processor (via jtag, or a serial port) to start/stop the processor, read and write memory, and (hopefully) at least one hardware breakpoint. We can expect good support from our distributers for either Xilinx or Altera, but I would value any opinions others here may have about which we should choose, or pointers to any web pages that could help us decide. David Brown NorwayArticle: 52691
In article <b30ago$u75$1@news.netpower.no>, David Brown <david@no.westcontrol.spam.com> wrote: >We can expect good support from our distributers for either Xilinx or >Altera, but I would value any opinions others here may have about which we >should choose, or pointers to any web pages that could help us decide. Flip a coin? The requirements you've stated are rather low, so either should work just fine. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 52692
Hi, Im a new user of FPGAs. I am trying to configure my Spartan1. I am using Boundry Scan mode to programming via a paralell 3 cable. According to the ISE software the program was downloaded to the spartan successfully, but im advised to manually check the done pin(the done pin isn,t used in the boundry scan mode?). When i check this, the Done pin isLOW, even though i have a 4.7Kohm resistor pulling it high. Also all the I/O pins (even the ones that aren't used in my program) are all at 5V, but i dont think there is much if any current on these I/O pins. Please can someone advise me. Does this sound right, if not are there any solutions? Conor CarrArticle: 52693
David, when I read "highest temperature" and "Norway", I assume this is for a down-hole oil-exploration drilling application. Xilinx devices have been used for such applications for many years. I remember that users reported week-long operation at 175 degr C, but that may have been a ceramic-packaged hybrid circuit. They also intended to try 200 degr C, but I never heard the results. Silicon usually works fine at 175, but timing parameters are slower, and of course not guaranteed. The plastic package material is usually the first one to give problems at very high temperatures. Xilinx offers MicroBlaze as a soft microprocessor. You mention Spartan and Cyyclone. These are the low-cost FPGA families from the two vendors ( Is Cyclone really available?). In your case, where the absolute lowest component cost is not the issue, you should also consider Virtex-II from Xilinx. But the Spartan-II family goes down to smaller chip sizes. You can download the software :-) Greetings Peter Alfke, Xilinx Applications David Brown wrote: > We are going to be using an fpga in a future product, and are trying to > decide which family to use. The most likely candidates seem to be Xilinx > Spartan or Altera Cyclone. The application will involve a error checking > and correcting for a communications link, plus a few other bits of control > logic. There is nothing too complex in it, nor do we need very high speed > (we are talking 100 kHz max), but it is more than I would like to fit into a > small microcontroller, which would be the alternative solution. We also > need a microcontroller on the board for a few other functions, so it could > be very interesting to look at soft cpus. Speed is not really an issue, but > temperature is - we would like components rated as high a temperature as > possible. > > The price of the chips themselves is not a major issue, since we would only > be looking at a few systems, but the price of development kits (simple demo > card, programming cabel, basic developement tools) is correspondingly more > relevant - especially since we will probably need two sets. > > I have had some experiance using a cpld (Mach 4), and would prefer to work > in VHDL, with Verilog as a second choice. If we go for an embedded cpu, > then I am quite happy working with gcc and gdb ports, as long as I can get > some basic debugging access to the processor (via jtag, or a serial port) to > start/stop the processor, read and write memory, and (hopefully) at least > one hardware breakpoint. > > We can expect good support from our distributers for either Xilinx or > Altera, but I would value any opinions others here may have about which we > should choose, or pointers to any web pages that could help us decide. > > David Brown > NorwayArticle: 52694
I have a board with pinout for EP1C6 and EP1C12 (Q240). As EP1C12 is currently not available I use EP1C6. Both have almost the same pinout. EP1C12 has additional GND and VCCINT pins (which are connected to GND and 1.5V on the board). My question is: Do I have to define these pins as input on the EP1C6 ot can I leave them unassigned? Default unasigned pins are GND* in Quartus. As I understand these pins are intern connected to GND. That's definitly a problem with the VCCINT pins. But when I assign 'dummy' input pins some of them are connected to 1.5V. About the middle of the VCCIO (3.3V). Would be nice if 'device migration' is enabled in the Web version of Quartus. MartinArticle: 52695
Hi all, I've got a problem in instantiating single port Block RAM in WebPack 4.2 and 4.1. When my Block RAM exceeds 128 bits, the XST synthesizer seems to not recognize a Block RAM description and instantiates it as distributed RAM, even if I use the Xilinx template and set RAM Style = Block! Is this a WebPack bug? How can I fix it? [I've tried to install the Service Pack, but nothing appended...] Thanks in advance Dr. Jones P.S. I'm using a Spartan2E (xc2s300e-6pq208)Article: 52696
> Thank you for your answer. I am using a TQFP-144 package and the clock >frequency will be 8 Mhz. Do you think that a 2-layer PCB will work, or 4 >layers are necessary for correct circuit operation? The clock frequency isn't the critical parameter. It's the edge rate. Of course, the edge rate must be fast for a high speed clock, but it can also be fast when the clock is running slowly, and often is with modern chips. I'd expect it would be interesting/challenging to get a solid design on two layers. I'm sure it's been done. Do you have any big busses? (Lots of outputs changing at the same time.) Are all your outputs using low drive? How many long wires? I'd probably do a trial layout and start by filling the bottom layer under the chip with a ground pad. Can you get the bypass caps near the power pins? What else is on the board? Can you use most of the bottom layer as a ground plane? The other consideration is how important is it that it work the first time? Do you have a software team waiting? How much time are you willing to spend chashing obscure bugs? Are the extra layers cheap insurance? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 52697
Conor, When tou generate the bitstream is there an option (bitgen) for the startup clock, this should be jtagclk in you case (not cclk) Aurash Conor Carr wrote: > > Hi, > Im a new user of FPGAs. I am trying to configure my Spartan1. I am > using Boundry Scan mode to programming via a paralell 3 cable. > According to the ISE software the program was downloaded to the > spartan successfully, but im advised to manually check the done > pin(the done pin isn,t used in the boundry scan mode?). When i check > this, the Done pin isLOW, even though i have a 4.7Kohm resistor > pulling it high. Also all the I/O pins (even the ones that aren't used > in my program) are all at 5V, but i dont think there is much if any > current on these I/O pins. > > Please can someone advise me. > Does this sound right, if not are there any solutions? > > Conor Carr -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 52698
chris Shaw wrote: > > I'm trying to rebuild an old ABEL file and I don't seem to be able to > get any of the tools - abl2pld, abl2edif, etc - to produce an output > netlist. They all fail from 2.1i to 4.1i. > > What I *do* get is a warning message saying that the tools can't find > some file called Xabel.msg > > Anyone got any ideas ? I'm really stuck & don't want to have to re-write > in Verilog. Abel is still around, just not as visible. What devices / fitters do you need to target ? AFAIK the Xilinx Webpack still has Abel, and the Philips XPLA tools (Pre Xilinx ) also used an Abel variant. Lattice also mention Abel flows. Depending on the device, there is also Atmel WinCUPL, which is quite similar to Abel. -jgArticle: 52699
Hi, XST doesn't "fail" unless there's an error. You seem to have edited the error message out of your post. (Hint: It will have a RED icon next to it.) SH "Xateta" <spanishgirlinireland@yahoo.es> wrote in message news:<b2u30j$12r$1@peque.uv.es>... > Hello, > Im compiling a Verilog Code (XST Verilog) for a Xilinx FPGA (Virtex-E 600) > but the process fails, I dont know why. > > this is what I get: > > Analyzing top module <main>. > WARNING : (VLG__6004). "main.v", line 21: Name conflict (<I> and <i>, > renaming I as i_rnm0). > WARNING : (VLG__4010). "main.v", line 165: The signals <count, clk_index, > PId, IQoutd, PQd, Itemp, IQtemp, addr, i_rnm0, Iin, Q, Qin, eId, eQd, PId2, > PQd2, shift> are missing in the sensitivity list of always block. > Module <main> is correct for synthesis. > Synthesizing Unit <main>. > Extracting 3-bit up counter for signal <count>. > Extracting T flip-flop for signal <IQclk>. > Extracting 10-bit up counter for signal <addr>. > Extracting T flip-flop for signal <clk_index>. > Extracting 12-bit register for signal <Itemp>. > Extracting 12-bit register for signal <Qtemp>. > Extracting 12-bit register for signal <i_rnm0>. > Extracting 12-bit register for signal <Q>. > WARNING : (ADVISOR__0001). Extracting 12-bit latch for signal <IQDAC>. > ....... > ....... > > WARNING : (ADVISOR__0001). Extracting 1-bit latch for signal <eQ<0>>. > Extracting 32-bit 2-to-1 multiplexer for internal node. > Done: failed with exit code: 0002. > > Any help will be very appreciated.Thanks > Laura
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