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Messages from 53575

Article: 53575
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Article: 53576
Subject: FPGA based PCB
From: "Stamatis Sotiropoulos" <ssothro@hotmail.com>
Date: Mon, 17 Mar 2003 10:20:26 +0200
Links: << >>  << T >>  << A >>
Hi all,
    I 'm designing a PCB with a SpartanII Xilinx FPGA (XC2S100- TQ144). The
FPGA will be programmed via JTAG (multilinx cable that operates in 3.3V). If
I use 2.5  Volt power supply for all the FPGA's IOBs, will this be a problem
for the programming? Or the FPGA's JTAG pins are independent from the
internal IO banks and from the external power supply?

Thank you in advance,
Stamatis




Article: 53577
Subject: Re: more footprints...
From: "Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk>
Date: Mon, 17 Mar 2003 09:19:38 -0000
Links: << >>  << T >>  << A >>
> > What is a footprint?
>
> You don't live in snow country I guess.  Think about your foot.
> Then design a PC board to plug yourself into.

So, in the context of FPGAs <cough>, a footprint is the pattern of
pins/connections that the device plugs into - with all of the connections
labelled with their Sunday name.....?

Correct?

Cheers,

Ken



Article: 53578
Subject: Re: Using divided clock
From: Rick Filipkiewicz <rickXYZspamXYZ@mips.com>
Date: Mon, 17 Mar 2003 09:40:36 +0000
Links: << >>  << T >>  << A >>


Falk Brunner wrote:
> "David" <gretzteam@hotmail.com> schrieb im Newsbeitrag
> news:Ts5ba.21118$dN3.344629@weber.videotron.net...
> 
>>Hi,
>>I have a system divided in two parts. One is running at 256Fs and the
> 
> other
> 
>>one at 64 Fs. Is it good practice to use feed the 256Fs clock into a
> 
> counter
> 
>>and use the 2nd lsb to clock the second part of the circuit? In my digital
>>system design class, we have always been told to NEVER clock components
> 
> with
> 
>>anything else than the master clock, and use some logic to enable/disable
>>those components to lower the clock rate. However, after searching in the
>>newsgroup for clock divider, it seems everyone is using a counter as a
> 
> clock
> 
>>divider. What is the best way to do it?
> 
> 
> Do it as you have been told. Use a clock enable, NO derived clock.
> 
> --
> MfG
> Falk
> 
> 
> 
> 

Although this is, in abstract terms, the *correct* solution it contains 
a couple of practical problems:

o Any timing constaints in the "slow" domain will have to be multicycle 
but care & attention will have to be used to make sure these don't in 
some way leak into the slow->fast or fast->slow transition regions.
In general IMHO multicycle constraints are bad news, best avoided.

o Each FF in the slow domain will have to have a global CE control in 
addition to any local one needed i.e.

always @(posedge clk)
   if (local_cond & global_slow_ce)
     ....

under pressure it strikes me that it would be easy to miss this in some 
rarely visited corner of the design that simulation misses and write:

always @(posedge clk)
   if (local_cond)
     ....


As suggested by a previous poster I feel that using a separate "slow" 
clock is a perfectly viable answer as long as:

1. The logic in different domains is separated into different modules. 
More strictly the different domains should have their own hierarchy.

2. a special pair of modules is used to transfer between domains, one 
for each direction. These always operate on the "fast" clock but use a 
clock enable to account for the - fixed/bounded - phase difference 
between the domains. These need to have some magic string in their name 
that survives synthesis and so can be used to pick them out in the 
constraints file.

Note that the actual domain crossing only has to be applied, as usual, 
to a small collection of "valid" signals, not necessarily the whole 
fast/slow i/f.


Article: 53579
Subject: Re: more footprints...
From: "Jonathan Bromley" <jonathan.bromley@doulos.co.uk>
Date: Mon, 17 Mar 2003 09:41:21 -0000
Links: << >>  << T >>  << A >>
"Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote

> So, in the context of FPGAs <cough>, a footprint is the pattern of
> pins/connections that the device plugs into - with all of the connections
> labelled with their Sunday name.....?

Partly correct, at least in every PCB layout package I ever used.

In fairness, many tools let you create a footprint with simple numbered
or labelled pads, and then create a mapping file (in plain text,
puh-leeze!) for relating pins on your schematic symbol to
pads on your footprint.  So you can share the huge and dreary labour
of drawing the package outline across any number of different components
that use the same physical package, regardless of their pinout.
That's kinda neat if you have several identical FPGAs on your board,
all with different functionality and therefore all with different
pin names.  It helps with the "what's this pin called today" problem, too.

O happy days... I haven't done a serious layout job for about five years
now.  My heart goes out to all you poor souls who are trying to get
the signal tracks away from the middle ring of 700-pin BGA packages.
I used to think that 200-pin PQFPs were pretty high-tech stuff :-)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 53580
Subject: Re: RESET --- Synchronous Vs Asynchronous
From: hmurray@suespammers.org (Hal Murray)
Date: Mon, 17 Mar 2003 09:49:01 -0000
Links: << >>  << T >>  << A >>
>Thanks to your hint (also to the response from Ray). I didn't thought about 
>this issue, because I never had problems concerning reset skew. I guess 
>this issue will rise with the newly more complex fpgas. 
>Do you have a rule of thump what size of fpga has this problem?

The size of the FPGA isn't important.  It's the clock speed
relative to the speed of the (async) reset network.

>I know a lot of designs up to XCV1000E with asynch Reset and never heard 
>something about problems during power-on reset.

You have been lucky.

I learned my lesson (the hard way) with a one hot state machine that had
only 4 FFs.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 53581
Subject: Non-integer ratio interpolation and decimation
From: hswnetin@yahoo.com (hswnetin)
Date: 17 Mar 2003 02:02:13 -0800
Links: << >>  << T >>  << A >>
Hi all,

Can anybody tell me about handling clock in multi rate signal
processing? I am working on two-dimensional interpolation and
decimation. Here I have to work on many clocks. So the sampling rate
conversion of this type is difficult to handle in ASIC or FPGA. Please
suggest me the good way of doing this rate conversion. Also please
tell me any algorithm of zero padding for non integer ratio sampling
rate conversion. E.g., converting 3 billion samples per second(bsps)
to 6 bsps is achieved by padding zeros for the half duration of the
clock or the data. This zero padded data is passed through low ass
filter for interpolation. Doing the same for the non-integer ratio
like rate conversion from 3 bsps to 5 bsps is difficult task. Can
anyone tell me about handling this non-integer ratio
interpolation/decimation?

Thanks in advance.

Regards,
hswnetin

Article: 53582
Subject: Modular Design:Fatal error issued by PAR
From: "Eduardo Wenzel Brião" <briao@inf.pucrs.br>
Date: Mon, 17 Mar 2003 04:33:04 -0800
Links: << >>  << T >>  << A >>

Hi. 

In the Place and Route process of the Final Assembly Phase of Modular Design flow, PAR 
tool issued this fatal error below: 

Line command:par -w top_map.ncd top.ncd top.pcf 

Loading device database for application par from file 
"..\..\pims/contador_A/contador_A.ncd". 
   "top" is an NCD, version 2.37, device xc2v1000, package fg456, speed -4 
The STEPPING level for this design is 0. 
FATAL_ERROR:Guide:basgitaskphyspr.c:369:1.17.4.3:137 - Guide encountered a 
   Logic0 or Logic1 signal GLOBAL_LOGIC1_0 that does not have a driver or load 
   within the module boundary. This problem may be caused by having a constant 
   driving the input from outside the module boundary or because a driver or 
   load comp did not meet the par-guiding criteria. The design will not be 
   completely placed and routed by Par-Guide Process will terminate. To 
   resolve this error, please consult the Answers Database and other online 
   resources at http://support.xilinx.com. If you need further assistance, 
   please open a Webcase by clicking on the "WebCase" link at 
   http://support.xilinx.com 

My VHDL Code of reconfigurable module, I have some constants: 

clock : process (reset, clk) 
begin 
if reset='0' 
then pulse <= (others=>'0'); 
displayA_i <= (others=>'0'); 

elsif clk'event and clk = '1' then 
if pulse = x"B71AFF" 
then displayA_i <= displayA_i + '1'; 
pulse <= (others => '0'); 
else pulse <= pulse + '1'; 
if displayA_i = "1010" 
then displayA_i <= (others => '0'); 
end if; 
end if; 
end if; 
end process; 

The numbers below are constants using in my design: 
x"B71AFF" 
'0' 
"1010" 
'1' 

I don´t know if I may to create components with inoperative LUTs to use constants in my design, according 
XAPP290. Could someone help me sending some tips about this subject? Is this fatal error issued because 
of these constants on the VHDL Code of reconfigurable module? 

Eduardo Wenzel Brião 
Catholic University of Rio Grande do Sul State - PUCRS 
Porto Alegre city 
Brazil 





Article: 53583
Subject: Re: Help understanding 7408 and gate chip
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Mon, 17 Mar 2003 14:14:24 +0000
Links: << >>  << T >>  << A >>
On Sun, 16 Mar 2003 06:31:55 GMT, "Glen Herrmannsfeldt"
<gah@ugcs.caltech.edu> wrote:

>
>"Brian Drummond" <brian@shapes.demon.co.uk> wrote in message
>news:ndc17v0bfavtd5u6ivs508og63t23ujauh@4ax.com...
>(snip)
>
>Someone wrote:
>
>> >> By the way this is the wrong NG, and the wrong century.
>> >
>> >Which newsgroup do you suggest, comp.arch.ttl?
>>
>> oh goody...
>>
>> can we have a comp.arch.tube as well?
>
>Oh no.  
Hey, if the rec.audio folks can have one...

>I just remembered that someone I knew some time ago worked on what
>would have been integrated circuit vacuum tubes.  The application was
>ballistic missiles, after it was found that tubes were less sensitive to
>radiation and/or EMP*.
>
>* (not Experience Music Project)

Hehehe... I wonder if an ECC83 (12AU7 "over there"?) counts as an
integrated circuit? Probably not, since the passives are external. Some
of those fancy triode-hexode self oscillating mixers must come close
though.

I confess to being curious about the Binac, which was supposed to be a
usable computer with about 150 active devices. How small can a CPU be?

- Brian

Article: 53584
Subject: Re: Help understanding 7408 and gate chip
From: Ray Andraka <ray@andraka.com>
Date: Mon, 17 Mar 2003 14:21:40 GMT
Links: << >>  << T >>  << A >>
If you do everything  bit serial, pretty small.

Brian Drummond wrote:

> On Sun, 16 Mar 2003 06:31:55 GMT, "Glen Herrmannsfeldt"
> <gah@ugcs.caltech.edu> wrote:
>
> >
> >"Brian Drummond" <brian@shapes.demon.co.uk> wrote in message
> >news:ndc17v0bfavtd5u6ivs508og63t23ujauh@4ax.com...
> >(snip)
> >
> >Someone wrote:
> >
> >> >> By the way this is the wrong NG, and the wrong century.
> >> >
> >> >Which newsgroup do you suggest, comp.arch.ttl?
> >>
> >> oh goody...
> >>
> >> can we have a comp.arch.tube as well?
> >
> >Oh no.
> Hey, if the rec.audio folks can have one...
>
> >I just remembered that someone I knew some time ago worked on what
> >would have been integrated circuit vacuum tubes.  The application was
> >ballistic missiles, after it was found that tubes were less sensitive to
> >radiation and/or EMP*.
> >
> >* (not Experience Music Project)
>
> Hehehe... I wonder if an ECC83 (12AU7 "over there"?) counts as an
> integrated circuit? Probably not, since the passives are external. Some
> of those fancy triode-hexode self oscillating mixers must come close
> though.
>
> I confess to being curious about the Binac, which was supposed to be a
> usable computer with about 150 active devices. How small can a CPU be?
>
> - Brian

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53585
Subject: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
From: "Arash Salarian" <arash dot salarian at epfl dot ch>
Date: Mon, 17 Mar 2003 16:04:50 +0100
Links: << >>  << T >>  << A >>

Have you checked the decoupling capacitors? I had more than one PCB in
the past that the capacitors were the source of VCC-GND shorts....
  "Padraig FitzGerald" <pfitzgerald@conwin.ie> wrote in message
news:ee7c445.-1@WebX.sUN8CHnE...
  Hi,
  I was wondering if anybody had come accross this problem when using
Xilinx FPGA's and if so do they know how to solve it.

  I have just recieved a PCB design back from FAB and We are having an
issue with a short between the VCC and GND planes. This however only
occurs when the Xilinx Spartan XL XCS30 is populated on the board, ie
the short is finding it's way through the silicon of the FPGA.

  Immediately I suspected an error on the footprint of the FPGA but it
was correct, then I thought maybe an IO pin which was externally pulled
up or down was shorted to the opposite level internal to the chip. Ijn
trying to determine this I lifted every pin except the PWR pins and the
short still occurs, so I can categorically say that the short is
iunternal betweent the two levels.

  My question is this.

  Is it possible that when an FPGA leaves the FAB it is configured in
this way? Perhaps for ESD protection??? Does anyone know how to overcome
this problem?

  Padraig




Article: 53586
Subject: LogicLock and SOPC Builder
From: petersommerfeld@hotmail.com (Peter Sommerfeld)
Date: 17 Mar 2003 07:06:59 -0800
Links: << >>  << T >>  << A >>
Has anyone tried using LogicLock with slaves or masters placed using
Altera's SOPC Builder?

Would this be possible?

Thanks for your time.

-- Pete

Article: 53587
Subject: Re: Help understanding 7408 and gate chip
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Mon, 17 Mar 2003 10:19:14 -0500
Links: << >>  << T >>  << A >>
On Tue, 11 Mar 2003 14:15:55 -0500, Niranjandas wrote:

> please find me if DM7408 chip
>  2 input Quad AND gate has ESD diodes(Elesctro static diodes). if yes
>  please let me know.
>  thank you.
> Nidar@rediffmail.com
 
You sparked my curiosity, I did a google search and to my surprise the
7408 in a 14 pin DIP still exists. Fairchild still makes it. 

BTW some of you may be surprised that
Fairchild, the mother of all semiconductor firms, still exists. National,
which swallowed in the 80s, spit it out again in the late 90s.

Why are using a 7408 in a modern design? There are some microscopic cmos
devices available that do this function if you really need a piece of SSI.

Article: 53588
Subject: Re: FPGA dev boards
From: Ken McElvain <ken@synplicity.com>
Date: Mon, 17 Mar 2003 15:46:52 GMT
Links: << >>  << T >>  << A >>

Here is a page listing the board suppliers in the "Partners in
Prototyping" program for Certify.

	http://www.synplicity.com/partners/pip/index.html

I believe that the Hardi board is designed to be stacked.

- Ken



Jerry wrote:

> Tad off subject BUT,
> 
> Does anyone know of a FPGA dev board that can be expanded? I know of the
> DINI group that
> has 5 large FPGAs on it but what I'm looking for is a board that can connect
> to other boards
> in order to expand the gate count.
> 
> Tks in advance
> Jerry
> 
> "Buddy Smith" <nullset@dookie.net> wrote in message
> news:b52kg4$l0c$1@news-int.gatech.edu...
> 
>>Hi,
>>
>>I'm looking to acquire a dev board for xilinx fpgas.  As i'm currently a
>>hobbyist, price is probably my main concern, although i will need a
>>moderate number of gates.
>>
>>Recommendations of models/manufactureres are greatly appreciated.
>>
>>thanks,
>>
>>--buddy
>>
>>
> 
> 


Article: 53589
Subject: PROM for SpartanII Configuration
From: "Stamatis Sotiropoulos" <ssothro@hotmail.com>
Date: Mon, 17 Mar 2003 18:36:33 +0200
Links: << >>  << T >>  << A >>
Hi all,
    I'm using an XC18V01 PROM in order to configurate an XC2S100 (Xilinx
SpartanII FPGA). However, I encounter problems, as the circuit does not work
properly. The EEPROM can be programmed via JTAG, however it cannot then
configurate the FPGA. The XC18V01 operates in 3.3 V and the FPGA in 2.5 V
(2.5 V power supply is used both in the Vcco and Vccint pins of the FPGA).
Is this a problem for the communication of the two ICs?

Thank you in advance






Article: 53590
Subject: new XC95xx global clock
From: =?ISO-8859-1?Q?Ralf_Oberl=E4nder?= <ralf.oberlaender@emsys.de>
Date: Mon, 17 Mar 2003 18:25:25 +0100
Links: << >>  << T >>  << A >>
Hi Gurus,

I have a question related to using devided clock inside XC9572.

-input clock is 48MHz clk48
-I want to devide this clock by 8 => clk6


Can I use clk6 as global clock for a synchronous design in this device.

Thanks in advange
Ralf


Article: 53591
Subject: Re: FPGA dev boards
From: "Paul Baxter" <pauljnospambaxter@hotnospammail.com>
Date: Mon, 17 Mar 2003 18:06:19 -0000
Links: << >>  << T >>  << A >>
www.gidel.com for large ALTERA prototyping


"Jerry" <nospam@nowhere.com> wrote in message
news:v7a83s19pgqj31@corp.supernews.com...
> Tad off subject BUT,
>
> Does anyone know of a FPGA dev board that can be expanded? I know of the
> DINI group that
> has 5 large FPGAs on it but what I'm looking for is a board that can
connect
> to other boards
> in order to expand the gate count.
>
> Tks in advance
> Jerry
>
> "Buddy Smith" <nullset@dookie.net> wrote in message
> news:b52kg4$l0c$1@news-int.gatech.edu...
> > Hi,
> >
> > I'm looking to acquire a dev board for xilinx fpgas.  As i'm currently a
> > hobbyist, price is probably my main concern, although i will need a
> > moderate number of gates.
> >
> > Recommendations of models/manufactureres are greatly appreciated.
> >
> > thanks,
> >
> > --buddy
> >
>
>



Article: 53592
Subject: Re: new XC95xx global clock
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 17 Mar 2003 19:23:35 +0100
Links: << >>  << T >>  << A >>


--
MfG
Falk

"Ralf Oberländer" <ralf.oberlaender@emsys.de> schrieb im Newsbeitrag
news:3E760505.3070000@emsys.de...
> Hi Gurus,
>
> I have a question related to using devided clock inside XC9572.
>
> -input clock is 48MHz clk48
> -I want to devide this clock by 8 => clk6
>
>
> Can I use clk6 as global clock for a synchronous design in this device.

You can, but only if you drive this 6 MHz clock off chip and come back into
on a global clock pad, since AFAIK there is no way to drive a global clock
net in this CPLD from inside (as it is possible with FPGAs).

--
MfG
Falk




Article: 53593
Subject: Re: Using divided clock
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 17 Mar 2003 19:26:32 +0100
Links: << >>  << T >>  << A >>
"Rick Filipkiewicz" <rickXYZspamXYZ@mips.com> schrieb im Newsbeitrag
news:3E759814.30302@mips.com...

[ gated clock stuff ]

Yes, I agree.

--
MfG
Falk





Article: 53594
Subject: Re: FPGA dev boards
From: johnjakson@yahoo.com (john jakson)
Date: 17 Mar 2003 10:27:08 -0800
Links: << >>  << T >>  << A >>
"Jerry" <nospam@nowhere.com> wrote in message news:<v7a83s19pgqj31@corp.supernews.com>...
> Tad off subject BUT,
> 
> Does anyone know of a FPGA dev board that can be expanded? I know of the
> DINI group that
> has 5 large FPGAs on it but what I'm looking for is a board that can connect
> to other boards
> in order to expand the gate count.
> 
> Tks in advance
> Jerry
> 


At the high end (since you said DINI) Nallatech & AlphaData do boards
that have high pin count doughter boards that you could add more FPGA,
A/D or whatever. There are many more companies around, see the 3rd
fpga board lists at xilinx etc.

Article: 53595
Subject: Re: more footprints...
From: Keith R. Williams <krw@attglobal.net>
Date: Mon, 17 Mar 2003 13:29:48 -0500
Links: << >>  << T >>  << A >>
In article <b54418$s18$1@dennis.cc.strath.ac.uk>, aeu96186
_MENOWANTSPAM@yahoo.co.uk says...
> > > What is a footprint?
> >
> > You don't live in snow country I guess.  Think about your foot.
> > Then design a PC board to plug yourself into.
> 
> So, in the context of FPGAs <cough>, a footprint is the pattern of
> pins/connections that the device plugs into - with all of the connections
> labelled with their Sunday name.....?

> Correct?

Not necessarily their Sunday name, because it surely will change on 
Monday. ;-)  

I think I'd just to the layout with their package pin numbers. The 
schematic does the "Sunday name" to physical pin conversion. I wouldn't 
even hard code the power/ground pins because they too can change.  I 
instantiate them all on a page of the schematic and hook them to the 
appropriate voltage there.

-- 
  Keith
 

Article: 53596
Subject: Re: more footprints...
From: Keith R. Williams <krw@attglobal.net>
Date: Mon, 17 Mar 2003 13:37:09 -0500
Links: << >>  << T >>  << A >>
In article <b5456o$92r$1$830fa78d@news.demon.co.uk>, 
jonathan.bromley@doulos.co.uk says...
> "Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote
> 
> > So, in the context of FPGAs <cough>, a footprint is the pattern of
> > pins/connections that the device plugs into - with all of the connections
> > labelled with their Sunday name.....?
> 
> Partly correct, at least in every PCB layout package I ever used.
> 
> In fairness, many tools let you create a footprint with simple numbered
> or labelled pads, and then create a mapping file (in plain text,
> puh-leeze!) for relating pins on your schematic symbol to
> pads on your footprint.

I use an Excel spreadsheet.  I then have all the pin names with color 
coded voltages, IO technologies, partitions on different worksheets in 
the workbook. It really helps to have all this work up-front before the 
schematic is even started.  The information particular to the design 
then gets added as the work progresses.
 
> So you can share the huge and dreary labour
> of drawing the package outline across any number of different components
> that use the same physical package, regardless of their pinout.

Absolutely.

> That's kinda neat if you have several identical FPGAs on your board,
> all with different functionality and therefore all with different
> pin names.  It helps with the "what's this pin called today" problem, too.

Which is why I keep this information in a spreadsheet.  Besides pretty 
spreadsheets impress the boss. ;-)
 
> O happy days... I haven't done a serious layout job for about five years
> now.  My heart goes out to all you poor souls who are trying to get
> the signal tracks away from the middle ring of 700-pin BGA packages.
> I used to think that 200-pin PQFPs were pretty high-tech stuff :-)

It's not so bad at all.  The biggest I've personally done was an FG680, 
but it wasn't all that hard.  I did have 10 layers (5P 5S), but most of 
the stuff wired out on three (designed for 50 ohm) layers.  The FG680 
is nice because it has a large hole in the pattern (really nice for de 
coupling and terminators).

-- 
  Keith

Article: 53597
Subject: Re: Non-integer ratio interpolation and decimation
From: "Kevin Neilson" <kevin_neilson@removethistextattbi.com>
Date: Mon, 17 Mar 2003 18:49:43 GMT
Links: << >>  << T >>  << A >>
I've done irrational rate conversion in an FPGA, in which I had data at the
symbol rate, and a symbol clock, and I had to interpolate by an irrational
(and always-changing) factor to the sample rate clock, which was not
syncrhonous to the symbol rate clock.

If you are doing rational interpolation, things are a lot easier.  For my
irrational interpolation, you will have to approximate the result somehow,
either by using lookup tables to get two results and interpolating between
them or by using something like the Farrow filter to approximate the
interpolation coefficients.

-Kevin

"hswnetin" <hswnetin@yahoo.com> wrote in message
news:a4d4dd49.0303170202.13ccacdd@posting.google.com...
> Hi all,
>
> Can anybody tell me about handling clock in multi rate signal
> processing? I am working on two-dimensional interpolation and
> decimation. Here I have to work on many clocks. So the sampling rate
> conversion of this type is difficult to handle in ASIC or FPGA. Please
> suggest me the good way of doing this rate conversion. Also please
> tell me any algorithm of zero padding for non integer ratio sampling
> rate conversion. E.g., converting 3 billion samples per second(bsps)
> to 6 bsps is achieved by padding zeros for the half duration of the
> clock or the data. This zero padded data is passed through low ass
> filter for interpolation. Doing the same for the non-integer ratio
> like rate conversion from 3 bsps to 5 bsps is difficult task. Can
> anyone tell me about handling this non-integer ratio
> interpolation/decimation?
>
> Thanks in advance.
>
> Regards,
> hswnetin



Article: 53598
Subject: Re: IFDs in Xilinx Foundation 4.1i
From: "Josh Pfrimmer" <yeah_spam_me@thisaddress.com>
Date: Mon, 17 Mar 2003 10:52:08 -0800
Links: << >>  << T >>  << A >>
I'm sorry, I don't understand this.  Do you mean that it is impossible to
infer FFs in an XC4000 (specifically, XC4010XLA) which have an aysnchronous
reset?  If so, I'm afraid you're mistaken.

http://direct.xilinx.com/bvdocs/publications/4000.pdf - Page 7, top,
Set/Reset


JP

"David Binnie" <david.binnie@btinternet.com> wrote in message
news:b55288$6d5$1@helle.btinternet.com...
> 4000 series does not facilitate async reset
>
>
> Josh Pfrimmer <yeah_spam_me@thisaddress.com> wrote in message
> news:b4ret3$22m2l9$1@ID-132015.news.dfncis.de...
> > Hi, all...
> >     I'm TAing a 4th year processor design lab, and despite being very
> > familiar with the tools and VHDL, and having had success in the past,
I've
> > gotten myself stumped on what seems like an extremely simple problem.
I'm
> > hoping the Xilinx/VHDL experts around here can take a minute to point
out
> > my mistake.  I will accept mockery, afterwards, for being dumb, if
that's
> > any incentive.
> >
> > - Using Foundation 4.1i, creating a new project for an XC4010XLA, HDL
> flow.
> > - create a new source file with
> >     - library ieee;
> >     -use ieee.std_logic_1164.all;
> >     -use ieee.std_logic_unsigned.all;
> >     -the appropriate inputs, and only one process:
> >
> > process (clk, rst) is
> > begin
> >     if rst = '1' then
> >         d_out <= '0';
> >     elsif rising_edge(clk) then
> >         d_out <= din;
> >     end if;
> > end process;
> >
> > Just your standard DFF, with asynchronous clear, right?  But every time
I
> > do this, synthesize and simulate, I get the same result: d_out responds
to
> > din just fine, on the rising edge of the clock.  But the reset is
> > ineffectual... no change on dout no matter what the state or activity
on
> > rst.
> >
> > Upon closer examination of the signal hierarchy for dout, I notice that
I
> > the tools have instantiated a IFD, rather than the FDE I expect from
the
> > XC4000 library.  The IFD has no reset, synchronous or otherwise.  Why
> would
> > this get optimized out of the design?  What can I change, in tool
settings
> > or code, to avoid this?
> >
> > Thanks for your time.
> >
> > JP
> >
> > --
> >                 Josh Pfrimmer, B.Eng.
> > _________________________________________
> >  University of Victoria, ECE
> >  jpfrimmer<AT>ece<DOT>uvic<DOT>ca
> > _________________________________________
> > ->My views and opinions are not necessarily UVic's
> >
> >
>
>



Article: 53599
Subject: Re: Help understanding 7408 and gate chip
From: johnjakson@yahoo.com (john jakson)
Date: 17 Mar 2003 10:56:12 -0800
Links: << >>  << T >>  << A >>
>  
> You sparked my curiosity, I did a google search and to my surprise the
> 7408 in a 14 pin DIP still exists. Fairchild still makes it. 
> 
> BTW some of you may be surprised that
> Fairchild, the mother of all semiconductor firms, still exists. National,
> which swallowed in the 80s, spit it out again in the late 90s.
> 
> Why are using a 7408 in a modern design? There are some microscopic cmos
> devices available that do this function if you really need a piece of SSI.

Actually Fairchild was swallowed by Schlumberger which eventually IIRC
dumped it into Nationals hands. Fairchild came out of a management
buyout splitting of the analog & jelly beens biz from NS S.Portland ME
so NS could concentrate on whatever.

Kinda of nice to have that name back as they were the grand daddy of
most every other semiconductor company out there. Most of my career
has been close to x Fairchilders in UK &ME, so plenty of Fairchild
storys to tell.

At one time Fairchild even built a computer (Symbol high level
language architecture) that had the operating system, language
compilers & other SW were built as HW no doubt using lots of 7408s,
this would be in the early 70s, about 20-30yrs before any one here
built SW in HW.

As for the tubes ref, I don't think anybody here is dissing tubes, but
there still here in various forms, this nice monitor in front of me,
FEDs & Plasma displays are all tubes. Some audiophiles swear by them
for their softer clipping of signals.

The Ballistic thing, I thought that Stanford U was working on tiny
ceramic devices a while back that are equiv to tubes, the electrons
are the ballistics. Of course tubes used for Saddam busters are more
EMP resilient not sure how much though.

rambling on



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