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Messages from 53525

Article: 53525
Subject: Re: IFDs in Xilinx Foundation 4.1i
From: "Josh Pfrimmer" <yeah_spam_me@thisaddress.com>
Date: Fri, 14 Mar 2003 17:01:04 -0800
Links: << >>  << T >>  << A >>
oops.. its dout.  I rewrote it from memory, since the current iteration of
the file I'm using to track the problem is a little more complex.... but
when it was just a single flop, like below, it had the same symptoms.

This is a PC lab... windows 2000.  (vcom? vas is das?) The Foundation tools
don't report any syntax errors, and synthsize it without reporting errors
or warnings.

 It's frustrating.  Especially since I can't solve this simple problem, and
my students have to demo a processor to me in 2 weeks.  Has anyone ever had
this problem; Xilinx tools deciding that your design didn't really need an
asynchronous reset?

JP


"Mike Treseler" <tres@fluke.com> wrote in message
news:3E726ABC.4050007@fluke.com...
>
> Is that dout or d_out?
>
> Consider doing at least a "vcom flop.vhd" before synthesizing.
>
>     -- Mike Treseler
>



Article: 53526
Subject: JPEG encoder implementation
From: "Rick" <slshee@yahoo.com.au>
Date: Sat, 15 Mar 2003 12:05:45 +1100
Links: << >>  << T >>  << A >>
Hi,

I am looking for a VHDL/Verilog implementation of a JPEG encoder for
reference.  Do you guys have any idea where I can find one?

Thanks.




Article: 53527
Subject: Re: Adding delay to a signal?
From: Igor Orlovich <igoro@hotmail.com>
Date: Sat, 15 Mar 2003 01:49:58 GMT
Links: << >>  << T >>  << A >>
That's exactly what I ended up doing, but I am still seeing different delays
on the same signal. Time to see if I have any jitter on the clock I guess.


Brian Drummond wrote:

> On Thu, 13 Mar 2003 18:09:37 -0800, Peter Alfke <peter@xilinx.com>
> wrote:
> 
>>Igor,
>>SpartanIIE is like Virtex-E, so it just has a DLL, no phase adjustment.
> 
> Or ... (alternative viewpoint) phase adjustments, but only in 90 degree
> steps. Maybe that would be good enough for the application? Pick the
> nearest 90 degree step, and analyze how close it is to requirements. It
> will be pretty stable across time and temp.
> 
> - Brian
> 
>>> > Igor Orlovich <igoro@hotmail.com> wrote in message
>>> > news:sJRba.8853$Gk2.5234@twister.nyroc.rr.com...
>>> >> I have a project which need sto interface to a system with fairly
>>> >> rigid timing specs. As a result I need to delay my signals coming
>>> >> that way a certain number of nS whiich is not a multiple of any clock
>>> >> I have in the chip.


Article: 53528
Subject: Cypress Users Anyone?
From: "Brad Smallridge" <bsmallridge@dslextreme.com>
Date: Fri, 14 Mar 2003 18:03:58 -0800
Links: << >>  << T >>  << A >>
I just built a board with a 39K100.
Are there any Cypress users in this discussion group?
Brad




Article: 53529
Subject: Re: Help understanding 7408 and gate chip
From: johnjakson@yahoo.com (john jakson)
Date: 14 Mar 2003 18:13:18 -0800
Links: << >>  << T >>  << A >>
nidar@rediffmail.com (Niranjandas) wrote in message news:<4f155288.0303131723.2e93ebed@posting.google.com>...
> thank you john.,
> I am amatuer in this area. i appreciate your time for guiding me. keep
> me posted if you find anyone interested for PhD students for digital
> testing, computer architecture or Computer newtorks.
> By the way what is NG ?
> - Niranjandas M
> 
> johnjakson@yahoo.com (john jakson) wrote in message 
> > Simple bipolar devices like glue logic would'nt need much protection
> > from ESD, its intrinsic to the device, no thin oxides to protect
> > right?. Later on VLSI bipolar did start to get the same type of hard
> > ESD protection as CMOS was getting when the features got to small to
> > wing it.
> > 
> > In fact TTL was so tough as old boots, there are Fairchild stories
> > that Chinese fabs used to make ripoff TTL in fabs where the air
> > conditioning was an open window.
> > 
> > By the way this is the wrong NG, and the wrong century.


News Group where we are

Article: 53530
Subject: Re: IFDs in Xilinx Foundation 4.1i
From: Duane Clark <junkmail@junkmail.com>
Date: Fri, 14 Mar 2003 18:18:28 -0800
Links: << >>  << T >>  << A >>
Josh Pfrimmer wrote:
> oops.. its dout.  I rewrote it from memory, since the current iteration of
> the file I'm using to track the problem is a little more complex.... but
> when it was just a single flop, like below, it had the same symptoms.
> 
> This is a PC lab... windows 2000.  (vcom? vas is das?) The Foundation tools
> don't report any syntax errors, and synthsize it without reporting errors
> or warnings.
> 
>  It's frustrating.  Especially since I can't solve this simple problem, and
> my students have to demo a processor to me in 2 weeks.  Has anyone ever had
> this problem; Xilinx tools deciding that your design didn't really need an
> asynchronous reset?

Assuming you are using the ISE (or Webpack) gui, then there are two 
places which control the packing of FFs into I/O buffers. At least there 
were in version 4.2, so probably also in 4.1.

First, right click on the "Synthesize" heading in the "Processes for 
Current Source" box, click on the "Xilinx Specific Options" tab, and 
there is a selection for "Pack I/O Registers into IOBs".

The second place is the most important one. Right click on "Implement 
Design" and select the "Map Properties" tab. A similar box is selectable 
there.

Of course, the synthesis tool really should not strip out a reset pin. 
At least not without a warning message that should also tell you how to 
prevent it from happening. Perhaps it is assumes you intend an 
asynchronous reset to use the Startup block.

I will just point out that in general, if you are not going to use the 
startup block, I would expect an external reset to be synchronous. But 
perhaps for purposes of a classroom assignment it doesn't matter.

-- 
My real email is akamail.com@dclark (or something like that).


Article: 53531
Subject: Re: About VLCT
From: johnjakson@yahoo.com (john jakson)
Date: 14 Mar 2003 18:20:09 -0800
Links: << >>  << T >>  << A >>
nidar@rediffmail.com (Niranjandas) wrote in message news:<4f155288.0303131733.45938e72@posting.google.com>...
> Is there any one out there who can help me with the VLCT 's ITP
> (interactive tester pascal )program:
> 1) do we need to define VCC and GND pins. if yes, how to do that.
> if no, how to test ICC tests
> 2) can i get a small program covering basic test for a small chip and
> has explanation why they wrote the program the way it is written.
> 3)if i have  a file in MS word how to transfer that to a solaris OS to
> run ITP program.
> cna u debug this program which is done for DM7408 fr leakage tests,
> Voh,Vol,Vih,Vil tests and ICC tests
> thank you
> Niranjandas
> _____________________________

All very well to ask serious engineering related question from
industry, but it takes some nerve to ask so many question which as far
as I can tell do not relate to FPGA.

You should be asking class mates who will be much more familiar with
your assignments.

Still in the wrong NG (news group)

Article: 53532
Subject: Re: Adding delay to a signal?
From: Duane Clark <junkmail@junkmail.com>
Date: Fri, 14 Mar 2003 18:28:11 -0800
Links: << >>  << T >>  << A >>
Igor Orlovich wrote:
> Ray, that's it- that's the answer I was looking for!
> I can simply take my slow clock, run it through DLL, and use 2X or 4X of it
> to register my signals, effectively delaying them by that time. Or I can
> take 2X clock and use both edges to clock the signals out.. And since this
> derived clock will be synchronous to the first clock, my delays will be
> consistent. Thanks for the idea!
> Igor

Your "slow clock"? The SpartanII DLL is speced for a minimum clock of 
20MHz, as I recall.

If you only need a few ns, then running through an unused (and 
unconnected) pin will add delay, and the tools won't strip it out.

Hmmm... Followup-To set to ray@andraka ? Me thinks something is 
misconfigured.

-- 
My real email is akamail.com@dclark (or something like that).


Article: 53533
Subject: Re: Integrating an VHDL component in a project in Handel-C
From: johnjakson@yahoo.com (john jakson)
Date: 14 Mar 2003 18:52:37 -0800
Links: << >>  << T >>  << A >>
gerardo_sr@yahoo.com (Gerardo Sosa) wrote in message news:<f4ee0441.0303131800.6b12ff0f@posting.google.com>...
> Hi, I hope that somebody can help me, because I don't know what more
> to do.
> I'm trying to integrate a VHDL component in a project in Handel-C. 
> DK-1 generate an .edf file and I create a new project in ISE 5 and add
> this .edf, and try to synthesize, but I obtain the following error in
> ISE:
> 
> ERROR:NgdBuild:604 - logical block
> 'B90_reg32x1k_test_98_main_registers' with
>    type 'reg32x1k1' could not be resolved. A pin name misspelling can
> cause
>    this, a missing edif or ngc file, or the misspelling of a type
> name. Symbol
>    'reg32x1k1' is not supported in target 'virtexe'.
> 
> And the interface in Handel-c  for the vhdl component is:
> 
> interface reg32x1k1(unsigned 32 data_out) 
>                registers(unsigned 10 address = addressVal with {extpath
> {registers.data_out}},
>                        unsigned 32 data_in = data_inVal,
>                        unsigned 1 ck = __clock,
>                        unsigned 1 write = writeVal);
> 
> I'm using a RC-1000 Card with XV2000eBG560-6.
> 
> Advanced Thanks for your time
> 
> Gerardo

Looks like homework

Problem with free SW is the tech support really sucks!

But if you did pay, isn't tech support 1st place to go.

JJ

Article: 53534
Subject: Re: IFDs in Xilinx Foundation 4.1i
From: "Josh Pfrimmer" <yeah_spam_me@thisaddress.com>
Date: Fri, 14 Mar 2003 20:34:02 -0800
Links: << >>  << T >>  << A >>
Well, we're not using the ISE tools (maybe next year) but similar options
are available... and they seem to have done the trick.  At least, they're
an acceptable workaround.  Thanks tons!

I'm a little disappointed with the software, though... that workaround is
going to prevent the use of _all_ IOB latches, and that seems needless.
Sneaking flops into IOBs is usually a good way to free up a few CLBs.

Thanks again.  You too, Mike

JP


"Duane Clark" <junkmail@junkmail.com> wrote in message
news:b4u2hl021cc@enews1.newsguy.com...
> Josh Pfrimmer wrote:
> > oops.. its dout.  I rewrote it from memory, since the current iteration
of
> > the file I'm using to track the problem is a little more complex....
but
> > when it was just a single flop, like below, it had the same symptoms.
> >
> > This is a PC lab... windows 2000.  (vcom? vas is das?) The Foundation
tools
> > don't report any syntax errors, and synthsize it without reporting
errors
> > or warnings.
> >
> >  It's frustrating.  Especially since I can't solve this simple problem,
and
> > my students have to demo a processor to me in 2 weeks.  Has anyone ever
had
> > this problem; Xilinx tools deciding that your design didn't really need
an
> > asynchronous reset?
>
> Assuming you are using the ISE (or Webpack) gui, then there are two
> places which control the packing of FFs into I/O buffers. At least there
> were in version 4.2, so probably also in 4.1.
>
> First, right click on the "Synthesize" heading in the "Processes for
> Current Source" box, click on the "Xilinx Specific Options" tab, and
> there is a selection for "Pack I/O Registers into IOBs".
>
> The second place is the most important one. Right click on "Implement
> Design" and select the "Map Properties" tab. A similar box is selectable
> there.
>
> Of course, the synthesis tool really should not strip out a reset pin.
> At least not without a warning message that should also tell you how to
> prevent it from happening. Perhaps it is assumes you intend an
> asynchronous reset to use the Startup block.
>
> I will just point out that in general, if you are not going to use the
> startup block, I would expect an external reset to be synchronous. But
> perhaps for purposes of a classroom assignment it doesn't matter.
>
> --
> My real email is akamail.com@dclark (or something like that).
>



Article: 53535
Subject: Re: Adding delay to a signal?
From: Igor Orlovich <igoro@hotmail.com>
Date: Sat, 15 Mar 2003 04:36:20 GMT
Links: << >>  << T >>  << A >>
Yep, you are right. The min for Spartan IIe is 25Mhz, and in one if the
modes I am feeding  18Mhz in. That could explain some oddities I noticed.
Do  you happen to know how those things behave with slower than specified
clocks?



Duane Clark wrote:

> Igor Orlovich wrote:
>> Ray, that's it- that's the answer I was looking for!
>> I can simply take my slow clock, run it through DLL, and use 2X or 4X of
>> it to register my signals, effectively delaying them by that time. Or I
>> can take 2X clock and use both edges to clock the signals out.. And since
>> this derived clock will be synchronous to the first clock, my delays will
>> be consistent. Thanks for the idea!
>> Igor
> 
> Your "slow clock"? The SpartanII DLL is speced for a minimum clock of
> 20MHz, as I recall.
> 
> If you only need a few ns, then running through an unused (and
> unconnected) pin will add delay, and the tools won't strip it out.
> 
> Hmmm... Followup-To set to ray@andraka ? Me thinks something is
> misconfigured.
> 


Article: 53536
Subject: Re: Cypress Users Anyone?
From: "leon qin" <leon.qin@2911.net>
Date: Sat, 15 Mar 2003 15:29:38 +0800
Links: << >>  << T >>  << A >>
too little people use it.

"Brad Smallridge" <bsmallridge@dslextreme.com> wrote in message
news:v752h71s4uu6c6@corp.supernews.com...
> I just built a board with a 39K100.
> Are there any Cypress users in this discussion group?
> Brad
>
>
>



Article: 53537
Subject: Re: What is the diff between FPGA and CPLD?
From: kolja@bnl.gov (Kolja Sulimma)
Date: 15 Mar 2003 02:35:02 -0800
Links: << >>  << T >>  << A >>
> what is FPGA?. Also what is the difference between FPGA, CPLD and
> ASIC?. Especially the functionality diff between ASIC and FPGA?.
> Thanks in advance.

ASIC is a tecnology to manufacture FPGAs. 

(I here that sometimes it is also used to build other devices such as
microprocessors.)

Kolja Sulimma

Article: 53538
Subject: Re: IFDs in Xilinx Foundation 4.1i
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Sat, 15 Mar 2003 12:36:44 +0000
Links: << >>  << T >>  << A >>
On Fri, 14 Mar 2003 20:34:02 -0800, "Josh Pfrimmer"
<yeah_spam_me@thisaddress.com> wrote:

>Well, we're not using the ISE tools (maybe next year) but similar options
>are available... and they seem to have done the trick.  At least, they're
>an acceptable workaround.  Thanks tons!
>
>I'm a little disappointed with the software, though... that workaround is
>going to prevent the use of _all_ IOB latches, and that seems needless.
>Sneaking flops into IOBs is usually a good way to free up a few CLBs.
>
I can't remember the exact details, but I think it can also be
controlled on a pin by pin basis with user constraints 
(in the .ucf file) - something like 

INST <myFFname> IOB=FALSE;
# keep FF named myFFname out of the IOB

Whether this replaces, overrides or is overridden by the options
previously mentioned is an exercise for the reader ;-)

- Brian

Article: 53539
Subject: Re: Adding delay to a signal?
From: Duane Clark <junkmail@junkmail.com>
Date: Sat, 15 Mar 2003 08:34:22 -0800
Links: << >>  << T >>  << A >>
Igor Orlovich wrote:
> Yep, you are right. The min for Spartan IIe is 25Mhz, and in one if the
> modes I am feeding  18Mhz in. That could explain some oddities I noticed.
> Do  you happen to know how those things behave with slower than specified
> clocks?
> 

As a wild guess, I suspect the minimum clock is determined by the length 
of the digital delay. A 20MHz clock would seem to imply the overall 
length of the digital delay is 50nS.


-- 
My real email is akamail.com@dclark (or something like that).


Article: 53540
Subject: serial transmission between altera's fpga board and PALM?
From: "houman" <abrishamkar@ieee.org>
Date: Sat, 15 Mar 2003 11:41:11 -0500
Links: << >>  << T >>  << A >>
hello all,
i'm trying to establish a serial communication link between my fpga board
(altera) and my palm .
any advice on hardware/software requirements is greatly appreciated.

thanks in advance,

Houman



Article: 53541
Subject: Quality of Xilinx Document
From: qlyus@yahoo.com (qlyus)
Date: 15 Mar 2003 09:00:29 -0800
Links: << >>  << T >>  << A >>
I downloaded and read Xilinx Virtex-II User Guider Rev1.5.  Its LVPECL
section is all talking about xxxx_LVPECL_25.  Is it 3.3V Vccio LVPECL
or 2.5V?

Even this copy&paste section from Virtex-II Pro has other mistakes. 
It says the port signals of IBUFDS_LVPECL_25 are LVDS on pg223.

-qlyus

Article: 53542
Subject: Re: Development boards with optics
From: Andreas Kugel <akugel@t-online.de>
Date: Sat, 15 Mar 2003 21:43:02 +0100
Links: << >>  << T >>  << A >>
Hi there.

If you're looking for a prototyping board you might be interested in one 
of these:

MPRACE:
http://akugel.home.cern.ch/akugel/mpRace/
There is a mezzanine with 2.5GBit (TLK2501 SerDes) and 1.25 GBit (GBE) 
optics available.

RobIn:
https://edms.cern.ch/project/ATL-0000007976/0
then look for documents.
Has same interfaces as above, but tow of the 2.5Gbit links plus an 
electrical GBE.

Both boards are not commercialised yet.
Let me know if you need further information.

Andreas



Patrick MacGregor schrieb:
> I'm looking for FPGA development boards with optics availble.  I could use
> both telecom (OC3/12/48) and datacom (GbE) front-ends.  Does anyone know
> vendors who sell this type of thing?
> 
> 


Article: 53543
Subject: blockram optimized away
From: john_doebertson@yahoo.com (Chip)
Date: 15 Mar 2003 13:58:37 -0800
Links: << >>  << T >>  << A >>
Hello all,

I ran into a problem in a design where my instantiated dual port
blockrams were being optimized away.

I created a very simple example to help explain my problem.

A dual port block ram is created such that data is only written to
port A and only read from port B.

Port A of a Block RAM writes data into memory at addressX.
Port B reads data from memory at addressY.

the data output of of port B is attached with a signal to the data
input of port A. (in my original design this data was actually
modified)

This feedback of an output to an input causes synthesis to remove the
instantiated block ram entirely.  Am I doing something wrong or do I
just need to explicitly tell ISE 5.1 to not optimize my blockrams
away?


Here is the VHDL:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

--library unisim;
--use unisim.vcomponents.all;

entity fbtest is
    Port (	dataW : in std_logic_vector(15 downto 0);  -- port A data
	        	addrW : in std_logic_vector(9 downto 0); -- port A addr
	   		clk : in std_logic;
      	  	addrR : in std_logic_vector(9 downto 0));  -- port b addr
end fbtest;

architecture Behavioral of fbtest is

-- this is simply a wrapped RAMB16_S18_S18
component bram
	port (	dataW :	in std_logic_vector(15 downto 0);
				addrW :	in std_logic_vector(9 downto 0);
				addrR :	in std_logic_vector(9 downto 0);
				dataR :	out std_logic_vector(15 downto 0);
				clk   : in std_logic	);		
end component;

signal feedback_data : std_logic_vector(15 downto 0);

begin

state : bram port map	(	dataW => feedback_data, 
				addrW => addrW,     
				addrR => addrR, 
				dataR => feedback_data, 
			        clk => clk);
end Behavioral;





-- here is the important part of bram.vhd (wrapped RAMB16_S18_S18)

 RAMB16_S18_S18 instantiation copied from ISE 5.1 users guide
.
.
.
	port map (	DOA => open,
				DOB => dataR,
				DOPA => open,
				DOPB => open,
				ADDRA => addrW,
				ADDRB => addrR,
				CLKA => clk,
				CLKB => clk,
				DIA => dataW,
				DIB => "0000000000000000",  --DIB never written
				DIPA => "00",  -- don't care about this now
				DIPB => "00",  -- don't care about this now
				ENA => '1',
				ENB => '1',
				SSRA => '0',
				SSRB => '0',
				WEA => '1',  -- always write
				WEB => '0'); -- always read





Thank in advance,

Chip Lukes

Article: 53544
Subject: Re: blockram optimized away
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Sat, 15 Mar 2003 17:12:38 -0500
Links: << >>  << T >>  << A >>
On Sat, 15 Mar 2003 16:58:37 -0500, Chip wrote:

> Hello all,
> 
> I ran into a problem in a design where my instantiated dual port
> blockrams were being optimized away.
> 
> I created a very simple example to help explain my problem.
> 
> A dual port block ram is created such that data is only written to port
> A and only read from port B.
> 
> Port A of a Block RAM writes data into memory at addressX. Port B reads
> data from memory at addressY.
> 
> the data output of of port B is attached with a signal to the data input
> of port A. (in my original design this data was actually modified)
> 
> This feedback of an output to an input causes synthesis to remove the
> instantiated block ram entirely.  Am I doing something wrong or do I
> just need to explicitly tell ISE 5.1 to not optimize my blockrams away?
>

Is the output of the RAM connected to anything except it's data input? If
there is no logical path to an output pin the logic will be optimized
away.

Article: 53545
Subject: Re: IFDs in Xilinx Foundation 4.1i
From: "Josh Pfrimmer" <yeah_spam_me@thisaddress.com>
Date: Sat, 15 Mar 2003 15:20:31 -0800
Links: << >>  << T >>  << A >>
"Brian Drummond" <brian@shapes.demon.co.uk> wrote in message

>I'm a little disappointed with the software, though... that workaround is
> >going to prevent the use of _all_ IOB latches, and that seems needless.
> >Sneaking flops into IOBs is usually a good way to free up a few CLBs.
> >
> I can't remember the exact details, but I think it can also be
> controlled on a pin by pin basis with user constraints
> (in the .ucf file) - something like
>
> INST <myFFname> IOB=FALSE;
> # keep FF named myFFname out of the IOB
>

Excellent... that's exactly the kind of solution I was looking for.  I'll
give that a shot, when I get some time.

JP



Article: 53546
Subject: Re: Cyclone power up problem - Summery
From: "Jim Granville" <no.spam@designtools.co.nz>
Date: Sun, 16 Mar 2003 11:49:00 +1200
Links: << >>  << T >>  << A >>
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
news:wppca.229368$AV5.2637012@news.chello.at...
> I would like to thank all for their good ideas and help.
>
> I've tested some of the suggested ideas and wrote a little summary with
some
> osci plots. You can find them at:
> http://www.jopdesign.com/cyclone/powerup.jsp

Interesting results.
Observations:

There are two good plots that clearly show 'stalling', one at 400mA, and
another that peaks at
600mA+, and also stalls. This is the 'hard to model behaviour'.
A simple R-C model has some time element, and peak current content, but a
real device is more
charge modeled.

The 'sudden application' plots seem to have (slightly) lower thresholds ?
- perhaps the high dV/dT and spreading inductance allows this to pass the
thresholds in a wave manner ?

It may be that the dV/dT of the applied Vcc affects the required peak
current, and maybe Altera's tests
give lower values because of this ?

Power comments :
2 Diode drop is likely to be marginal - 3.3V -> 1.5V is 1.8V, so that's
asking 900mV per diode.
This is a high number, and diodes have negative tempco of 2.2mV/'C, plus you
need to allow
for 3.3V to be 3.5V - at higher temps, and higher IP vccs, you will
over-supply the core.
 The Vbe multiplier values give appx 3Vbe ( rather than 2 for the diodes ),
but the results show this
cannot start the Cyclone (room temp) - so there is a fine line between
enough kick to start,  and too much Vcc
creep when running.

The simple power supply can be improved with an Augmented Pair darlington :
PNP should have good beta at 1A, and the circuit self-shuts-off if Vassist
is taken above the
emitter follower level, leaving just the R1/R2 current.

 3.3V --------+-------------+
                       |                   e
                       R1        +--b    PNP
                       |            |        c
                       |            c       |
                       +-----b          |
                       |             e----+----------> Vassist
                       |          NPN
                       R2
                        |
                     GND
This is 4 components, and has no thermal or SC protections.

 A vanilla LM317 also looks a good candidate, tho the package is not small
(SOT223 & up)
the data shows :
- it has a 1.2V Vref, close to ideal for assist power of 1.5V FPGA
- the 10mA min Icc is rated for 40V, and drops with lower Vcc
- It can deliver > 1A with appx 2V drop, so can pull to 1.3V from 3.3V Vcc
  Cyclone ( and other FPGA ?) power up does not need the peak current once
Vcc is
over appx 750mV, so the higher priced low dropout 1117 etc families are not
mandatory.

-jg




Article: 53547
Subject: Re: Cyclone power up problem - Summery
From: already5chosen@yahoo.com (Michael S)
Date: 15 Mar 2003 15:51:42 -0800
Links: << >>  << T >>  << A >>
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<wppca.229368$AV5.2637012@news.chello.at>...
> I would like to thank all for their good ideas and help.
> 
> I've tested some of the suggested ideas and wrote a little summary with some
> osci plots. You can find them at:
> http://www.jopdesign.com/cyclone/powerup.jsp
> 
> Regards,
> 
> Martin Schoeberl

Martin,
Did you try to run LTC3405A in the "burst" mode, i.e. with a MODE pin
connected to the GND ?

Article: 53548
Subject: Re: Adding delay to a signal?
From: Ray Andraka <ray@andraka.com>
Date: Sun, 16 Mar 2003 00:04:51 GMT
Links: << >>  << T >>  << A >>
I think the min freq is 25 MHz per the data sheet (although I didn't look).  In
the lab, you'll probably get down to somewhere around 13-14 MHz, but if it is
production I wouldn't go outside of the spec sheet.  Can you use a 2x clock
coming into the FPGA?

Duane Clark wrote:

> Igor Orlovich wrote:
> > Yep, you are right. The min for Spartan IIe is 25Mhz, and in one if the
> > modes I am feeding  18Mhz in. That could explain some oddities I noticed.
> > Do  you happen to know how those things behave with slower than specified
> > clocks?
> >
>
> As a wild guess, I suspect the minimum clock is determined by the length
> of the digital delay. A 20MHz clock would seem to imply the overall
> length of the digital delay is 50nS.
>
> --
> My real email is akamail.com@dclark (or something like that).

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53549
Subject: Re: Cyclone power up problem - Summery
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Sun, 16 Mar 2003 01:21:41 GMT
Links: << >>  << T >>  << A >>

"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag
news:vZOca.5899$8b.682508@news02.tsnz.net...
> "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
> news:wppca.229368$AV5.2637012@news.chello.at...
> > I would like to thank all for their good ideas and help.
> >
> > I've tested some of the suggested ideas and wrote a little summary with
> some
> > osci plots. You can find them at:
> > http://www.jopdesign.com/cyclone/powerup.jsp
>
> Interesting results.
> Observations:
>
> There are two good plots that clearly show 'stalling', one at 400mA, and
> another that peaks at
> 600mA+, and also stalls. This is the 'hard to model behaviour'.
> A simple R-C model has some time element, and peak current content, but a
> real device is more
> charge modeled.

But both are the stalls of the LTC3405, not really the Cyclone. The first
one is where only the LTC3405 is used and it delivers 'what it can' at 0.5
V. The second is the same with additional current from the Vbe multiplier.
>
> The 'sudden application' plots seem to have (slightly) lower thresholds ?
> - perhaps the high dV/dT and spreading inductance allows this to pass the
> thresholds in a wave manner ?
>
> It may be that the dV/dT of the applied Vcc affects the required peak
> current, and maybe Altera's tests
> give lower values because of this ?

I think that the higher dV/dt helps the LTC3405 to 'not see' a short circuit
and continue to switch. The Cyclone needs the current at a minimum voltage
not a so fast dV/dt.

> Power comments :
> 2 Diode drop is likely to be marginal - 3.3V -> 1.5V is 1.8V, so that's
> asking 900mV per diode.
> This is a high number, and diodes have negative tempco of 2.2mV/'C, plus
you
> need to allow
> for 3.3V to be 3.5V - at higher temps, and higher IP vccs, you will
> over-supply the core.

That's the reason for the extra load resistor. But when the Cyclone is
operating and VCCINT goes up the regulator stops and ALL current has to be
delivered by the diodes. Increasing Ud again.

And when VCCINT goes up I expect more current into the FPGA, again Ud goes
down.

But you're right, there is some risk.

>  A vanilla LM317 also looks a good candidate, tho the package is not small
> (SOT223 & up)

I considered this too, but there are two reasons I don't like it. You have
to add an additions tantal co of 10uF for stability. And I'm a little bit
afraid that two integrated regulators (with all those protection) could
result in an unstabile circuit.

Martin

Martin





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