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I guess this is one case where I have no choice- I have no say in what another system does and the interface has been rigid for years, so I am stuck with trying to match the specs Noddy wrote: > From my meagre knowledge of FPGA designs, adding delays to any signals is > bad, bad, bad (a case could probably be argued for use in asynchronous > systems, but I'm not the one to argue it)... what you need is more > handshaking between the two systems. What about doubling your clock speed, > or double edge triggering? > > adrian > > > > Igor Orlovich <igoro@hotmail.com> wrote in message > news:sJRba.8853$Gk2.5234@twister.nyroc.rr.com... >> I have a project which need sto interface to a system with fairly rigid >> timing specs. As a result I need to delay my signals coming that way a >> certain number of nS whiich is not a multiple of any clock I have in the >> chip. Is there any way I can add some propagation delay/gate delay and >> not have it optimized out by the XST tools. Or alternatively, is there a >> way > to >> specify not only the max delay between signals, but also the min one? >> Thanks for any suggestions >>Article: 53476
Hi, I hope that somebody can help me, because I don't know what more
to do.
I'm trying to integrate a VHDL component in a project in Handel-C.
DK-1 generate an .edf file and I create a new project in ISE 5 and add
this .edf, and try to synthesize, but I obtain the following error in
ISE:
ERROR:NgdBuild:604 - logical block
'B90_reg32x1k_test_98_main_registers' with
type 'reg32x1k1' could not be resolved. A pin name misspelling can
cause
this, a missing edif or ngc file, or the misspelling of a type
name. Symbol
'reg32x1k1' is not supported in target 'virtexe'.
And the interface in Handel-c for the vhdl component is:
interface reg32x1k1(unsigned 32 data_out)
registers(unsigned 10 address = addressVal with {extpath
{registers.data_out}},
unsigned 32 data_in = data_inVal,
unsigned 1 ck = __clock,
unsigned 1 write = writeVal);
I'm using a RC-1000 Card with XV2000eBG560-6.
Advanced Thanks for your time
Gerardo
Article: 53477
1) Depends on whta metric you use. If average latency is what is
important, then use the average. If peak latency is important, you use
that. Be aware that average latency may be data dependent, so make sure
your data set is representative. In this case, you'll probably need both
numbers: average to determine the average performance of the system and
max to make sure the system can handle a worst case scenario. It may take
a sizeable effort to determine what a realistic worst case is in the
context of your system.
2) This is usually accomplished with matching delays if the amount of data
in both paths is similar. If it is just one or two samples that need to
be passed around a process thta is producing many samples, then you hold
it in a register (but that is not the usual case). The clock frequency
should match the clock frequency of your process data path, and the
latency should match the data path latency. Normally in hardware DSP the
latency is deterministic, and it is easiest if you try to balance the
latency through all sub paths so that the outputs come at a fixed time.
If they are variable or non-deterministic, you should consider putting a
FIFO in the bypass path.
JDS wrote:
> Hi everybody,
>
> I may have two (2) dummy questions, but I'd like to see how far are my
> thoughts on that.
>
> 1. How do I can measure the performance of DSP block if its processing
> time varies depending of the data itselft? By instantiation of a known
> time response circuit in parallel, i.e., a counter with a strobe
> signal and stop signal coming from the DSP block after it finishes the
> crunching. Can it be used?
>
> 2. Another case: Having two (2) input path to a main logic block; one
> of them is having a secundary combinational logic; and the secundary
> path (or input) does not have any logic at all. How do I synchronize
> the inputs of the main block? Without clock-gating, maybe with many
> pipeline registers on the empty path. Then, how do I determine the
> right number of registers and their clock frecuency. What is the right
> approach?
>
> Again, many thanks friends, and Ray thanks to take from your valuable
> time to allure our lay questions.
>
> JDS
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53478Igor, SpartanIIE is like Virtex-E, so it just has a DLL, no phase adjustment. When you concatenate delays, you must assume >2-to-1 error over temp, voltage and processing. So you only chance is to servo-control this in some way. To measure the artificial delay and adjust it to be a certain portion of something stable, like a clock period. That's effectively ( among other tricks ) what we do in the DCM in Virtex-II. So, put your creative hat on and think about how to build something accurate out of non-precise ingredients ( but with good short-time stability ). Peter Alfke Igor Orlovich wrote: > > I guess this is one case where I have no choice- I have no say in what > another system does and the interface has been rigid for years, so I am > stuck with trying to match the specs > > Noddy wrote: > > > From my meagre knowledge of FPGA designs, adding delays to any signals is > > bad, bad, bad (a case could probably be argued for use in asynchronous > > systems, but I'm not the one to argue it)... what you need is more > > handshaking between the two systems. What about doubling your clock speed, > > or double edge triggering? > > > > adrian > > > > > > > > Igor Orlovich <igoro@hotmail.com> wrote in message > > news:sJRba.8853$Gk2.5234@twister.nyroc.rr.com... > >> I have a project which need sto interface to a system with fairly rigid > >> timing specs. As a result I need to delay my signals coming that way a > >> certain number of nS whiich is not a multiple of any clock I have in the > >> chip. Is there any way I can add some propagation delay/gate delay and > >> not have it optimized out by the XST tools. Or alternatively, is there a > >> way > > to > >> specify not only the max delay between signals, but also the min one? > >> Thanks for any suggestions > >>Article: 53479
While the edges are supposed to line up, and I suppose they would in an ideal
situation, it is not that hard to create a situation where there is enough skew to
cause a problem. We ran into this when the 2.5v Virtex was fairly new. In our case,
the 2x clock was lightly loaded and the 1x was heavily loaded, the incoming clock had
a fair amount of jitter on it, and the pins near the clock input were outputs driving
memories. The outputs toggling modulate the clock input threshold adding additional
jitter. Turns out the DLLs can exhibit a substantial skew (a couple hundred ps) when
the input clock has a lot of jitter. We also had a couple of places where the signal
crossing the clock domain boundary went directly from a flip-flop Q to a flip-flop D
without passing through a LUT and routed on a direct route. This combination of
things got us to a situation where there was enough clock skew that the data was
beating the clock and messing things up on us. Ever since then, one of our check
points before releasing a design is to ensure that the data is not clocked on the
same supposedly aligned edges. For 1x to 2x, it means making a clock enable in the
2x domain so that the 1X signal is only sampled away from the active edge of the 1x
clock, and for 2x to 1x, same type of deal to make the 2x output change coincident
with the inactive edge of the 1x clock. Takes a bit more care, but not really much
more logic.
Tullio Grassi wrote:
> Peter Alfke wrote:
> > The classical well-behaved method is to use only one (global) clock, and
> > use a derived clock enable signal to make sure that the other part only
> > operates on every fourth clock cycle.
> > The price is slightly higher clock power consumption (provided you could
> > lay out the circuit such that you don't run the fast clock all over the place).
> >
> > If you use a derived clock, then you end up with two slightly staggered
> > time domains, which can bite you whenever there is data exchange between
> > the two domains. ( The obvious loss of performance due to a late-clokced
> > register driving data into an early-clocked one. The more devious case
> > is the early-clocked register driving data into the late-clocked
> > register, violating hold time requirements, and creating a
> > race-condition mess.)
> >
> > Single clock synchronous is best in 99% of the cases...
> >
>
> I have a similar case: a bring into a Virtex2 a 40 MHz clock
> and I multiply it by 2 (80MHz) with a DLL.
> For system reasons, I prefere to have 2 domains
> clocked by DLL outpus CLK0 and CLK2X.
> There is a unique module where data flow from the 80 MHz
> to the 40 MHz domain.
> Now, the documentation says that the outputs of the DLL
> are well aligned with the input (provided CLKFB is used).
> No matter how good the DLL is, there is a small mis-alignement
> between CLK0 and CLK2X. On top of that the separate distribution
> networks of the 2 clock increase the mis-alignement (skew).
>
> The question is if the skew
> is smaller then the clock-to-Q time of the flip-flops.
> I couldn't find it on the data sheet.
> The system seems to run fine in actual hardware,
> but I haven't done reliability studies.
>
> Thanks for commenting,
> --
>
> Tullio Grassi
>
> ======================================
> Univ. of Maryland - Dept. of Physics
> College Park, MD 20742 - US
> Tel +1 301 405 5970
> Fax +1 301 699 9195
> ======================================
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53480On Thu, 13 Mar 2003 07:05:08 -0600, "ArtO" <arm777@(spam-not)sockets.net> wrote: >Can anyone tell me some spechs for AMD processors in terms of heat ranges. >I plan on building a system with a 2200 or 2400 CPU and a GeForce4200 video >card. At this point I am trying to find a case. I like the Antec Sonata, >but am a little concerned about heat dissapation with only one (though >large) fan. > Don't sweat it. If you use a tbred, a single rear fan (I'm using a plain 80mm one) and using a power supply with a bottom intake will be plenty. I'm using a 2100+ with a 4200 and the temps are fine. StaceyArticle: 53481
Yeah.... I did that today.... CRS Mike Treseler wrote: > Clyde R. Shappee wrote: > > Is this kind of what you have in mind? I have been doing synchronous > > resets for a while, but based on your post, I bullet proofed it a little... > > Here is a component that takes an asynchronous reset and asserts it > > asynchronously, but deasserts it synchronously. > > Yes. That's what I had in mind. > If you fix up the :in and :out on the ports, > it will even compile. > > -- Mike TreselerArticle: 53482
You could use the clock DLLs to get a 4x clock in the 2E. Since you are dealing
with apparently vintage hardware, that should give you enough flexibility to get
around the hold time requirement. The spartan2E only has a DLL, not a DCM so
you don't have the same amount of flexibility. You could also use a purpose
made delay line or clock skew buffer (such as a Cypress roboclock) outside of
the chip in extreme cases to generate a skewed clock if you can't work out a
synchronous solution within the FPGA. Don't be tempted into using gates for
delay, the min and max times are spread far enough apart that about all you can
guarantee is that it will not be reliable when you go to production. This is
true regardless if you've taken the extra step to hand route them to guarantee
the routing delays are equal (I don't advocate that either except where
absolutely necessary...lets just say out of well over 100 high performance FPGA
designs, I can count on one hand the times I've needed to do any hand routing)
Igor Orlovich wrote:
> Is there anything similar in Spartan IIE?
> This is again that same much discussed in this ng problem of another system
> requiring the data to show up so many nanoseconds after the clock edge.
> I did try creating a delay block by sticking a bunch of inverters with keep
> attributes set, but I can't seem to get the same delay among different
> instances. I presume creating a netslist macro is a solution, but am not
> sure how that is done.
>
> Peter Alfke wrote:
>
> > In Virtex-II you can specify a clock delay of n/256 of the clock period
> > ( limited to a granularity of ~50 picoseconds ). That solves your problem.
> > For most other delays the ratio between max and min is >2, which makes
> > any compensation attempts pretty useless.
> >
> > Peter Alfke, Xilinx Applications
> > =====================
> > Igor Orlovich wrote:
> >>
> >> I have a project which need sto interface to a system with fairly rigid
> >> timing specs. As a result I need to delay my signals coming that way a
> >> certain number of nS whiich is not a multiple of any clock I have in the
> >> chip. Is there any way I can add some propagation delay/gate delay and
> >> not have it optimized out by the XST tools. Or alternatively, is there a
> >> way to specify not only the max delay between signals, but also the min
> >> one? Thanks for any suggestions
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53483
Hi, all...
I'm TAing a 4th year processor design lab, and despite being very
familiar with the tools and VHDL, and having had success in the past, I've
gotten myself stumped on what seems like an extremely simple problem. I'm
hoping the Xilinx/VHDL experts around here can take a minute to point out
my mistake. I will accept mockery, afterwards, for being dumb, if that's
any incentive.
- Using Foundation 4.1i, creating a new project for an XC4010XLA, HDL flow.
- create a new source file with
- library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-the appropriate inputs, and only one process:
process (clk, rst) is
begin
if rst = '1' then
d_out <= '0';
elsif rising_edge(clk) then
d_out <= din;
end if;
end process;
Just your standard DFF, with asynchronous clear, right? But every time I
do this, synthesize and simulate, I get the same result: d_out responds to
din just fine, on the rising edge of the clock. But the reset is
ineffectual... no change on dout no matter what the state or activity on
rst.
Upon closer examination of the signal hierarchy for dout, I notice that I
the tools have instantiated a IFD, rather than the FDE I expect from the
XC4000 library. The IFD has no reset, synchronous or otherwise. Why would
this get optimized out of the design? What can I change, in tool settings
or code, to avoid this?
Thanks for your time.
JP
--
Josh Pfrimmer, B.Eng.
_________________________________________
University of Victoria, ECE
jpfrimmer<AT>ece<DOT>uvic<DOT>ca
_________________________________________
->My views and opinions are not necessarily UVic's
Article: 53484Hi, How can store complex numbers into ROM.I am using Core generator to design my ROM.Also ,the values are to be loaded into ROM after calculation.I am need it for FFT transform, and the ROM stores the coefficients.Thanx.Article: 53485
Ray, that's it- that's the answer I was looking for! I can simply take my slow clock, run it through DLL, and use 2X or 4X of it to register my signals, effectively delaying them by that time. Or I can take 2X clock and use both edges to clock the signals out.. And since this derived clock will be synchronous to the first clock, my delays will be consistent. Thanks for the idea! Igor Ray Andraka wrote: > You could use the clock DLLs to get a 4x clock in the 2E. Since you are > dealing with apparently vintage hardware, that should give you enough > flexibility to get > around the hold time requirement. The spartan2E only has a DLL, not a DCM > so > you don't have the same amount of flexibility. You could also use a > purpose made delay line or clock skew buffer (such as a Cypress roboclock) > outside of the chip in extreme cases to generate a skewed clock if you > can't work out a > synchronous solution within the FPGA. Don't be tempted into using gates > for delay, the min and max times are spread far enough apart that about > all you can > guarantee is that it will not be reliable when you go to production. This > is true regardless if you've taken the extra step to hand route them to > guarantee the routing delays are equal (I don't advocate that either > except where absolutely necessary...lets just say out of well over 100 > high performance FPGA designs, I can count on one hand the times I've > needed to do any hand routing) > > Igor Orlovich wrote: > >> Is there anything similar in Spartan IIE? >> This is again that same much discussed in this ng problem of another >> system requiring the data to show up so many nanoseconds after the clock >> edge. I did try creating a delay block by sticking a bunch of inverters >> with keep attributes set, but I can't seem to get the same delay among >> different >> instances. I presume creating a netslist macro is a solution, but am not >> sure how that is done. >> >> Peter Alfke wrote: >> >> > In Virtex-II you can specify a clock delay of n/256 of the clock period >> > ( limited to a granularity of ~50 picoseconds ). That solves your >> > problem. For most other delays the ratio between max and min is >2, >> > which makes any compensation attempts pretty useless. >> > >> > Peter Alfke, Xilinx Applications >> > ===================== >> > Igor Orlovich wrote: >> >> >> >> I have a project which need sto interface to a system with fairly >> >> rigid timing specs. As a result I need to delay my signals coming that >> >> way a certain number of nS whiich is not a multiple of any clock I >> >> have in the chip. Is there any way I can add some propagation >> >> delay/gate delay and not have it optimized out by the XST tools. Or >> >> alternatively, is there a way to specify not only the max delay >> >> between signals, but also the min one? Thanks for any suggestions > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 53486
"Peter Alfke" <peter@xilinx.com> news:3E6CF17F.D49C95E1@xilinx.com... > > The classical well-behaved method is to use only one (global) clock, and > use a derived clock enable signal to make sure that the other part only > operates on every fourth clock cycle. > The price is slightly higher clock power consumption (provided you could > lay out the circuit such that you don't run the fast clock all over the place). > > If you use a derived clock, then you end up with two slightly staggered > time domains, which can bite you whenever there is data exchange between > the two domains. ( The obvious loss of performance due to a late-clokced > register driving data into an early-clocked one. The more devious case > is the early-clocked register driving data into the late-clocked > register, violating hold time requirements, and creating a > race-condition mess.) > > Single clock synchronous is best in 99% of the cases... > > Peter Alfke, Xilinx Applications I would like to adopt single clock for the whole design. However, it's hard to leverage the whole Spartan IIE to run at the high speed, for example, 160M. I thought it'd be difficult to meet the timing constraint for the entire chip with the clock-enable mechanism. So I designed my high speed interface module at 160M, and the others at 20M (1/8). The 20M was derived by counter. Do you have any other suggestion?Article: 53487
Hi, Peter Alfke <peter@xilinx.com> wrote > But the trailing edge will not reach all flip-flops at the same time, > since it is not distributed with low skew,( and even if it were, its > arrival could still straddle a clock edge). > So you inevitably end up with some, but not all flip-flops staying reset > beyond a certain clock edge. This can have bad consequences, especially > in one-hot state machines ( just as an example). Thanks to your hint (also to the response from Ray). I didn't thought about this issue, because I never had problems concerning reset skew. I guess this issue will rise with the newly more complex fpgas. Do you have a rule of thump what size of fpga has this problem? I know a lot of designs up to XCV1000E with asynch Reset and never heard something about problems during power-on reset. bye ThomasArticle: 53488
Hi, If you type the command vsim just tag on the term -noglitch, if you invoke via the menus look for turn off glitch detection or something like that. Best Regards Andre' "Y Varma" <queryplease@netscape.net> wrote in message news:3E712995.7070504@netscape.net... > Hi Andre' > > I could not find the simulation options page to set No Glitch - could > you please give me a pointer. > > Thanks a bunch. > > > > Andre Powell wrote: > > HI Lijo, > > If you are simulating with Modelsim you can turn off the glitch detection > > using -noglitch as one of the simualation options. > > > > Best Regards > > > > Andre' > > "LIJO" <lijo_eceNOSPAM@hotmail.com> wrote in message > > news:b4hhdm$1u7l6h$2@ID-159866.news.dfncis.de... > > > >>Hi all, > >> I am trying to implement a logic into FPGA. I have functionally verified > >>the logic and have synthesised the logic and verfied the post synthesis > >>simulation output. > >>After Implementation I have done the Timing Simulation with SDF files and > >>have found a lot of invalid transitions between transition from one valid > >>state to another valid state. I have no idea why this happens.. Is there > > > > any > > > >>problem if I download the code to the FPGA . Will it work properly. > >> > >>Please see the attached file. > >> > >>thanks > >>Lijo > >> > >> > >> > > > > > > >Article: 53489
On Fri, 14 Mar 2003 06:20:53 +0000 (UTC), Thomas Stanka <thomas@stanka-web.de> wrote: >Hi, > >Peter Alfke <peter@xilinx.com> wrote >> But the trailing edge will not reach all flip-flops at the same time, >> since it is not distributed with low skew,( and even if it were, its >> arrival could still straddle a clock edge). >> So you inevitably end up with some, but not all flip-flops staying reset >> beyond a certain clock edge. This can have bad consequences, especially >> in one-hot state machines ( just as an example). > >Thanks to your hint (also to the response from Ray). I didn't thought about >this issue, because I never had problems concerning reset skew. I guess >this issue will rise with the newly more complex fpgas. >Do you have a rule of thump what size of fpga has this problem? Any FPGA that has more than 1 flip flop potentially has this problem. >I know a lot of designs up to XCV1000E with asynch Reset and never heard >something about problems during power-on reset. Most of the time you get lucky. I estimate that for the designs I work on, > 99.9% of the flip flops aren't particularly sensitive to the power up state or the skew of the reset signal. It's the 0.1% that are sensitive that you have to worry about. I usually use synchronous resets for those. Regards, Allan.Article: 53490
"Thomas Stanka" <thomas@stanka-web.de> escribió en el mensaje news:Xns933E4AC0B5B2Fthomasstankawebde@129.143.4.1... > Thanks to your hint (also to the response from Ray). I didn't thought about > this issue, because I never had problems concerning reset skew. I guess > this issue will rise with the newly more complex fpgas. > Do you have a rule of thump what size of fpga has this problem? > I know a lot of designs up to XCV1000E with asynch Reset and never heard > something about problems during power-on reset. > > bye Thomas > I thought power-on reset was always safe. There is the configuration step, after which you come to an stable state. The trouble would be with an external asynchronous reset signal. The problem should become more visible in systems with fast clock. Please, someone correct me if I am wrong Josep.Article: 53491
Igor Orlovich wrote: > I have a project which need sto interface to a system with fairly rigid > timing specs. As a result I need to delay my signals coming that way a > certain number of nS whiich is not a multiple of any clock I have in the > chip. Is there any way I can add some propagation delay/gate delay and not > have it optimized out by the XST tools. Or alternatively, is there a way to > specify not only the max delay between signals, but also the min one? > Thanks for any suggestions > Just in case your're already at the upper end of the clock and need some delay. There is the AD9501, an analog delay from Analog Devices. At a repetition rate of 50MHz or so it allows a digitally settable delay with down to 10ps increments on a 8 bit value. The slope is defined by an RC. It allows to delay a rising slope. Meaning to create an arbitrary pulse you need 2 of these devices and 4 lines plus a flip flop. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 53492
There are sytems to be controlled without handshake. We had a system : A laser makes a pulse with a length of 0.1ps every 10ns. No we had to get every 1234567th pulse or so for further experiments. Since the detector for the pulses is placed somewhere and the device to cut the pulse from the stream somewhere else, though in close proximity, there was the need for a delay. The counter had some delay, the cutter, a high voltage unit delivering 5kV within few ns had also delays. Not to forget that the light does 1m every 3ns. We used AD9501 digitally controlled analog delays. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net Noddy wrote: > From my meagre knowledge of FPGA designs, adding delays to any signals is > bad, bad, bad (a case could probably be argued for use in asynchronous > systems, but I'm not the one to argue it)... what you need is more > handshaking between the two systems. What about doubling your clock speed, > or double edge triggering? > > adrian > > > > Igor Orlovich <igoro@hotmail.com> wrote in message > news:sJRba.8853$Gk2.5234@twister.nyroc.rr.com... > >>I have a project which need sto interface to a system with fairly rigid >>timing specs. As a result I need to delay my signals coming that way a >>certain number of nS whiich is not a multiple of any clock I have in the >>chip. Is there any way I can add some propagation delay/gate delay and not >>have it optimized out by the XST tools. Or alternatively, is there a way >>to specify not only the max delay between signals, but also the min one? >>Thanks for any suggestionsArticle: 53493
I tend to consider them a bit steep too. Yes, i could use a flash and be concerned on how to load it. I once spent a few day gathering information on how it could be done and found for low volume, the configuration circuits are the cheapest solution. Rene Kolja Sulimma wrote: > For 15€ you get a Fujitsu micrcontroller with 256KByte Flash. > For 30€ you get a 64MHz, 32-Bit Processor with 768kB Flash. > Price for a single piece, no lead time. > > You can write your own software to make it JTAG-programmable, or you > implement PPP and upload your bitstreams via FTP ;-) > > Does anybody besides me think that the FPGA configuration flash-ROMs > are overpriced? > > Kolja Sulimma > > zumbita00@yahoo.es (Pepito Perez) wrote in message news:<441d2f16.0303121138.568f4a23@posting.google.com>... > >>Hello, >> >> I bought while ago two FPGA from Altera, they are called APEX and >>ACEX, their distributor sent me both FPGA, but... they came without >>memory, i have talked to them and they said they could sell me memory, >>and it is almost as expensive as FPGA. They gave me this prices: >> >>EPC1PC8 or EPC2LC20 for EP1K50,(ACEX) >>EPC2LC20 for EP1K100.(APEX) >> >>EPC2LC20.Altera >>-price 21,59 eu. >>- This one is JTAG programable. >> >>EPC1PC8.Altera. >>-price 7,12 eu. >> >>Are this good prices ? Add sending and taxes...its in euro, almost >>like dollar. >> >>Anyways, it's the first time i buy this things, i don't know if they >>are being nice or being too smart...what do you think ? >> >>Could I use another memory for my FPGA ? What tipe would you recommend >>me ? >> >>Thank you ! > -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 53494
"Hari" <natara@eng.fsu.edu> schrieb im Newsbeitrag news:10629fcf.0303131911.6791b0a3@posting.google.com... > Hi, > How can store complex numbers into ROM.I am using Core generator to > design my ROM.Also ,the values are to be loaded into ROM after > calculation.I am need it for FFT transform, and the ROM stores the > coefficients.Thanx. ???? Homework? A complex number is just a pair of "normal" numbers. So all you need to do is to store these two numbers. You can do this in parallel (using two ROMS) or interleave them. -- MfG FalkArticle: 53495
what sort of voltage should i expect to see at the VCC_SENSE (pin 15) of the DB-25 parallel connector? "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<b4qdq2$2142ne$1@ID-84877.news.dfncis.de>... > "Giuseppe³" <miaooaim@inwind.it> schrieb im Newsbeitrag > news:b4q49b$227b6i$1@ID-61213.news.dfncis.de... > > > > I fix a similar problem with IJC-2 JTAG cable in the follow mode: > > > > In my board I've put a capacitor of 100pF nearest the TDO pin. > > Then I've open the JTAG interface and remove the capacitor labeled C1. > > > > In my opinion the R9-C1 filter is too big. > > IMHO the schematics of the parallel-III cable is a little bit senseless. I > added two Schmitt triggers (74HC14) BEFORE the TCK line. The input to the > first schmitt-trigger is filterd by a RC filter consisting of 330 Ohms and 1 > nF. This works well on a 3m long cable. Since there are 4 more buffers free > inside the chip, I buffer TDI and TMS the same way. But TCK (which becomes > CCLK in serial slave mode) is by far the most critical signal. So keep the > connetion from the 74HC125 (tristate driver) to the TCK pin on the board > short, lets say < 10cm (4 inch for the non-SI guys ;-)Article: 53496
On Fri, 14 Mar 2003 10:21:59 +0100, "j" <j.duran@teleline.es> wrote: > >"Thomas Stanka" <thomas@stanka-web.de> escribió en el mensaje >news:Xns933E4AC0B5B2Fthomasstankawebde@129.143.4.1... > >> Thanks to your hint (also to the response from Ray). I didn't thought >about >> this issue, because I never had problems concerning reset skew. I guess >> this issue will rise with the newly more complex fpgas. >> Do you have a rule of thump what size of fpga has this problem? >> I know a lot of designs up to XCV1000E with asynch Reset and never heard >> something about problems during power-on reset. >> >> bye Thomas >> > >I thought power-on reset was always safe. There is the configuration step, >after which >you come to an stable state. It would only be safe if the reset was deasserted before the clocks start to transition, which isn't usually the case. The internal reset may be released before or after the DLLs lock. Look at the bitgen -g option for details. Regards, Allan.Article: 53497
On Thu, 13 Mar 2003 18:09:37 -0800, Peter Alfke <peter@xilinx.com> wrote: >Igor, >SpartanIIE is like Virtex-E, so it just has a DLL, no phase adjustment. Or ... (alternative viewpoint) phase adjustments, but only in 90 degree steps. Maybe that would be good enough for the application? Pick the nearest 90 degree step, and analyze how close it is to requirements. It will be pretty stable across time and temp. - Brian >> > Igor Orlovich <igoro@hotmail.com> wrote in message >> > news:sJRba.8853$Gk2.5234@twister.nyroc.rr.com... >> >> I have a project which need sto interface to a system with fairly rigid >> >> timing specs. As a result I need to delay my signals coming that way a >> >> certain number of nS whiich is not a multiple of any clock I have in the >> >> chip.Article: 53498
i find a problem after read this problem
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
#include "nios.h"
void main (void)
{
int c;
printf("please enter a character:\n");
while((c=nr_uart_rxchar(nasys_printf_uart))==-1);
printf("Your character is:\t%c\n",c);
}
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
First,i want NIOS to read my data in the file "in.txt"
and output to the file "out.txt"
i think it should use "uart" to do it
i try many times but i couldn't success
could any one help me
thanks a lot
my c problem are as follow
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
#include <stdio.h>
void main(void)
{
FILE *in,*out;
in=fopen("in.txt","r");
out=fopen("out.txt","w");
int x;
fscanf(in,"%d",&x);
fprintf(out,"%d",x);
}
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
Sincerely Yours!
Article: 53499Hello, In parity generator block in my PCI design, how should i implement parity generation parallelly ie x(0) xor x(1) xor(2).......x(36); or do f1:=x(0) xor x(2) nine each; f2:=nine each f3:=nine each; f4:=nine each; f5:=f1 xor f2 xor f3 xor f4; which is the better way????so that i can check the parity generated with the PAR signal coming in the next clock
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