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Messages from 53900

Article: 53900
Subject: Re: triple des
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Wed, 26 Mar 2003 23:58:07 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <qhptod8z8e.fsf@ruckus.brouhaha.com>,
Eric Smith  <eric-no-spam-for-me@brouhaha.com> wrote:
>nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes:
>> And probably nobody has used it in a system where there is a >$100k
>> payout if you can break this particular form of security, 
>
>Actually, if you can break 3DES you can get a ***MUCH*** larger payout
>than that.  The banking industry uses 3DES for their transactions.  So
>the incentive to develop an effective means of breaking 3DES is quite
>high.
>
>Either no one has done it yet, or they're keeping quiet.

I'm not talking about breaking 3DES, I'm talking about breaking the
bitfile security, which uses 3DES for the encryption.

Breaking the security relies on extracting (mostly, with errors
allowed) the encryption key stored in SRAM.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 53901
Subject: xilinx/modelsim simulate a subsystem ?
From: eric_usenet@yahoo.com (Eric)
Date: 26 Mar 2003 18:40:03 -0800
Links: << >>  << T >>  << A >>
Is there any way to route and simulate a half-complete design ? I'd
love to P&R an d then simulate a subsystem of my design, but the rest
of it isn't implemented yet, and this portion of the design would
require too much off-chip IO to synthesize in my target-sized device
by itself. I.e. the subsystem has input ports A, B, C, and D, all of
which will be connected to other portions of the design (inside the
FPGA), but which exceed the external IO capabilities of the device. Am
I just out of luck? or is there a way use ModelSim XE / ISE5.1 to do a
post P&R sim of a subsystem by itself ?


        ...Eric

Article: 53902
Subject: Differential LVPECL Inteface of Spartan IIE
From: Wang Xiao-yun <wangxy@fudan.ANTISPAM.edu>
Date: Thu, 27 Mar 2003 10:59:38 +0800
Links: << >>  << T >>  << A >>
Gurus,
I'm considering using differential LVPECL interface of Spartan IIE.
Based on the information provided in XAPP133, the interface requires no 
termination voltage or DC bias as normal ECL circuits do. On the other 
hand, a PI resistor network is suggested on the transmitter side (to 
perform a voltage-division function, if I understand correctly).

My first question is wether the res. network is necessary for LVPECL 
interconnection between Spartan IIE FPGA's.

Second, will it be more power-saving to apply a VCCO-2V voltage with 2 
50E resistors as receiver termination?

Thanks in advance.


Article: 53903
Subject: Re: FPGA FFT Questions
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 27 Mar 2003 03:22:30 -0000
Links: << >>  << T >>  << A >>
>> If the spectrum is fairly flat, then it makes sense to clip because
>> the information is kept in the least significant bits.
>> But if you're expecting large spikes in the frequency domain
>> then it is wise to shift and drop the LSB.

>This point is far from obvious to me.

[Begin handwave.]

Consider conservation of energy.

When you do an FFT, you take N samples in time and transform them
into N samples in frequency.  Each sample in either view of the
signal represents some energy.  The totals will be equal.

Suppose the input samples are a perfect sine wave with a peak that
is close to full scale.  What will the output samples look like?
Roughly, all the energy gets dumped into one slot, so it has to
have enough bits to hold the sum of the input bins.  [Mumble,
think RMS and power rather than voltage...]  So you need more
bits in that output slot, and since you don't know which slot
it will land in you probably want more bits in all the output
slots.

I'm far from a DSP wizard, but I've been exposed to some of this
stuff.  (It's neat and weird.)  You might get more info by hanging
out in the dsp newsgroup.

You can do similar weird things with an oversampling D/A using
information rather than energy to convince yourself that you
can get more than N bits of information from an N bit D/A.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 53904
Subject: help! How can I make the messages posted in this group be sent to my E-mail box.
From: qiu.xiaoyong@zte.com.cn (wosiqiu)
Date: 26 Mar 2003 19:47:00 -0800
Links: << >>  << T >>  << A >>
I hope that the messages posted in this group can be sent to my E-mail
box, But I can't find how . Could anybody help me? Thansk.
Best Rgds.
Qiuxy

Article: 53905
Subject: Re: Increased Wafer yield by row adjusted placement
From: johnjakson@yahoo.com (john jakson)
Date: 26 Mar 2003 19:57:29 -0800
Links: << >>  << T >>  << A >>
> 
> You'd break too many in the process, which nullifies the advantage.
> Besides, you can't just nilly willy offset the rows against each other
>...
> 
> Achim.

You raise some good points. Its not just Xilinx, could be any company
making relatively huge dies on wafer that might be optimised as long
as they are high value. Maybe Itaniums, probably not P4s.

It's certainly true that a diamond wheel couldn't do this process with
out 1st spliting the wafer into partial blocks that are all manhatten,
so now it becomes a 2 step process with varying size pieces, probably
a big headache, but I don't think impossible, depends on the holding
platform. I was under the impression that lasers were once used, its
been along time, I still remember the rolling pin technology.

Fab less foundries probably don't want to be seen to be stepping on
the fabs business, maybe, but then again if it were my wafers, & they
could be split as suggested, I'd give it a try, if its my business
that loses 10%. Also I don't think the fabs necessarily organize
anything after the wafer is done, last time I handled a wafer tray I
was taking it from foundry to packaging house both chosen by asic
design shop. We could have used mickey mouse for all the foundry
cared.

The more dificult issue I forgot to mention was that the masks would
have to be stepped in this slightly less regular way, and would
probably limit the field to 1 die so stepping and sometimes jogging,
something the steppers might not want to do.

Same goes for test probe stepping. Now alot more parties are involved.

>There is none off grid. I see two shots that have a process monitor 
>inset middle left and right and another inset lower left and upper 
>right, possibly with a different design. What you mistake for an 
For the xcv1000 sure, never even looked at that, it gives up 2 sites
for test, apart from that, no extra sites look possible.

I was referring to the 1st copper picture, still a 2 by 2 cell at top
is offset, only 1 can be good, still looks like the same as others to
me.

> Is it necessary to use the same final process for $10 parts v parts 
> that could be worth several thousand $. 

I would go much further, the wafer breaking process probably came out
of TI or NS along time ago, one of the jelly been companies during the
heydey of msi so as much automation had to be in place to handle these
literally 2c chips.

So an ancient 2c process is being used to break up $6K parts. Lets not
shake the boat.

Along the same lines lets not use that 45deg routing process, or lets
ignore the idea of combining critical masks onto 1 mask (see recent
EET) to halve mask set costs.

During my 20yrs in this biz, there have been many crazy suggestions &
technologies brought to bare, I certainly never thought I needed 2
layers of Al, but I am sure glad we now 8+ of Cu. There have been
thousands of process changes in that time.


> more costly than it already is. Ten percent of ten percent of the
> product cost just doesn't justify taking many risks.

uhha, I don't get that one, 10% extra yield for me goes straight to
the bank, why does it get diluted to 10% of 10% etc. Fancy packages,
testing are expensive, but I am sure the biggest dies are much more
so.

Its just an idea, run it up the flagpole see if anyone salutes.

JJ

Article: 53906
Subject: Re: Differential LVPECL Inteface of Spartan IIE
From: "sanjay" <sanjay@cg-coreel.com>
Date: Thu, 27 Mar 2003 11:49:26 +0530
Links: << >>  << T >>  << A >>
Hi,
Answer to your first question.
Why we need a termination? To ensure that all pins are getting some pull up
or Pull down current, so that it will not go into high impedance or any
undefined state before configuring the device. The Termination Res. network
given in App Note 133 is by considering the Spartan -II E Device
Characteristics all together. It gives a Min. High and Low Identification on
the pin.
So its recommended not to change it.

Secondly you asked  with Vcco of 2 V and 50 Ohm Termination, Logically
speaking it should give Power saving. But this VCCOof 2V is not supported on
Spartan -IIE for LVEPCL.

Thanks
Sanjay

"Wang Xiao-yun" <wangxy@fudan.ANTISPAM.edu> wrote in message
news:b5tped$1q1q$1@mail.cn99.com...
> Gurus,
> I'm considering using differential LVPECL interface of Spartan IIE.
> Based on the information provided in XAPP133, the interface requires no
> termination voltage or DC bias as normal ECL circuits do. On the other
> hand, a PI resistor network is suggested on the transmitter side (to
> perform a voltage-division function, if I understand correctly).
>
> My first question is wether the res. network is necessary for LVPECL
> interconnection between Spartan IIE FPGA's.
>
> Second, will it be more power-saving to apply a VCCO-2V voltage with 2
> 50E resistors as receiver termination?
>
> Thanks in advance.
>



Article: 53907
Subject: Re: Translating 2 CLKDLLs for SpartanII architecture
From: "sanjay" <sanjay@cg-coreel.com>
Date: Thu, 27 Mar 2003 11:59:17 +0530
Links: << >>  << T >>  << A >>
Hi Chris,
Can you  send me the VHD Instatiation of DLL and UCF syntax you have used to
lock it.
R u using any IBUFG?
If it is, Pls. remove it.

Thanks
Sanjay

"CSchuster" <nospam@gmx.de> wrote in message
news:hkrr5b.si2.ln@yodel.asimus.de...
> I'm working on a design for the SpartanII architecture. Everything worked
> fine and I was able to simulate, synthesize, translate and work with the
> design. because of performance issues I had to use the CLKDLLs (standard
> design from Xilinx/ask Sparty) to quadruple (x4) the clock. From the
moment
> I instanciated the DLLs I encounter error messages on pins that I am sure
> that they are correct:
>
> ERROR:NgdBuild:455 - logical net 'spdsel' has multiple drivers
> ERROR:NgdBuild:466 - input pad net 'spdsel' has illegal connection
>
> Also, when I try to constraint the two DLL's used to certain locations,
the
> translator exits on the lines with the constrains. He tells me that the
DLLs
> i instanciated can not be found. Does anyone have any idea how to get this
> issues solved?
>
> I really apreciate your help,
>
> Chris
>
>



Article: 53908
Subject: Re: xilinx/modelsim simulate a subsystem ?
From: Spam Hater <spam_hater_7@email.com>
Date: Thu, 27 Mar 2003 06:33:30 GMT
Links: << >>  << T >>  << A >>

Easy.

Start a new ISE project.

Add the module you want to RTL simulate as type 'module'.  And its
submodules too.

Add ALL the rest as type 'testbench'.  ISE does not check for
synthesizable code in the test benches.

And away you go.

SH

On 26 Mar 2003 18:40:03 -0800, eric_usenet@yahoo.com (Eric) wrote:

>Is there any way to route and simulate a half-complete design ? I'd
>love to P&R an d then simulate a subsystem of my design, but the rest
>of it isn't implemented yet, and this portion of the design would
>require too much off-chip IO to synthesize in my target-sized device
>by itself. I.e. the subsystem has input ports A, B, C, and D, all of
>which will be connected to other portions of the design (inside the
>FPGA), but which exceed the external IO capabilities of the device. Am
>I just out of luck? or is there a way use ModelSim XE / ISE5.1 to do a
>post P&R sim of a subsystem by itself ?
>
>
>        ...Eric


Article: 53909
Subject: Re: Anyone have difficulty downloading this core?
From: "Hans" <hansydelm@no-spam-ntlworld.com>
Date: Thu, 27 Mar 2003 08:54:05 -0000
Links: << >>  << T >>  << A >>
Works fine for me, nice core!!

Hans.
www.ht-lab.com

"Alex Rast" <ad.rast.7@nwnotlink.NOSPAM.com> wrote in message
news:93499217Eadrastnwnotlinkcom@216.168.3.44...
> http://www02.so-net.ne.jp/~morioka/cqpic.htm
>
> Supposedly a PIC16F84 implementation in VHDL. Version 1.00b appears to be
> downloadable on the site. But when I click the link, I get the following:
>
> "Forbidden
> You don't have permission to access /fb3/morioka/pic100a/cqpic100b.exe on
> this server."
>
> i.e. the standard no-access message. Are others running into this? If so,
> is there some other location from which I can download? Or is it somehow
> something in my environment that I need to change in order to download
> successfully?
> --
> Alex Rast
> ad.rast.7@nwnotlink.NOSPAM.com
> (remove d., .7, not, and .NOSPAM to reply)



Article: 53910
Subject: Re: Altera EPXA1 Development Kit - problems with the GNUPro Insight
From: Franz Hollerer <nospam@nospam.org>
Date: Thu, 27 Mar 2003 10:50:06 +0100
Links: << >>  << T >>  << A >>
Hi Nathan,

Thanks. This is a good idea.

I also posted a support request to your (Altera) company
and I got slightly different but also interesting answer:

 > You can debug your code from the start of the program by
 > making sure that you do not start the processor running
 > code when you download it to the board.  In the X! Getting
 > Started design you download code to the board using the
 > "prog_hw.bat" file.  If you open this file you will see that it
 > uses a function called exc_flash_programmer to download the design
 > to the board.  One of the flags passed to this function is "-g".
 > The "-g" flag tells the flash programmer to start the processor
 > running after you have downloaded the code.  In your case syou
 > should delete the -g option from the prog_hw.bat file and then
 > reprogram the board.  Now the code will not run automatically.
 > You can then open GDB and bein debugging from the beginning of the
 > main.c file.

Best regards,
Franz

Nathan Knight wrote:
> Hello Franz,
> 
> We've found the easiest way to start your debugging from the beginning
> of main using GDB is to put a small conditionally compiled "while
> (spin == 1);" statement right up at the top of main.  This will stop
> your software here when the board is reset, and give you time to fire
> up GDB.  You can then change the spin variable in GDB and go on with
> your debugging.
> 
> If you try to restart while GDB is connected, there can be problems
> because the bootloader does some memory map manipulation that will
> likely confuse the debugger.  The elf file you load into GDB does not
> match the context of the board until the bootloader finishes, so it's
> not until that point that you'll want to load the elf file.  Using the
> spin-loop mentioned above allows the bootloader to finish booting the
> board, then lets you start GDB and load the elf file before the real
> software on the board starts running.
> 
> Hope this helps.
> 
> Regards,
> 
> -Nathan Knight
> Altera Corp.
> 
> Franz Hollerer <nospam@nospam.org> wrote in message news:<newscache$s59bch$gp41$1@news.sil.at>...
> 
>>Hi,
>>
>>I now found that I can use the gdb to interrupt the already
>>downloaded an running hello example and go from this point step by step.
>>
>>If I set a breakpoint at main() and restart the program gdb says:
>>
>> > Error: You can't do that without a process to debug.
>>
>>What does this message mean? How can I use the gdb to restart
>>the program to allow debuging from the very begin of the program?
>>
>>Best regards,
>>Franz Hollerer
>>
>>
>>Franz Hollerer wrote:
>>
>>>Hi,
>>>
>>>I try to experiment with the "hello" example described in the
>>>Altera Excalibur EPXA1 Development Kit - Getting Started User Guide.
>>>
>>>I want to use the GNUPro Debugger to debug the program. I can
>>>start the debugger as described in the document, but setting
>>>breakpoints, single steps etc. does not work.
>>>
>>>Are there some restrictions for using the gdb? e.g. Ram, Flash?
>>>
>>>Best regards,
>>>Franz
>>>


Article: 53911
Subject: Re: FPGA specs
From: Bernd Paysan <bernd.paysan@gmx.de>
Date: Thu, 27 Mar 2003 11:15:49 +0100
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> That is weird, and I am sure Marketing ( for all its other foibles) is
> not responsible for this stupidity.  I also do not believe that this
> silly method is part of FPGA gate counting.
> When I was involved, we reduced everything to 2-input gates, and a 2-XOR
> became 4 gates.

The more or less best utilization you can get out of a FPGA LE is a full 
adder and a flip flop with asynchronous set or reset (or two of them for 
Xilinx LC). I looked into one cell library, and these two count as 16 NAND2 
gates (size, not transistor count); I used a scannable flip-flop, since 
this is often required for testing, to blow up the number of gate 
equivalents.

Unfortunately, this best case is not the usual case. Many flip-flops in 
FPGAs are unused, and the logic table also is often used in a much simpler 
way. A multiplexer (2.3 gate equivalents) already consumes a complete LE. 
FPGA producers also count the SRAM cells as "gates". I don't know how many 
gate equivalents they use, but my SRAM cell is the size of 0.5 NAND2 gates.

-- 
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://www.jwdt.com/~paysan/

Article: 53912
Subject: Re: Differential LVPECL Inteface of Spartan IIE
From: Wang Xiao-yun <wangxy@fudan.ANTISPAM.edu>
Date: Thu, 27 Mar 2003 18:25:12 +0800
Links: << >>  << T >>  << A >>
Hi, Sanjay,
Thanks for your post, but I beg to differ.

A termination is used to ensure the signal integrity on a transmission 
line instead of providing bias current. In a true (P)ECL interface, I 
don't think the res. network suggested in the XAPP133 will work, because 
the supposed emitter-follower outputs do not have a current path to the 
bias voltage. (of course, Xilinx might include bias resistors inside the 
chip, but I don't think it's available in Spartan 2E)
Based on my understanding, striping out the PI network on the 
transmitter side will only increase the signal swing seen by the 
receiver. In another word, Voh and Vol will be even improved without the 
PI. The PI may also serve to absorb the reflection resulted from the 
impedance mismatch, but I don't think it's the main purpose.
The only purpose for the PI seems only to tweak the voltage swing within 
PECL spec. to interface with other standard devices, but will the 
Spartan 2E receiver require the trick? That's what I want to know.

For the second question, I may not have stated clearly. I would like to 
know wether a termination of 50ohm to VCCO - 2V (nominally 1.3V in the 
case of LVPECL) is also fine for the buffer, instead of supplying 2V to 
VCCO.

Thanks.

sanjay wrote:
> Hi,
> Answer to your first question.
> Why we need a termination? To ensure that all pins are getting some pull up
> or Pull down current, so that it will not go into high impedance or any
> undefined state before configuring the device. The Termination Res. network
> given in App Note 133 is by considering the Spartan -II E Device
> Characteristics all together. It gives a Min. High and Low Identification on
> the pin.
> So its recommended not to change it.
> 
> Secondly you asked  with Vcco of 2 V and 50 Ohm Termination, Logically
> speaking it should give Power saving. But this VCCOof 2V is not supported on
> Spartan -IIE for LVEPCL.
> 
> Thanks
> Sanjay
> 


Article: 53913
Subject: Re: Translating 2 CLKDLLs for SpartanII architecture
From: sanket@insight.memec.co.in (Xilinx FAE from Insight SANKET)
Date: 27 Mar 2003 05:07:02 -0800
Links: << >>  << T >>  << A >>
Hi Chris,

Your answer lies in the below link assuming that you are using
XST.Even otherwise the below link will help you debug your problem.

http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=13206

Also hand place the DLLs in Floorplanner and check the outcome.


Also check below for the exact way of coding .

_______________________________________________

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity dll_standard is
    port (CLKIN : in  std_logic;
          RESET : in  std_logic;
          CLK2X : out std_logic;
          CLK4X : out std_logic;
          LOCKED: out std_logic);
end dll_standard;

architecture structural of dll_standard is

signal CLKIN_w, RESET_w, CLK2X_dll, CLK2X_g, CLK4X_dll, CLK4X_g :
std_logic;
signal LOCKED2X, LOCKED2X_delay, RESET4X, LOCKED4X_dll : std_logic;
signal logic1 : std_logic;

begin 

logic1 <= '1';

clkpad : IBUFG  port map (I=>CLKIN, O=>CLKIN_w);
rstpad : IBUF   port map (I=>RESET, O=>RESET_w);

dll2x  : CLKDLL port map (CLKIN=>CLKIN_w,   CLKFB=>CLK2X_g,
RST=>RESET_w,
                          CLK0=>open,   CLK90=>open, CLK180=>open,
CLK270=>open,
                          CLK2X=>CLK2X_dll, CLKDV=>open,
LOCKED=>LOCKED2X);

clk2xg : BUFG   port map (I=>CLK2X_dll,   O=>CLK2X_g);

rstsrl : SRL16  port map (D=>LOCKED2X, CLK=>CLK2X_g,
Q=>LOCKED2X_delay,
                          A3=>logic1, A2=>logic1, A1=>logic1,
A0=>logic1);

RESET4X <= not LOCKED2X_delay;

dll4x  : CLKDLL port map (CLKIN=>CLK2X_g,  CLKFB=>CLK4X_g,
RST=>RESET4X,
                          CLK0=>open,   CLK90=>open, CLK180=>open,
CLK270=>open,
                          CLK2X=>CLK4X_dll, CLKDV=>open,
LOCKED=>LOCKED4X_dll);


clk4xg : BUFG   port map (I=>CLK4X_dll,  O=>CLK4X_g);
lckpad : OBUF   port map (I=>LOCKED4X_dll, O=>LOCKED);

CLK2X <= CLK2X_g;
CLK4X <= CLK4X_g;

end structural;
___________________________________________________________________________

I hope the above shall solve your problem.
Regards,
SANKET.




"sanjay" <sanjay@cg-coreel.com> wrote in message news:<b5u5mr$2dak72$1@ID-164436.news.dfncis.de>...
> Hi Chris,
> Can you  send me the VHD Instatiation of DLL and UCF syntax you have used to
> lock it.
> R u using any IBUFG?
> If it is, Pls. remove it.
> 
> Thanks
> Sanjay
> 
> "CSchuster" <nospam@gmx.de> wrote in message
> news:hkrr5b.si2.ln@yodel.asimus.de...
> > I'm working on a design for the SpartanII architecture. Everything worked
> > fine and I was able to simulate, synthesize, translate and work with the
> > design. because of performance issues I had to use the CLKDLLs (standard
> > design from Xilinx/ask Sparty) to quadruple (x4) the clock. From the
>  moment
> > I instanciated the DLLs I encounter error messages on pins that I am sure
> > that they are correct:
> >
> > ERROR:NgdBuild:455 - logical net 'spdsel' has multiple drivers
> > ERROR:NgdBuild:466 - input pad net 'spdsel' has illegal connection
> >
> > Also, when I try to constraint the two DLL's used to certain locations,
>  the
> > translator exits on the lines with the constrains. He tells me that the
>  DLLs
> > i instanciated can not be found. Does anyone have any idea how to get this
> > issues solved?
> >
> > I really apreciate your help,
> >
> > Chris
> >
> >

Article: 53914
Subject: Re: Virtex II pro board design question
From: mrand@my-deja.com (Marc Randolph)
Date: 27 Mar 2003 05:08:55 -0800
Links: << >>  << T >>  << A >>
Theron Hicks <hicksthe@egr.msu.edu> wrote in message news:<3E81D568.6D7D0B32@egr.msu.edu>...
> Marc Randolph wrote:
> 
> >
> > To answer your concern, I would not spend any time worring about the
> > I/O pins themselves - there is no problem with fully utilizings the
> > I/Os.
> >
[...]
>  Also, routing that many i/o pins could be a little tight especially when you are routing 100% of the
> pins.  It certainly will increase the number of layers (and cost).  You will want to be very careful in selecting
> a PCboard fab house.  See the hardware user guide for more info.  Also see Answer Record # 13572.
> 

Theron has a point.  If the OP is very senstitive to cost, layout
complexity and layer count can push up cost - and that didn't really
cross my mind because the company I work for has an excellent layout
group, and we just accept the fact that it takes at least four routing
layers (plus power and ground layers - we typically do two of each) to
route out of a 600-700 pin FPGA.

As for SSO, that it *could* be an issue.  But at the same time, any
design could have that problem - it isn't limited to the design could
use a large percentage of the I/O's in only one bank on a 256 pin part
and have SSO problems.  My (perhaps slightly unclear) point was that,
if designed correctly, the I/O's can be fully utilized and should not
be the limiting factor of the design.

Have fun,

   Marc

Article: 53915
Subject: SCSI LVDS and VirtexE
From: "L. Nguyen" <nguyenld@perkinselectronics.com>
Date: Thu, 27 Mar 2003 07:11:22 -0800
Links: << >>  << T >>  << A >>
Hi all, 

I remember there were few posts before about implemeting LVDS 
for SCSI interface in VirtexE. Some also pointed out that the SCSI LDVS is asymetrical (because the termination) and it may cause the VirtexE LVDS less noise immunity on SCSI bus. 

My question is does the VirtexE really work? If so how fast one can achieve? Since I am thinking of a SCSI interface using VirtexE, Fast-160 is the speed I interest at. 

Thanks folks, 




Article: 53916
Subject: Re: Translating 2 CLKDLLs for SpartanII architecture
From: "CSchuster" <nospam@gmx.de>
Date: Thu, 27 Mar 2003 16:17:32 +0100
Links: << >>  << T >>  << A >>
Hi Sanjay,

The hint with the IBUFGs was essential. As soon as I took the IBUFGs out,
the problems with the other IOs where solved.
Also, the issue with the not found DLLs in the UCF file are history. It
seems like the hirarchies are flattened, so that the names were put together
from the toplevel design and the lower instances: "dllx4_dll_dll2x" instead
of "dllx4_dll/dll2x".

Thank you so much,
Chris

"sanjay" <sanjay@cg-coreel.com> schrieb im Newsbeitrag
news:b5u5mr$2dak72$1@ID-164436.news.dfncis.de...
> Hi Chris,
> Can you  send me the VHD Instatiation of DLL and UCF syntax you have used
to
> lock it.
> R u using any IBUFG?
> If it is, Pls. remove it.
>
> Thanks
> Sanjay
>
> "CSchuster" <nospam@gmx.de> wrote in message
> news:hkrr5b.si2.ln@yodel.asimus.de...
> > I'm working on a design for the SpartanII architecture. Everything
worked
> > fine and I was able to simulate, synthesize, translate and work with the
> > design. because of performance issues I had to use the CLKDLLs (standard
> > design from Xilinx/ask Sparty) to quadruple (x4) the clock. From the
> moment
> > I instanciated the DLLs I encounter error messages on pins that I am
sure
> > that they are correct:
> >
> > ERROR:NgdBuild:455 - logical net 'spdsel' has multiple drivers
> > ERROR:NgdBuild:466 - input pad net 'spdsel' has illegal connection
> >
> > Also, when I try to constraint the two DLL's used to certain locations,
> the
> > translator exits on the lines with the constrains. He tells me that the
> DLLs
> > i instanciated can not be found. Does anyone have any idea how to get
this
> > issues solved?
> >
> > I really apreciate your help,
> >
> > Chris
> >
> >
>
>



Article: 53917
Subject: Modular Design: level of module hierarchy
From: "Eduardo Wenzel Brião" <briao@inf.pucrs.br>
Date: Thu, 27 Mar 2003 07:42:22 -0800
Links: << >>  << T >>  << A >>
I make few small designs over modular design flow. I can create these and these work without any problem. But when I wanna create a bigger project, do Modular Design of ISE5.1 package
supports more than two levels of module hierarchy? Do the current version of Modular Design (ISE5.1) allow a module include another module without problems? 

Eduardo Wenzel Brião 
Catholic University of Rio Grande do Sul state 
Porto Alegre city 
Brazil 



Article: 53918
Subject: Re: How failures happen, and how they don't
From: Michael Garvie <mmg20@cogs.susx.ac.uk>
Date: Thu, 27 Mar 2003 16:22:04 +0000
Links: << >>  << T >>  << A >>
Given your FIT rates for high temperature, high moisture, electrical
overstress, or purely random; what is the fault mode induced?  Are these
localized and permanent?  Or do they go away with scrubbing?  Or are
they at the FPGA subsystem level?
Regards,
Miguel

Austin Lesea wrote:

> I suggest that if you have suddenly experienced a failure, that is the
> kind of failure known as "random" and fits well within our FIT rate
> predictions.
>
> As everyone knows, failures do happen, and if the designers, industry
> and foundries could prevent that from happening, we would all be
> happier when we have to design fail-safe systems.
>
> So, until then, fail safe systems fail, by failing to fail safely.
>
> Austin


Article: 53919
Subject: constant on Maxplus2
From: ebereau@radiocom.spm.univ-rennes1.fr (Eleonore Bereau)
Date: 27 Mar 2003 08:23:34 -0800
Links: << >>  << T >>  << A >>
hello,

On the software maxplus+ II, I try to use the symbol "constant" of the
"maxplus2\max2lib\prim" library in a graphic description file (.gdf).

I give a name on the left of the symbol, init[9..0] for example, a value on
the right, 1111111111 for example, and I try to affect the constant on an
output (output symbol of the prim library) named CST[3..0] to have 10
bits on this output.
The output is connected to a bus line named init[9..0];

When I compil, I have always error message like "node missing source" 

What is the syntax for use this symbol 

Thank you for your help.

Eleonore

Article: 53920
Subject: Modular Design: level of module hierarchy
From: "Eduardo Wenzel Brião" <briao@inf.pucrs.br>
Date: Thu, 27 Mar 2003 08:27:17 -0800
Links: << >>  << T >>  << A >>
Can I use the for-generate statement to create adders inside a module in the Module Design flow? Do it allow several instances of the same module (since my modules are inside another modules
(three level of hierarchy)(see diagram)? 

top 
| 
|-->module_Adder_4_bits 
           | 
           |-->for generate 
                adder1bit 4 times 

Eduardo Wenzel Brião 
Catholic University of Rio Grande do Sul state 
Porto Alegre city 
Brazil 




Article: 53921
Subject: Tristate pins + Inputs => External Pullup ?
From: rrr@ieee.org (Rajeev)
Date: 27 Mar 2003 08:30:46 -0800
Links: << >>  << T >>  << A >>
People,

I could use a little help, maybe I'm just not thinking about this
clearly...

When an FPGA pin is tri-stated (high-Z), is the input buffer for
that pin connected or disconnected to the pin ?  

What I'm thinking is: if it's connected, the pin may float to a voltage where
the input buffer draws high current, and I had better provision the pin with
an external pullsup/down.

(Families of interest to me are: Spartan2, 2E, Stratix.)

Thanks for your help,
-rajeev-

Article: 53922
Subject: DSP-FPGA interface
From: iidigoras@ikerlan.es (ii)
Date: 27 Mar 2003 08:31:37 -0800
Links: << >>  << T >>  << A >>
Hello,

I have to design a control board with a TI DSP (C67xx). For providing
some peripherals (PWM generation, encoder read) I will use a Xilinx
FPGA.

My concern is how to connect both of them. The DSP has the EMI block,
where the FPGA could be connected, as a memory mapped device.

What are the best design practices for synchrous design? Do I use the
same clock for both devices? or different ones? how can I synch them?

Use the FPGA's built-in DPRAM or build registers?

I have searched for this kind of info but did not find much helpful
info. There have also been discussions on this group, but I was not
able to have a clear image.

Any advise will be welcome. Thanks for your help.

Article: 53923
Subject: Re: DSP-FPGA interface
From: "Mike Shonle" <mike@psychonic.net>
Date: Thu, 27 Mar 2003 11:52:11 -0500
Links: << >>  << T >>  << A >>
Why not use one of the TI dsp chips with built-in PWM & encoder reading,
like the 320F2407?


"ii" <iidigoras@ikerlan.es> wrote in message
news:80ddf5b.0303270831.530da142@posting.google.com...
> Hello,
>
> I have to design a control board with a TI DSP (C67xx). For providing
> some peripherals (PWM generation, encoder read) I will use a Xilinx
> FPGA.
>
> My concern is how to connect both of them. The DSP has the EMI block,
> where the FPGA could be connected, as a memory mapped device.
>
> What are the best design practices for synchrous design? Do I use the
> same clock for both devices? or different ones? how can I synch them?
>
> Use the FPGA's built-in DPRAM or build registers?
>
> I have searched for this kind of info but did not find much helpful
> info. There have also been discussions on this group, but I was not
> able to have a clear image.
>
> Any advise will be welcome. Thanks for your help.



Article: 53924
Subject: Re: Tristate pins + Inputs => External Pullup ?
From: Allan Herriman <allan_herriman.hates.spam@agilent.com>
Date: Fri, 28 Mar 2003 04:05:02 +1100
Links: << >>  << T >>  << A >>
On 27 Mar 2003 08:30:46 -0800, rrr@ieee.org (Rajeev) wrote:

>People,
>
>I could use a little help, maybe I'm just not thinking about this
>clearly...
>
>When an FPGA pin is tri-stated (high-Z), is the input buffer for
>that pin connected or disconnected to the pin ?  

Connected.

>What I'm thinking is: if it's connected, the pin may float to a voltage where
>the input buffer draws high current, and I had better provision the pin with
>an external pullsup/down.

Yes, that's right.    It usually takes some microseconds for the
signal to float into the transition region, so if you are driving the
signal more often than that, you may not need the pullup or pulldown.

OTOH, the extra current may be within your power budget, and you may
not need to worry at all.


Note: if you are referring to *unused* pins, there is a weak pullup
enabled (by default) inside the FPGA  that neatly avoids this issue.

Regards,
Allan.



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