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Messages from 54575

Article: 54575
Subject: Re: fpga fault tolerence.
From: cvmnk@yahoo.com (naveen)
Date: 14 Apr 2003 08:58:53 -0700
Links: << >>  << T >>  << A >>
hi,
 i meant all the list of the faults. doent matter if its before
testing or after testing.
   i lnow some of them but iam writing a paper on "diagnosis and fault
tolerence of FPGA's", i dont want to miss ne of them.
  thanks,
 naveen
nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message news:<b770oe$171v$1@agate.berkeley.edu>...
> In article <b7f5eb6a.0304110842.4abb46a8@posting.google.com>,
> naveen <cvmnk@yahoo.com> wrote:
> >hi,
> >  can ne one lemme know all the different faults on FPGA, both
> >interconect and logical faults, on Xilinx based FPGA's.
> > thankin you in advance,
> 
> What do you mean? Soft errors vs hard errors?  From the fab (before
> testing) or after testing?

Article: 54576
Subject: configuration file
From: cvmnk@yahoo.com (naveen)
Date: 14 Apr 2003 09:08:11 -0700
Links: << >>  << T >>  << A >>
Hi,
   iam working on "DIAGNOSIS AND FAULT TOLERENCE OF FPGA's"
   in all the papers related to these fields they say that different
multiple configurations are to b used to deal with the faults on
FPGA's.
   my questionS ARE
     1) HOW TO WRITE A CONFIGURATION FILE?
     2) WAT ARE THE CAD TOOLS WHICH WRITE THE CONFIGURATION FILES?
     3) CAN WE EDIT CONFIGURATION FILE MANUALLY?
     4) HOW CAN I LOCATE CONFIGURATION FILE ON XILINS FPGA's I MEAN
THE FILE EXTENSION?

    THANX IN ADVANCE
  NAVEEN

Article: 54577
Subject: synthesis of a VHDL module in Xilinx
From: bamini222@yahoo.com (bams)
Date: 14 Apr 2003 09:15:05 -0700
Links: << >>  << T >>  << A >>
Hello,

I have written a module in VHDL using generate and process
statements.when I simulated in Cadence nclaunch tool.It worked
perfectly, Out of curiousity, I tried to simulate in Xilinx, it didn't
synthesis.It is giving me multiple driver problem.Why it is so?why it
is different to different softwares.I am posting the VHDL code for
reference.the multiple driver problem is coming in the output
(Data_out1) in the code.please let me know why the same code isn't
simulated in two different softwares.


------------------------------------------------------------------
VHDL code
------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity FIFO_new is
	generic (width: integer := 64;
	size: integer := 4);
    port (
        Data_in: in STD_LOGIC_VECTOR( (width -1) downto 0);
        clk: in STD_LOGIC;
        clear: in STD_LOGIC;
	control: in STD_LOGIC;
        load: in STD_LOGIC;
        Data_out1: out STD_LOGIC_VECTOR(15 downto 0)
	);
end FIFO_new;

architecture FIFO_arch of FIFO_new is


component reg2 
	generic (k: integer := 16);
    port (
        D: in STD_LOGIC_VECTOR((k -1) downto 0);
        clk: in STD_LOGIC;
        clear: in STD_LOGIC;
        Q: out STD_LOGIC_VECTOR((k -1) downto 0)
    );
end component;

---signal declarations 

type DATA is array (0 to (size-1)) of STD_LOGIC_VECTOR(15 downto 0);
signal T: DATA;
type ENTRY is array (0 to (size-1)) of STD_LOGIC_VECTOR (15 downto 0);
signal S: ENTRY;


begin
  -- <<enter your statements here>>

G1: for i in 0 to (size-1) generate
    

	   S(i) <= Data_in(((16*i) + 15) downto (16*i)) ;
  
 	   FG2: reg2 port map  (S(i), clk, clear, T(i));   
 


---new process for the parsed outputs to be retrieved from the array.


P1: process (clk,load,control)

variable tmp: integer range 0 to (size-1);	
 begin
	if (clk'event and clk = '1') then
		

  		if (control='0' and load='1' ) then
		tmp := 0;
	
	
		elsif (load ='1' and control='1') then
		if (tmp < (size-1)) then 
		tmp := tmp + 1;
		end if;
		end if;

		Data_out1 <=T(tmp);
	end if;

end process P1 ;

end generate G1;
      	         
end FIFO_arch;

Article: 54578
Subject: Re: request for simple UART
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 14 Apr 2003 09:26:40 -0700
Links: << >>  << T >>  << A >>
UARTS only oversample the start bit. Once they thus found the center of
the bit, they sample open-loop the remaining 8 or 9 bits. Then
resynchronize on the next start bit, etc.
Peter Alfke

Rene Tschaggelar wrote:
> 
> Valeria Dal Monte wrote:
> > "valentin tihomirov" <valentin@abelectron.com> ha scritto nel messaggio
> > news:3e9a865c_2@news.estpak.ee...
> >
> >>I have an idea to implement all digital logic of my circuit into a CPLD.
> >
> > The
> >>only doubt is external UART. I know, additional UART is a big pain,
> >>currently I use tl16c750. I think that a price of external uart is the
> > same
> >>or greater than an average CPLD chip. All IP cores suggested by google are
> >>complex, ie with FIFOs and flow control. I would be satisfied with the
> >>8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers,
> >
> >>RI flags and a hardwired frecuency. Any suggestions.
> >
> > I think a such non-programmable UART is very simple to implement
> > and very inexpensive in terms of macrocells, likely less than 32.
> 
> This may be impossible. A UART uses oversampling and taking the
> majority. For 8 databits plus 1 startbit and 1 stopbit at 4 times
> oversampling the shiftregister is 40 bits long. Add 2 bytes for
> transmission and 2 bytes for reception and you're at 64 bits.
> Then add a few macrocells for the logic.
> 
> Rene
> --
> Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> & commercial newsgroups - http://www.talkto.net

Article: 54579
Subject: error correcting codes
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Mon, 14 Apr 2003 12:27:52 -0400
Links: << >>  << T >>  << A >>
Hello,
    I have an embedded system composed of several FPGAs.  The control
codes for the system are sent via a com port on a PC.  The UART is taken
from UAPP 223 (Thanks to Ken Chapman).  Unfortunately this UART has no
parity bit.  This should not be a problem as we are echoing the command
string back to the PC to verify correct data transmission.  However, we
still seem to have some sort of system corruption problem that I believe
is caused by the serial data stream.  The control stream consists of 3
8-bit characters.  To me the obvious solution is to add a 4th 8 bit word
that could contain the ECC data.  I have several questions.

1.    Is 8 bits enough to Error correct a 24 bit data stream?
2.    Assuming it is, how many errors can it correct?
3.    The data is being sent to a pico-blaze.  Should the ECC be done in
the pico blaze or in hardware before the pico-blaze?  My suspicion is to
do it in the pico-blaze and thus take care of any comunication issues
including the input to the pico-blaze.

Note: I did not design this FPGA but I need to get to near 100%
reliability in it.  The individuals who did design it work for me and
usually do very good work.  We would rather stick with the UART and
pico-blaze we have and put the ECC into another data word.  This would
allow a minimum of design changes.


Article: 54580
Subject: Re: 2.5V switching regulator for Spartan 2
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 14 Apr 2003 12:33:20 -0400
Links: << >>  << T >>  << A >>
Rajeev wrote:
> 
> I'm planning to use the MAX8869 1Amp LDO from 3.3V, which I like
> because it uses ceramic caps and it has a power-good output.  It's
> not available from D/K but I was able to obtain less than full reel
> direct from Maxim about 18 months ago (for an earlier project that never
> got built).
> 
> Can somebody shed light on why power-up waveforms matter ?  I mean, one
> might (naively ?) imagine that things would be OK so long as all the
> voltages settle down before configuration starts...

Well that is the 64 thousand dollar question...  Seems that as the
transistors cross threshold and actually start to operate there are
numerous paths that are turned on which draw significant current until
the voltage has risen enough to turn the transistors off.  I have never
gotten Xilinx (and have never talked to Altera) to give me the details
about why this happens since it has to do with internal structures that
they don't want to share info about.  

But be aware of it and don't try any shortcuts.  You will not like the
results if you do.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 54581
Subject: Re: Tristate-Bus-Termination; fast pullup req'd
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 14 Apr 2003 09:33:25 -0700
Links: << >>  << T >>  << A >>
Xilinx comes to the rescue:
Look at #5 in
http://support.xilinx.com/support/techxclusives/6easy-techX37.htm

Peter Alfke, 
Good Samaritan = Guter Samariter...
=========================
Christian wrote:
> 
> Hi There,
> I am looking for a solution forcing a tristated bus-line to 1 (VCCIO) when
> it is in highZ state.
> I made a simple approach using a 330 Ohms pullup resistor to pull the line
> up to 3,3V when not driven.
> When the IO cell of my APEX FPGA drives the bus low, it can consume
> about -10 mA of IOL current. (flowing through my pullup into the FPGA,
> therefore 330Ohms is maximum pullup value)
> But in highZ state, it takes much to long until ti reaches VCCIO.
> Now my question: Is it possible to use an active termination to reach faster
> pullup functionality? Or would a pullup/pulldown combination be sufficient
> for that?
> 
> thanks in advance
> best regards
> Chris.

Article: 54582
Subject: Re: Hardware acceleration for raytracing purposes
From: Luc Claustres <claustre@irit.fr>
Date: Mon, 14 Apr 2003 18:38:18 +0200
Links: << >>  << T >>  << A >>
http://www.saarcor.de/

Svjatoslav Lisin wrote:

> Does somebody know any ready hardware systems for raytracing acceleration ?
> How much can it cost?


Article: 54583
Subject: Re: Verilog to VHDL or vice-versa converters ??
From: fortizzz@hotmail.com (Fernando)
Date: 14 Apr 2003 09:46:01 -0700
Links: << >>  << T >>  << A >>
(In case you haven't seen it) you can try XHDL, I don't know about its
reliability though. It didn't work very well for me.

http://www.edadirect.com/products.html

prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0304100920.25920bfe@posting.google.com>...
> Hi,
> Are there any reliable Verilog-to-VHDL or VHDL-to-Verilog converters in the market ?
> 
> Thanks,
> Prashant

Article: 54584
Subject: Re: Testing engineering ability prior to work?
From: richardgrise@yahoo.com (Rich Grise)
Date: 14 Apr 2003 10:42:57 -0700
Links: << >>  << T >>  << A >>
anglomont@yahoo.com (TI) wrote in message news:<18a34598.0304061942.18a55177@posting.google.com>...
> Is there some type of standard test other than hobby projects
> that could serve to test for example circuit designs ability or
> sales/marketing  skill prior to taking a job?
> I feel I could do both equally well provided I get paid enough to try
> hard.
> ( I suppose the experienced specialists bored with work probably  have
> the same attitude -dont care what I do provided I regularly get paid
> enough?)

Not a "standard" test, although I've undergone what could be
regarded as "tests," and in each case it was related to what
the company wanted the person to accomplish. In a couple of 
cases it involved reading schematics - those jobs I got. In
another case, for a programmer job, the "test" was to output
all the prime numbers between 1 and 1000. I panicked, as it
was a timed test, and didn't even get half-through writing
the stupid program. Some weeks later, I had a flash of 
inspiration at a bus stop, and wrote a Sieve of Eratosthenes
in like 5 lines. But that job was long gone. Now I'm a "Tech
Writer," and I do a variety of things. The only test, really,
was when I showed the guy a couple of websites I've designed,
and the recommendation of someone who's practically a partner.
We're both contractors, and neither of us calls ourself an
engineer, but when somebody else accidentaly calls me an
engineer, I don't go to great lengths to correct them.
Sometimes, when people ask me about a degree, I tell them
I've had 30 years of BS in the School of Hard Knocks. ;-}

Good Luck!
Rich

Article: 54585
Subject: Re: Double Edge FlipFlop
From: CCNguyen <>
Date: Mon, 14 Apr 2003 11:25:25 -0700
Links: << >>  << T >>  << A >>
Hi Peter, 

Another question of how to implement it. Right now Im thinking 
two ways to do it : 

1) Implement the clock doubler in Virtex. But then I can't use BUFG to fan out the doubled clock (I think that is true) 

2) Use discreate components, then feed the doubled clock to Virtex 
through clock pad so BUFG can play its role. 

Probabbly I will setup prototype layout so I can try either one, 
but which one will you not prefer to, why? 

many thanks,


Article: 54586
Subject: Spartan 3, Vccaux?
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 14 Apr 2003 14:49:13 -0400
Links: << >>  << T >>  << A >>
I guess I have not spent enough time keeping up with the newer Xilinx
parts.  Seems the Spartan 3 chips have inherited from the Virtex II
chips THREE power supply voltages; Vccint, Vcco and *Vccaux*.  I belive
in the VII parts there is a circuit for decrypting a bit stream and
holding the key in internal ram.  But I see a fourth voltage, Vbatt, for
that.  

So what exactly is the Vccaux for?  Is this a Vcco for the various IOs
that are not general user IOs?  If the current levels are similar to the
VII, I can accomodate that very easily with a SOT-23 regulator.  But I
am surprises to see this.  

Are there other issues using this chip on a board with 3.3 volt powered
IOs?  The configuration signals seem to be working to a LVCMOS25
standard.  According to the data sheet a 3.3 volt signal will exceed the
max allowed voltage.  Is there some easy way to work around this?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 54587
Subject: Re: Spartan 3, Vccaux?
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Mon, 14 Apr 2003 19:01:36 +0000 (UTC)
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> wrote:
: I guess I have not spent enough time keeping up with the newer Xilinx
: parts.  Seems the Spartan 3 chips have inherited from the Virtex II
: chips THREE power supply voltages; Vccint, Vcco and *Vccaux*.  I belive
: in the VII parts there is a circuit for decrypting a bit stream and
: holding the key in internal ram.  But I see a fourth voltage, Vbatt, for
: that.  

: So what exactly is the Vccaux for?  Is this a Vcco for the various IOs
: that are not general user IOs?  If the current levels are similar to the
: VII, I can accomodate that very easily with a SOT-23 regulator.  But I
: am surprises to see this.  

Looka at ds099-2.pdf page 9:
3. The VCCAUX is an auxiliary source of power, primarily to optimize the
performance of various FPGA functions such as I/O switching.

: ...

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 54588
Subject: Re: Testing engineering ability prior to work?
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 14 Apr 2003 15:10:17 -0400
Links: << >>  << T >>  << A >>
Rich Grise wrote:
> 
> anglomont@yahoo.com (TI) wrote in message news:<18a34598.0304061942.18a55177@posting.google.com>...
> > Is there some type of standard test other than hobby projects
> > that could serve to test for example circuit designs ability or
> > sales/marketing  skill prior to taking a job?
> > I feel I could do both equally well provided I get paid enough to try
> > hard.
> > ( I suppose the experienced specialists bored with work probably  have
> > the same attitude -dont care what I do provided I regularly get paid
> > enough?)
> 
> Not a "standard" test, although I've undergone what could be
> regarded as "tests," and in each case it was related to what
> the company wanted the person to accomplish. In a couple of
> cases it involved reading schematics - those jobs I got. In
> another case, for a programmer job, the "test" was to output
> all the prime numbers between 1 and 1000. I panicked, as it
> was a timed test, and didn't even get half-through writing
> the stupid program. Some weeks later, I had a flash of
> inspiration at a bus stop, and wrote a Sieve of Eratosthenes
> in like 5 lines. But that job was long gone. Now I'm a "Tech
> Writer," and I do a variety of things. The only test, really,
> was when I showed the guy a couple of websites I've designed,
> and the recommendation of someone who's practically a partner.
> We're both contractors, and neither of us calls ourself an
> engineer, but when somebody else accidentaly calls me an
> engineer, I don't go to great lengths to correct them.
> Sometimes, when people ask me about a degree, I tell them
> I've had 30 years of BS in the School of Hard Knocks. ;-}


I have met good engineers with no degrees and lousy engineers who had
degrees.  A degree is just one way to get an education, not a
certificate of accomplishment.  

On the other hand, I have met very, very few good managers.  The one who
gave you a timed programming test was clearly out to lunch.  Your
abililty to *write* code in a five minute window is no indication of the
*many* tasks you will have to perform as a programmer.  I would be much
more interested in how well you write code and how you approach
debugging a program than how fast you can *code* it.  Like soneone
posted in one of the other groups...  "Since I touch type, I can *write*
code quite fast.  Debugging it is another matter"  or something
equivalent.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 54589
Subject: Bus Macros:Power Supply
From: eduwenzel@yahoo.com.br (=?ISO-8859-1?Q?Eduardo_Wenzel_Bri=E3o?=)
Date: 14 Apr 2003 12:15:06 -0700
Links: << >>  << T >>  << A >>
Hi, 

To install bus macros in my design, I use two kinds of power supply:
Vcc e Gnd pins for each reconfigurable area group (see XAPP290
example). So I use four IO pins and I set these as PULLUP or PULLDOWN.
But I don´t want to use IO pins. I heard to talk about GND and VCC
signals that they are created with internal LUTs. How do I create and
instanciate these signals inside of LUTs? Do someone have a
suggestion? I apreciate any kind of help.

Regards 

Eduardo Wenzel Brião 
Catholic University of Rio Grande do Sul state 
Porto Alegre city 
Brazil

Article: 54590
Subject: Re: Xilinx has released SpartanIII
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 14 Apr 2003 12:32:52 -0700
Links: << >>  << T >>  << A >>
In the Spartan 3, Only two of the slices in a CLB can have their LUTs
used for distributed RAM or SRL.  That's a new "feature", isn't it?  Was
there a technical reason why this was done, or is it just product
differentiation?

Article: 54591
Subject: Re: Xilinx has released SpartanIII
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 14 Apr 2003 12:45:59 -0700
Links: << >>  << T >>  << A >>
I wrote:
> In the Spartan 3, Only two of the slices in a CLB can have their LUTs
> used for distributed RAM or SRL.  That's a new "feature", isn't it?  Was
> there a technical reason why this was done, or is it just product
> differentiation?

After I posted that, I realized that it might sound like a complaint,
which it isn't.  The Spartan 3 parts look great, and I've never yet
needed to use more than half the logic elements of any FPGA as
distributed RAM or SRLs.

What I was really getting at was whether there was some technical reason
why the CLB design for the 90 nm process worked out better if the
right-half slices didn't work as DRAM or SRL, for instance, if there
wasn't enough room to route some signals that would have been necessary
for that.  If so, perhaps we should expect this same behavior in future
90 nm families (Virtex 3?  Virtex Pro 2?).



Article: 54592
Subject: Re: An Improvement for the Booth multiplier
From: boothmultipler@hotmail.com (booth multiplier)
Date: 14 Apr 2003 12:49:42 -0700
Links: << >>  << T >>  << A >>
johnjakson@yahoo.com (john jakson) wrote in message > 

> This is a much explored area and is thought to be completely
> understood.
> 
> The Wallace structure is also well known and handily beats the Booth
> algorithm by larger & larger margins as the arrays get bigger. If
> anyone was really after speed, they would already be using Wallace
> despite its irregular structure.
> 
> Wallace multiplication times can approach O(logN) times.
> Booth multiplication times generally follow O(N) times.
> 
> Perhaps you should outline the idea and see if others will salute it,
> or perhaps you have reinvented one of the minor variations covered in
> many texts.
> 
> I doubt that either Booth or Wallace recieved any fortune, but their
> names are immortalized here, perhaps yours will too.

The discovered technique has nothing to do with Partial Product
Reduction, it is dealing with partial product generation.It produces
fewer partial product bits to sum than the modified booth algorithm.So
whatever you are using to reduce the PP bits :wallace tree or 4:2
counters or other compressors,there are fewer bits to sum and the
column heights are less. This changes the signal arrival profile to
the final adder and reduces the PPRT(Partial Product Reduction Tree)
hardware. The final adder could sum the last sum+carry faster.

So the VLSI guys have:
 Less complicated PPRT.
 Less complicated Final Adder.
=Less critical path delay

Article: 54593
Subject: Re: Spartan 3, Vccaux?
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 14 Apr 2003 15:57:11 -0400
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:
> 
> rickman <spamgoeshere4@yahoo.com> wrote:
> : I guess I have not spent enough time keeping up with the newer Xilinx
> : parts.  Seems the Spartan 3 chips have inherited from the Virtex II
> : chips THREE power supply voltages; Vccint, Vcco and *Vccaux*.  I belive
> : in the VII parts there is a circuit for decrypting a bit stream and
> : holding the key in internal ram.  But I see a fourth voltage, Vbatt, for
> : that.
> 
> : So what exactly is the Vccaux for?  Is this a Vcco for the various IOs
> : that are not general user IOs?  If the current levels are similar to the
> : VII, I can accomodate that very easily with a SOT-23 regulator.  But I
> : am surprised to see this.
> 
> Looka at ds099-2.pdf page 9:
> 3. The VCCAUX is an auxiliary source of power, primarily to optimize the
> performance of various FPGA functions such as I/O switching.

Ok, so what does it do?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 54594
Subject: Re: error correcting codes
From: "John Milbanks" <phony@nowhere.cc>
Date: Mon, 14 Apr 2003 13:01:39 -0700
Links: << >>  << T >>  << A >>
Are you sure you want to bother with error correction, as opposed to error
detection and retransmission?
A Cyclic Redundancy Check character would have very high probability of
detecting an error, and you could have your embedded system send an 'ack' or
'nak' character to acknowledge a transmission. The sender would retransmit
if it got a nak. Naturally, you'd have to handle the case where the ack or
nak is corrupted, such as, for example, making ack=00001111 and
nak=11110000. The pattern would allow the sender to figure out which was
meant, even if one of the bits got corrupted.

To answer your specific question, it's been a while since I studied ECCs,
but if 8 bits is sufficient to correct, it'll be capable of correcting 1 bit
at most. If you get two or more errors and the ECC detects them, you'll
still have to retransmit. So my argument would be to use CRC (which will be
more robust in its error-detecting abilities) and retransmit any time you
get an error.

"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message
news:3E9AE188.9F1A2DDD@egr.msu.edu...
> Hello,
>     I have an embedded system composed of several FPGAs.  The control
> codes for the system are sent via a com port on a PC.  The UART is taken
> from UAPP 223 (Thanks to Ken Chapman).  Unfortunately this UART has no
> parity bit.  This should not be a problem as we are echoing the command
> string back to the PC to verify correct data transmission.  However, we
> still seem to have some sort of system corruption problem that I believe
> is caused by the serial data stream.  The control stream consists of 3
> 8-bit characters.  To me the obvious solution is to add a 4th 8 bit word
> that could contain the ECC data.  I have several questions.
>
> 1.    Is 8 bits enough to Error correct a 24 bit data stream?
> 2.    Assuming it is, how many errors can it correct?
> 3.    The data is being sent to a pico-blaze.  Should the ECC be done in
> the pico blaze or in hardware before the pico-blaze?  My suspicion is to
> do it in the pico-blaze and thus take care of any comunication issues
> including the input to the pico-blaze.
>
> Note: I did not design this FPGA but I need to get to near 100%
> reliability in it.  The individuals who did design it work for me and
> usually do very good work.  We would rather stick with the UART and
> pico-blaze we have and put the ECC into another data word.  This would
> allow a minimum of design changes.
>



Article: 54595
Subject: Re: An Improvement for the Booth multiplier
From: Ray Andraka <ray@andraka.com>
Date: Mon, 14 Apr 2003 20:06:22 GMT
Links: << >>  << T >>  << A >>
Absolutely.  I missed that it went to other newsgroups.  The inappropriateness of a Wallace tree as I described is more or less
unique to FPGAs with a fast carry chain.  What the Wallace tree does is postpone the carry until the last adder in the tree.
Normally (in ASIC land), the fastest adders are ones that use fairly expensive carry look-ahead techniques, while the cheapest
(and generally the slowest) are ripple carry adders.  The FPGAs with a carry chain represent an anomaly because the dedicated
carry logic is much faster than the general purpose logic so it turns out that the ripple carry adder is both minimum cost and
minimum delay.  The irregular routing of the wallace tree degrades the Wallace tree relative to a ripple tree in the FPGA.

john jakson wrote:

> Ray Andraka <ray@andraka.com> wrote in message news:<3E99A0E9.95868F7B@andraka.com>...
> > Wallace tree multipliers only make sense where fast adders cost more than minimum area adders.  For  FPGAs with built in
> > fast carry logic, this is not the case.  I have a more detailed discussion on this on the multipliers page on my website.
> >
>
> Yes ofcourse, from FPGA pt of view it would be Booth based and ripple
> adder based.
>
> However the post did go to other NGs where FPGAs are not relevant, and
> the last time I built an ASIC MAC, the multiplier was definitely a
> Wallace design. Since it was back in the 0.8u days the adder delays
> were dominant over wires by a long shot. In a previous Wallace design
> I even had to do the wiring and cell placement by hand in 1 layer of
> metal plus poly & dif, those were the days.
>
> These days 0.18u and less, with interconnects being very slow relative
> to cell delays, I am not so sure Wallace would beat Booth anymore
> unless I sat down & redid it both ways. Then again if Xilinx had no
> fast carry path in CLB, the same situation might arise there.
>
> In the end to mr Booth.multiplier, I think the ASIC guys already know
> what they are doing and there is likely to be more impact from circuit
> layout related decisions than any tweaking of the Booth algorithm.
>
> John

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 54596
Subject: Re: Testing engineering ability prior to work?
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 14 Apr 2003 13:12:02 -0700
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> writes about interviewing engineers:
> I would be much
> more interested in how well you write code and how you approach
> debugging a program than how fast you can *code* it.  Like soneone
> posted in one of the other groups...  "Since I touch type, I can *write*
> code quite fast.  Debugging it is another matter"  or something
> equivalent.  

I've found that it *is* necessary when interviewing programmers to ask
them to write at least a little code, because some people with great
resumes can't actually code their way out of a paper bag.  Having been
on the other side of the interview process, I know that spontaneously
writing code on a whiteboard is much more difficult than coding in a
normal situation.  So when I do this, I'm not timing them, and I'm not
looking for perfect syntax.  I mostly just want to see that they appear
to know how to write code.

If you do give such a test, *please* think up an original problem,
rather than using one that all your colleagues use.  You're not trying
to find a candidate who has memorized the answer to a common problem,
you should be looking for someone that can solve a new problem.  The
last time I was looking for a job, I interviewed with about 14 people at
two companies, and at least ten times I was asked to write a C function
to reverse a singly linked list.  after the first time or two I had that
down cold, such that some of the interviewers were amazed; apparently
they had no idea that I'd been given this same problem multiple times on
the same day until I told them.

One of my friends uses as an interview question something like "what was
the most difficult bug you've had to find?"  He had one candidate with
an impressive looking resume that was completely unable to answer this
question.  Needless to say, he recommended against hiring that
candidate.

When interviewing programmers, I describe a problem I once faced, write
some C code on the whiteboard, and ask the candidate to debug it.  I
offer to pretend to be any sort of debugging tool or test equipment the
candidate wants to apply, e.g., I'm willing to "play computer", pretend
to be GDB, and in-circuit-emulator, or whatever the candidate thinks
would be useful.

The particular problem I usually use for this can be stated reasonably
simply, but may be tricky to solve.  It originally took me two days to
track it down and fix it, but I give the candidate more information than
I started from.  I explain this to the candidate, and that I'm really
just interested in seeing how they approach debugging; I don't want the
candidate to think that not getting to the bottom of the problem will
fail the interview.

Once in a while I get a candidate who spots the problem immediately,
which is impressive but requires me to spend more time probing for
debugging skills.  Once I got a candidate who simply had no clue how to
go about debugging the problem.  I tried all sorts of prompting, like
"would you like to set a breakpoint here", and got nowhwere.

Article: 54597
Subject: NIOS 3.0 Fmax and other Issues
From: jim006@att.net (Jim M.)
Date: 14 Apr 2003 13:22:51 -0700
Links: << >>  << T >>  << A >>
I recently purchased a NIOS Stratix 1S10 Development Kit from Altera
and have mixed feelings about Quartus, SOPC Builder, and the NIOS
Core.  (For those poor souls interested, I've included some comments
at the end of this post... feel free to provide feedback.)

However, here's my question:

What's the maximum clock frequency anyone has achieved using the NIOS
3.0 CPU in 32bit mode with the standard peripherals (SRAM, SDRAM,
Ethernet, PIO, UART, etc. as in the Reference Design provided by
Altera)?

I've tried isolating the various components into LogicLock regions. 
I've tried different fitter/netlist optimizations.  The maximum Fmax I
have achieved to date is 80 MHz.  This is after letting Quartus "fit"
for 10 hours... it actually didn't stop, I had to abort the fitting
and refit to finially get an interim result (see other misc comments
below).

Altera advertises 125 MHz for the Stratix Device and NIOS 3.0...
However a reference design that builds at that clock rate is not
provided.  It appears that Altera gives you just enough to get your
feet wet... anything above and beyond that is Intellectual Property
that you need to buy.

Other Observations/Comments:

1.  The Quartus II SP1 software is extremely flakey.  I've generated
numerous faults when deleting/modifying child LogicLock Regions.  It
also takes forever to fit my Stratix design which is only 6000 LEs. 
If I select the "limit fitting attempts to 1" option, Quartus
sometimes fits many times (like forever...) why?!?!?  Also, after a
design is finished building, the software sits around for up to 5
minutes before it generates a "finished" dialog box.  I'm not sure
what's going on between the Quartus Application thread and the Quartus
Compiler thread, but it's fustrating enough just waiting for the
design to build, let alone waiting for Quartus to figure out the build
is done.  I could go on and on, and that's only the result of 4 weeks
of effort with a small design.  I feel sorry for those folks working
on a 100,000+ gate design.  I guess modularity is the key there.

2.  I can't simulate designs with virtual pins.  I get warning during
the analysis of the simulation and then receive results with all input
pins a zero and output pins undefined.  In addition, I can generate
hold time warnings during simulation for a design that didn't compile
with any hold time warnings.  I'm not talking about hold time warnings
on my input signals, I'm talking about hold time warnings on internal
registers in my verilog code.  Registers that I've taken care to hold
for 1 or more clock cycles before using in other parts of the design. 
Again, the compilation of the design did not generate hold time
warnings... only the simulation of the design.

3.  PLLs generate different timing analysis results.  THIS IS VERY
ANNOYING!  When I build up a "black-bock" design with virtual pins I
obtain a Fmax calculation from the timing analysis routine.  I then
LogicLock the design and export it.  When I import the design into a
new project and clock it using a PLL it generates negative slack time
warnings!  If I remove the PLL and replace it with a clock pin, I get
the Fmax result that I obtained during the "black box" design.  I beat
myself up for a week trying to debug a design that wasn't broken
because of this goofy behavior in Quartus.  I'm still not sure if the
slack time warning it legit and wether I should be concerned about it.

4.  SOPC Builder will lock itself up if you double-click components
before selecting them.  Give it a try... double click a component line
in your NIOS design before selecting the line item.  After a couple
times the SOPC builder application creeps to a halt.

5.  Documentation on the various megafunctions is lacking.  A good
example is the altsyncram megafunction.  It doesn't state any timing
requirements on the input registers, enable, and clock signals.  Do I
hold the data 1 cycle before flipping the write enable?  How about
holding the write enable before de-activating it?  Why is the
addressing based upon the data bit-width?  Trying to tie a 32-bit
altsyncram block to a NIOS CPU is difficult because you need to
specify the address space of the peripheral and the address space of
the altsyncram block is based upon the bit width (not the number of
bytes).

6.  I have yet to get a Leonaro-Spectrum synthesized Verilog file to
build in Quartus.  I can used Spectrum generated .edf files but not
verilog.  I get LCELL parameter errors.  Unfortunately, Altera can't
seem to duplicate this... anyone else see this behavior?  I'm not sure
if Spectrum synthesizes Verilog better that Quartus, but it definitely
does it faster.

Feedback is welcome... even if it's the "you're an idiot and here's
why" variety...

Article: 54598
Subject: Re: error correcting codes
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 14 Apr 2003 13:28:23 -0700
Links: << >>  << T >>  << A >>
If you absolutely need Hamming error correction ( because retransmission
is impossible) the 8 bits are more than plenty to correct a single-bit
error in a 24+8-bit word.
32 bits give you 4 billion codes, but you only have 16 million
legitimate codes, and each of them has 24 single-error derivatives (
Hamming distance of 1). That means you need to decode ~400 million
codes. I suppose you can even sneak in double-error detection, but
definitely not double-error correction..

Peter Alfke
==============
Theron Hicks wrote:
> 
> Hello,
>     I have an embedded system composed of several FPGAs.  The control
> codes for the system are sent via a com port on a PC.  The UART is taken
> from UAPP 223 (Thanks to Ken Chapman).  Unfortunately this UART has no
> parity bit.  This should not be a problem as we are echoing the command
> string back to the PC to verify correct data transmission.  However, we
> still seem to have some sort of system corruption problem that I believe
> is caused by the serial data stream.  The control stream consists of 3
> 8-bit characters.  To me the obvious solution is to add a 4th 8 bit word
> that could contain the ECC data.  I have several questions.
> 
> 1.    Is 8 bits enough to Error correct a 24 bit data stream?
> 2.    Assuming it is, how many errors can it correct?
> 3.    The data is being sent to a pico-blaze.  Should the ECC be done in
> the pico blaze or in hardware before the pico-blaze?  My suspicion is to
> do it in the pico-blaze and thus take care of any comunication issues
> including the input to the pico-blaze.
> 
> Note: I did not design this FPGA but I need to get to near 100%
> reliability in it.  The individuals who did design it work for me and
> usually do very good work.  We would rather stick with the UART and
> pico-blaze we have and put the ECC into another data word.  This would
> allow a minimum of design changes.

Article: 54599
Subject: Re: Xilinx has released SpartanIII
From: "MikeJ" <support@{nospam}fpgaarcade.com>
Date: Mon, 14 Apr 2003 21:52:05 +0100
Links: << >>  << T >>  << A >>
I noticed that today as well - it was a bit of a shock. It suggests it is
not just a Virtex 2 die, and why the amount of distributed ram is half what
you would expect.
As far as I remember, Xilinx told me once that there is a significant area
overhead in implementing the ramd / srl function - so perhaps that's the
cost of having more luts.

It means some of my rloc'd macros will not work without some placement
fiddling - but I think it is a sensible compromise.

Nice price per lut as well  ...

/Mike

"Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message
news:qhptnon9qg.fsf@ruckus.brouhaha.com...
> I wrote:
> > In the Spartan 3, Only two of the slices in a CLB can have their LUTs
> > used for distributed RAM or SRL.  That's a new "feature", isn't it?  Was
> > there a technical reason why this was done, or is it just product
> > differentiation?
>
> After I posted that, I realized that it might sound like a complaint,
> which it isn't.  The Spartan 3 parts look great, and I've never yet
> needed to use more than half the logic elements of any FPGA as
> distributed RAM or SRLs.
>
> What I was really getting at was whether there was some technical reason
> why the CLB design for the 90 nm process worked out better if the
> right-half slices didn't work as DRAM or SRL, for instance, if there
> wasn't enough room to route some signals that would have been necessary
> for that.  If so, perhaps we should expect this same behavior in future
> 90 nm families (Virtex 3?  Virtex Pro 2?).
>
>





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