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Messages from 53725

Article: 53725
Subject: Re: PCI specification
From: Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om>
Date: Thu, 20 Mar 2003 14:38:25 -0600
Links: << >>  << T >>  << A >>
Praveen,

I will say that pick the implementation to fits your needs.
For example, if you are targeting a Xilinx or Altera FPGA, XOR 4 inputs
simultaneously because their basic logic cell has only 4 inputs, and
cascade the XOR gates calculate the parity.
However, if you are targeting a CPLD (an architecture with very coarse
grain logic cells), you may want to XOR 20 or more inputs
simultaneously.
  

Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)



praveen wrote:
> 
> Hello,
> In parity generator block in my PCI design, how should i implement
> parity generation
> parallelly
> ie x(0) xor x(1) xor(2).......x(36);
> or do
> f1:=x(0) xor x(2) nine each;
> f2:=nine each
> f3:=nine each;
> f4:=nine each;
> f5:=f1 xor f2 xor f3 xor f4;
> which is the better way????so that i can check the parity generated
> with the PAR signal coming in the next clock

Article: 53726
Subject: Re: Using FPGAs as coprocessors in a PC
From: johnjakson@yahoo.com (john jakson)
Date: 20 Mar 2003 12:39:27 -0800
Links: << >>  << T >>  << A >>
Response is pretty much same as those before.

For high speed live data to real world or tremendous/interesting
computing per point, consider FPGA even ASIC, otherwise stick to
fastest cpu. That may explain why FPGA accelerators are not common,
x86 is too damn fast already and getter relatively even faster than it
can be fed from HDs or network. Even FFTs don't really do that much
compute per point if you figure total_math / total_data.


> Is it possible to buy a PCI card with one (or several) FPGAs,

There are plenty of cards available, for PCI they usually start at $1K
& up to to the sky for the high end stuff, even upto $50k a board.
These can generally be wedded to A/D IO doughter boards.

avnet, nallatech, alpha-data, annapolis, dini (he can do custom for
you), see the lists in previous posts

> If so, what is the typical speed increase I can hope for 
> compared to a state-of-the-art 1 CPU PC (i.e. P4 3GHz).

This is the big question, for DSP it is most straight forward to
answer since you can easily represent the algorithm in it's math form,
asm/C/Fortran form, schematic form.

For something like a FIR filter, imagine writing the code in a
straight line of branchless C/asm code and do as much as possible
including buffering etc, but no OS calls. This could be called a clock
cycle if all the math can fit in suitable FPGA. That means you could
do quite a few muls & adds on the virtex 2 (more than a hundred IIRC).
Now if the basic operation is limited to *+ then you can set a max
freq for FPGA, this might be 120MHz or so.

From the C code as best optimized as possible on x86 you can measure
the no of x86 cycles for a 3GHz P4 (or any cpu). Make sure the timing
is repeatable on differnt data sets. So C_period/8ns is your potential
speed up.

Now you could elect to use a smaller cheaper FPGA so break the C code
into smaller chunks, find a segment that can be looped, acceleration
will go down by loop cnt, but then control complexity starts to creep
in.

The C code is really going to be dominated by memory references to
data and your OS ability to hide the HDs slow performance. If you can
feed this C block at a continuos rate of n samples per sec, then
consider that the speeded up FPGA must be fed & attended x times
faster. I would venture that even with the fastest HDs, even C code
can be disk limited.

If your data is live from AD/DA converters you can push the processing
speed easily upto the limits of conversion for FPGA. If your data is
fed from a network server, you might as well give up unless you are
doing lots of computation on every point/sample transfered.

In otherwords consider how much processing per point and the cost of
getting that data point in/out of the engine.

For something like an FFT it gets much more interesting as most of the
design is control which isn't so easy to figure what the cost is
either C or HW.

As a reference we did a 1024 complex Rad4 FFT engine that takes 15us
or so in latency. Since it is 5 way overlapped, it starts/finishes a
new FFT every 3us or so. Clock is about 120MHz. A Rad2 would normally
require 512.4.10 (20K) muls or less. A Rad4 is 256.12.5 (15K) or less
(ie about 25% less). This project needed >40 muls each for forward &
inverse and a good no of engineers for a 1yr. It also included
Floating point math in other areas & doubled the complexity.

As a comparison, if I were doing this on x86 I would probably use
Intels Math lib, I seem to recall 15us awhile back but I can't find it
on their site anymore. For Intel I assume they used Rad2, I assume
that each butterfly needed takes 10 cycles on avg, thats 50K cycles at
3GHz about 17us. I doubt Intel can do a butterfly any faster. A Rad4
would have required 25% less muls but may not have been faster. Now
x86 could use floating point, a possible advantage for some.

FFTs really pick up steam when you can put a no of these DSP blocks
together to increase the amount of compute per point keeping data
moving nicely between them.

Article: 53727
Subject: Re: fpga implementation problems
From: vishker@yahoo.com (Vishker)
Date: 20 Mar 2003 13:14:54 -0800
Links: << >>  << T >>  << A >>
Try running simulation for post synthesis and post place&route
results. There is a switch in ISE which outputs post place&route
netlist in verilog/vhdl. I am sure you ll find somthing similar in
Synthesis tools also. May be the tools are messing up the logic.

-Vs

ninjak@gmx.de (zerang shah) wrote in message news:<4d6c559c.0303182011.46e6e561@posting.google.com>...
> Hello,
> 
> I am working on a fairly large project on a Xilinx XCV1000, and I am
> using ISE 5.1i for synthesis. I've tested my design in simulation and
> it behaves as it is supposed to, but when I program my FPGA, it
> behaves weirdly. I'm sure that everything is wired correctly and I can
> get simple VHDL programs to synthesize correctly. I'm certain that the
> issue isn't timing, I've slowed the clock down to molassas speed. I've
> spent many hours trying to debug this, and I've had no luck. I was
> wondering: Does anyone here have some suggestions?? This is really
> frustrating...
> 
> Thanks for the help.

Article: 53728
Subject: Re: Altera ACEX 1K
From: davidg@altera.com (Dave Greenfield)
Date: 20 Mar 2003 13:40:07 -0800
Links: << >>  << T >>  << A >>
charleybrant@hotmail.com (CB) wrote in message news:<3e78c897.2415599@news.compuserve.com>...
> I have used the altera ACEX 1K product line and after studing the new
> Cyclone products ... except for possibly the very lowest cost 1K
> products which still seem to be cheaper than the lowest cost Cyclone
> .. is there any reason to still consider the 1K products for new
> designs over the Cyclone ?  thanks for any insight CB

Cyclone devices should be the product of choice for cost focused
design starts today. Cyclone devices specifically provide the lowest
cost per LE of any FPGA architecture and higher density options than
the ACEX 1K family. Cyclone devices also provides comparatively higher
performance than ACEX 1K devices and up to 5X the embedded memory. So
the family provides bigger, faster, and cheaper in this cost-sensitive
space. The primary reasons to consider ACEX 1K devices today relate to
absolute lowest cost (the EP1K10 with 576 logic elements is marginally
less expensive than the EP1C3 with 2910 logic elements) and ability to
interface with 5.0 V logic.

Article: 53729
Subject: Re: Using DDR placed on the PCB with a Virted II...
From: "Austin Franklin" <austin@dark88room.com>
Date: Thu, 20 Mar 2003 16:43:21 -0500
Links: << >>  << T >>  << A >>
> My thoughts were to use the SSTL_2_I I/O for address and control, using
the
> DCI for source termination which would provide a 25 ohm series resistor.
> Use SSTL_2_II for the D/DQS signals for source and receiver termination,
as
> they are bidirectional, which would provide 25 ohm source termination for
> writes, as well as a pseudo second "VTT" termination for the reads.
>
> Externally, I was going to use 22 ohm source termination resistors on the
> D/DQS pins at the DDR, and use 50 ohm VTT termination.

After some discussions with a memory SI engineer, he recommended using 56
ohm VTT termination on the control signals, and 25 ohm VTT termination on
the DQ/DQS signals, since the Xilinx will basically be providing basically a
25 ohm VTT when using the SSTL_2_II IO for the DQ/DQS signals.

> I'm not sure if the DCI/V2 can handle the clock termination using I/O
> options though...so I was going to use external 33 ohm source termination
> resistors, with 120 ohm impedance matching resistors just after the source
> resistors,

He also recommended removing the 33 ohm resistors and just using the Xilnx
25 ohm resistors in the IOBs, but putting 0 ohm resistors there to be able
to tune it if need be.  He also recommended removing the first 120 ohm
resistor that was just after the series terminators for CK/CK#.

> and then another 120 just before the DDR, between CK/CK# (that did say
DQ/DQ#...)

he also recommended using N resistors on each CK/CK# at each chip, where N
adds up to 120 ohms.

This should be a good starting point.  There are some very important PCB
constraints I won't go into here, unless someone else is interested.

Austin




Article: 53730
Subject: Re: Altera ACEX 1K
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Fri, 21 Mar 2003 10:08:23 +1200
Links: << >>  << T >>  << A >>
Dave Greenfield wrote:
> 
> charleybrant@hotmail.com (CB) wrote in message news:<3e78c897.2415599@news.compuserve.com>...
> > I have used the altera ACEX 1K product line and after studing the new
> > Cyclone products ... except for possibly the very lowest cost 1K
> > products which still seem to be cheaper than the lowest cost Cyclone
> > .. is there any reason to still consider the 1K products for new
> > designs over the Cyclone ?  thanks for any insight CB
> 
> Cyclone devices should be the product of choice for cost focused
> design starts today. Cyclone devices specifically provide the lowest
> cost per LE of any FPGA architecture and higher density options than
> the ACEX 1K family. Cyclone devices also provides comparatively higher
> performance than ACEX 1K devices and up to 5X the embedded memory. So
> the family provides bigger, faster, and cheaper in this cost-sensitive
> space. The primary reasons to consider ACEX 1K devices today relate to
> absolute lowest cost (the EP1K10 with 576 logic elements is marginally
> less expensive than the EP1C3 with 2910 logic elements) and ability to
> interface with 5.0 V logic.

 But hang on, the Altera web Trumpets the Cyclone as the 
'Lowest cost FPGA Ever' so this can't be right, can it ?

 Ah, I see, it's because Altera Marketing has graciously 
added some new units to the world :

 We have 'lowest cost', and 'absolute lowest cost', and I also
spotted 'smallest die area' and 'effective smallest die area'
in a whitepaper to be praised for its gymnastics.
( My English and Physics teachers would spin in their graves .. )

 Perhaps someone should tell them, that 'lowest cost', and
'lowest cost per LUT' are actually different units - one is 
dollars, and one is dollars / LUT.

 Or, should we not mention it, and keep the source of 
entertainment alive ?

 If they want to move into 'effective die area', they should
register a new 'Altera Effective Metre' with the international 
standards committees.   :)

-jg

Article: 53731
Subject: Re: Increased Wafer yield by row adjusted placement
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Fri, 21 Mar 2003 08:13:08 +1000
Links: << >>  << T >>  << A >>
Glen Herrmannsfeldt wrote:
> "John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:b58ok8
> (snip) regarding:
> 
> 
>>>http://www.xilinx.com/company/press/products/archive.htm
>>
>>What I find interesting is the Virtex die image.  If you display a
>>Virtex bitstream as a rectangular binary image with appropriate rows and
>>cols (avail in the data sheet), the resemblance is uncanny.  Right down
>>to the little "flecks" you see on each CLB, and the lines across the
>>centre of the chip.  It shouldn't be a surprise, but the mapping between
>>the bitstream format and the physical layout of the chip is more or less
>>1:1.  Which probably explains Xilinx' desire to keep it to themselves.
> 
> 
> It probably has to be that way to make the chip reasonably routable.

Sure.  I suppose the configuration SRAM cells are hooked up like a huge 
shift register, and it makes sense that the logical bit organisation 
would mirror the physical layout.

John


Article: 53732
Subject: Re: Altera ACEX 1K
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Thu, 20 Mar 2003 22:21:53 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3E7A3BD7.A79@designtools.co.nz>,
Jim Granville  <jim.granville@designtools.co.nz> wrote:
> Perhaps someone should tell them, that 'lowest cost', and
>'lowest cost per LUT' are actually different units - one is 
>dollars, and one is dollars / LUT.
>
> Or, should we not mention it, and keep the source of 
>entertainment alive ?

Keep the entertainment alive.  And is it really "Lowest cost in
marketing gates?"  

> If they want to move into 'effective die area', they should
>register a new 'Altera Effective Metre' with the international 
>standards committees.   :)

And they obviously aren't smallest in lambda or lambda/lut.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 53733
Subject: Re: Using FPGAs as coprocessors in a PC
From: fortizzz@hotmail.com (Fernando)
Date: 20 Mar 2003 14:44:51 -0800
Links: << >>  << T >>  << A >>
tom@arithlogic.com (Tom Hawkins) wrote in message news:<cf474e53.0303192012.6267c920@posting.google.com>...
 DSP.
> 
> A lot of people new to DSP on FPGAs at first tend to believe they need
> floating point precision.  In our development process we usually hand
> off a C math model early on to let our clients experiment with various
> levels of fixed-point precision.  Often this convinces them that fixed
> point works just as well, and sometimes even better, than floating
> point.  Also, don't forget Cordics for fixed-point sines and cosines. 
> They may be a better alternative than consuming memory for lookup
> tables.


I disagree with what you said. Floating-point units are coming along nicely,
and the features in the new fpgas (BRAM, multipliers) give a huge boost to
fp peformance.  Cordic is (in my opinion) not the way to go if you want high
performance, becase it requires a lot more cycles than LUT-derived methods.
You can even add (floating-point) linear interpolation to decrease the
memory footprint, and the latency will be still be lower than cordic,
keeping the compatibility and range of the IEEE-754 format.

However, I would like to hear the opinion of the experts, 

Fernando

Article: 53734
Subject: Re: Using FPGAs as coprocessors in a PC
From: already5chosen@yahoo.com (Michael S)
Date: 20 Mar 2003 15:50:25 -0800
Links: << >>  << T >>  << A >>
P4-3GHz is 200-400 times faster than PCI (200 times with
single-precision FP, 400 times with 16-bit fix-point SSE2). So in
order to see any  speedup you have to chew each data point 200 or 400
times. Typical beam-former (time domain, input rate equal to output
rate) chews each data point 8 times per output beam (4 MACs). So don't
bother yourself with coprocessor boards if you want less than 50
beams. If you want more than 50 beams within 90 degrees - coprocessor
makes sense.

But is FPGA really better than DSP in your application ? FPGA is very
good at handling a small number of very fast channels. It also excels
when ultra-low latency is paramount. DSP is often better when you have
several tens or few hundreds of slower channels . In this case the
FPGA could serve as a good IO front end.

On the other end, there are applications which accepts very long
latency, has large data sets and are insensitive to power budget. In
these applications  fast wide SIMD CPUs (possibly in SMP or NUMA
configuration) typically beat both DSPs and FPGAs.

Article: 53735
Subject: Re: Using FPGAs as coprocessors in a PC
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 21 Mar 2003 02:09:21 -0000
Links: << >>  << T >>  << A >>

>On the other end, there are applications which accepts very long
>latency, has large data sets and are insensitive to power budget. In
>these applications  fast wide SIMD CPUs (possibly in SMP or NUMA
>configuration) typically beat both DSPs and FPGAs.

How much do SIMD/NUMA boxes cost?  Where do I get one?

The SMP boxes I'm familiar with are aimed at the "server" market
and priced accordingly.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 53736
Subject: Implementation error ?
From: prasanth_cit@yahoo.com (Prasanth Anbalagan)
Date: 20 Mar 2003 18:31:58 -0800
Links: << >>  << T >>  << A >>
Hi
   I'm using Xilinx Foundation series 3.1i.I am able to synthesize my
design and perform functional simulation.But I'm not able to implement
it.The tool gives the following error message

  >> Automation caused an exception ,exit code 80010105
  >> The server threw an exception

I tried to run implmentation again and the error was..

 >> Specified revision is Invalid

I searched the Xilinx support(online)for help.But couldnt find any
solution specific for version 3.1.They have provided the solution only
for version 1.5.

Kindly post me a solution to this problem.

Bye
Prasanth.A

Article: 53737
Subject: Re: Using DDR placed on the PCB with a Virted II...
From: "Bob" <nimby1_not_spmmm@earthlink.net>
Date: Fri, 21 Mar 2003 04:28:54 GMT
Links: << >>  << T >>  << A >>
Austin,

If you're gonna attempt DDR333 in a 2Vxxxx you should do two things:

1) Look at Xilinx' app note XAPP266
2) Get your own SI simulator (HyperLynx is excellent)

The appnote was written for FCRAM, but is useful (invaluable?) for doing DDR
that requires the use of the DQS's to latch the read data from the RAM. For
slower rates (like DDR200 and below) you can get away with only driving DQS,
and using a phase-shifted clock to capture the read data. However, at
333Mbps/pin it is probably manditory to utilize DQS as a read data strobe,
too. The difficult thing about using the DQS's to "locally" strobe the read
data into the IOB's is that it puts some strict requirements on which IOB's
you can use for the DQS lines and their associated DQ bytes (each DQS
strobes 8 DQ bits). Only the top IOB in the "tile" can be used for the DQS,
and there are other restrictions on the use of the other 3 IOB's in that
tile.

I would strongly recommend using a simulator to verify that you have enough
valid data time (at the RAM and at the FPGA). You'll probably need class 2
SSTL (SSTL2_II) to meet the requirements, so termination is critical to be
able to meet the setup/hold reqs, and also to meet the overshoot/undershoot
reqs.

DDR333 is NOT a trivial task.

Best of luck to you,
Bob





 The number of DCM's and BUFG's you'll need may surprise you.


"Austin Franklin" <austin@dark88room.com> wrote in message
news:v7kdfuef826if9@corp.supernews.com...
> > My thoughts were to use the SSTL_2_I I/O for address and control, using
> the
> > DCI for source termination which would provide a 25 ohm series resistor.
> > Use SSTL_2_II for the D/DQS signals for source and receiver termination,
> as
> > they are bidirectional, which would provide 25 ohm source termination
for
> > writes, as well as a pseudo second "VTT" termination for the reads.
> >
> > Externally, I was going to use 22 ohm source termination resistors on
the
> > D/DQS pins at the DDR, and use 50 ohm VTT termination.
>
> After some discussions with a memory SI engineer, he recommended using 56
> ohm VTT termination on the control signals, and 25 ohm VTT termination on
> the DQ/DQS signals, since the Xilinx will basically be providing basically
a
> 25 ohm VTT when using the SSTL_2_II IO for the DQ/DQS signals.
>
> > I'm not sure if the DCI/V2 can handle the clock termination using I/O
> > options though...so I was going to use external 33 ohm source
termination
> > resistors, with 120 ohm impedance matching resistors just after the
source
> > resistors,
>
> He also recommended removing the 33 ohm resistors and just using the Xilnx
> 25 ohm resistors in the IOBs, but putting 0 ohm resistors there to be able
> to tune it if need be.  He also recommended removing the first 120 ohm
> resistor that was just after the series terminators for CK/CK#.
>
> > and then another 120 just before the DDR, between CK/CK# (that did say
> DQ/DQ#...)
>
> he also recommended using N resistors on each CK/CK# at each chip, where N
> adds up to 120 ohms.
>
> This should be a good starting point.  There are some very important PCB
> constraints I won't go into here, unless someone else is interested.
>
> Austin
>
>
>
>



Article: 53738
Subject: how do implement the exponential algorithm in fpga?
From: chen.songwei@mail.zte.com.cn (Apollo)
Date: 20 Mar 2003 21:20:59 -0800
Links: << >>  << T >>  << A >>
(1-1/2^9)^7

Article: 53739
Subject: Re: programmer adapter for Xilinx XC9572
From: Falser Klaus <kfalser@IHATESPAMdurst.it>
Date: Fri, 21 Mar 2003 08:34:07 +0100
Links: << >>  << T >>  << A >>
In article <3E79D97D.451DBD2D@mi.iasf.cnr.it>, fiorini@mi.iasf.cnr.it says...
> hi,
> I want to program a XC9572 with a Hi-Lo system All-07 programmer.
> 
> Has anyone any idea of the connections for an adapter from PLCC84
> to DIL 48 ??
> 
> Thanks
> 
 
Why do you want to do that?
The XC9572 is made to be programmed in system, after mounting on the PCB.
I do not know this ALL07 programmer, but if it has a JTAG output 
connector you have to connect this to the TDO, TDI and TCLK pins of 
your CPLD.
Connecting the DIL48 socket to the CPLD will most certainly not work.

Buy a programming cable from Xilinx and use it together with their 
programming SW (it's free !).

Best regards 
-- 
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMdurst.it

Article: 53740
Subject: Re: FPGA choice (UK)
From: "Alex Gibson" <alxx@ihug.com.au>
Date: Fri, 21 Mar 2003 18:53:09 +1100
Links: << >>  << T >>  << A >>

"jools" <j.p.murphy@ncl.ac.uk> wrote in message
news:7fb35ec4.0303201113.2036367e@posting.google.com...
> Hi
>
> Does anyone have any recomendations for which "device" to use for the
> implementation of a simple CPU I have implemented in VHDL. This is a
> university project I have to complete as a result the number gates is
> very low so the simplest device possible would probably be most
> suited.
>
> Assuming I have chosen a suitable FPGA, what do I need to purchase to
> implement the code in the FPGA, do I need a development board or just
> a programmer, I need to spend as little as possible. What is the bare
> minimum to program it. Can I send the code off to an external company
> in the UK to program it for me??? <- very much prefered.
>
> Also after reearching the various FPGA manufacturers, Ive found that
> to order a FPGA or deelopement board requires ordering from the US to
> the UK. Are there no suppliers in the UK where I can get these
> products from simply by placing an online order as I would with any
> other component.
>
> Cheers
>
> jools

Program it yourself, it's as simple as plugging a dev board into parallel
cable
and running the programming software.

Doesn't the uni have a board you can borrow to demonstrate your code on ?

Have you download the xilinx web pack or similar and put your design in
to see what size device you need ?



For a spartan2 board digilentic
http://www.digilentinc.com/Catalog/digilab_2e.html
http://www.digilentinc.com/Catalog/digilab__io1.html   display / leds /
switches etc
http://www.digilentinc.com/Catalog/digilab_breadboard___wire-wrap.html
breadboard



Article: 53741
Subject: Glue logic beetween an Xscale PXA250 and PC104 Bus
From: "Timothée GROS" <sorg@no_spam_non_pas_de_spam_netcourrier.com>
Date: 21 Mar 2003 08:01:43 GMT
Links: << >>  << T >>  << A >>
Hello all,
Does anyone have a schema of the  glue logic necessary beetween a Intel 
Xscale PXA250 and a PC104 bus (or ISA) ?
It would be very useful for me.
Thank you, 
Timothée GROS

FU2 comp.sys.arm

Article: 53742
Subject: Re: programmer adapter for Xilinx XC9572
From: "Neeraj Varma" <neeraj@cg-coreel.com>
Date: Fri, 21 Mar 2003 13:39:07 +0530
Links: << >>  << T >>  << A >>
Hi Klaus - I think if Mauro wants to accomplish mass CPLD programming, a
hardware programmer like the Xilinx HW-130 or a 3rd party programmer like
the one from ALL-07 is more suitable than JTAG cable programming. However,
adapters for particular packages and devices can be very expensive...

If mass programming is not an issue, then you are right JTAG cable is just
the right thing. A simple low cost parallel cable (from Xilinx or Insight or
home made) coupled with free Webpack software will do the job very well....

--Neeraj



"Falser Klaus" <kfalser@IHATESPAMdurst.it> wrote in message
news:MPG.18e4deda8676a68c989694@151.99.250.3...
> In article <3E79D97D.451DBD2D@mi.iasf.cnr.it>, fiorini@mi.iasf.cnr.it
says...
> > hi,
> > I want to program a XC9572 with a Hi-Lo system All-07 programmer.
> >
> > Has anyone any idea of the connections for an adapter from PLCC84
> > to DIL 48 ??
> >
> > Thanks
> >
>
> Why do you want to do that?
> The XC9572 is made to be programmed in system, after mounting on the PCB.
> I do not know this ALL07 programmer, but if it has a JTAG output
> connector you have to connect this to the TDO, TDI and TCLK pins of
> your CPLD.
> Connecting the DIL48 socket to the CPLD will most certainly not work.
>
> Buy a programming cable from Xilinx and use it together with their
> programming SW (it's free !).
>
> Best regards
> --
> Klaus Falser
> Durst Phototechnik AG
> kfalser@IHATESPAMdurst.it



Article: 53743
Subject: source code for crc
From: "Benoit" <benoit.hamon@elios-informatique.fr>
Date: Fri, 21 Mar 2003 09:37:38 +0100
Links: << >>  << T >>  << A >>
Hi all,

I need to calculate and verify a CRC in frames,  at more than  4 Gbps in a
FPGA.
The common CRC implementation is based on a linear feedback shift register
architecture which can be used to process 1 bit per clock cycle.
Easy but slow tyically only for low rates.

To meet the requirements of CRC calculation for gigabit networks, a solution
is
to calculate CRC32 in several steps using "Galois Method".. .

So I'm looking for a free VHDL Source code using this method in FPGA.
Can you help me please ?.

Thanx,
    Benoit.





Article: 53744
Subject: how do implement the exponential algorithm in fpga?
From: chen.songwei@mail.zte.com.cn (Apollo)
Date: 21 Mar 2003 01:12:16 -0800
Links: << >>  << T >>  << A >>
1>1&#65293;0.001953125
2>&#65288;1&#65293;0.001953125&#65289;^6
3>&#65288;1&#65293;0.001953125&#65289;^1/2

Article: 53745
Subject: Re: Integrating an VHDL component in a project in Handel-C
From: "Alan Fitch" <alan.fitch@doulos.com>
Date: Fri, 21 Mar 2003 09:40:22 -0000
Links: << >>  << T >>  << A >>

"Gerardo Sosa" <gerardo_sr@yahoo.com> wrote in message
news:f4ee0441.0303182304.1fe77859@posting.google.com...
> Thanks Alan, I had done that, but the ISE give other
errors like follows:
>
> ERROR:NgdBuild:455 - logical net 'GND' has multiple
drivers. The possible
>    drivers causing this are pin G on block BG1_Ground with
type GND, pin PAD on
>    block B318_comp/GND with type PAD
> ERROR:NgdBuild:462 - input pad net 'GND' drives multiple
buffers. Possible pins
>    causing this are:  pin I on block B415_OBUF with type
OBUF, pin i on block
>    B318_comp/s1_7_ibuf with type IBUF, pin i on block
B318_comp/s1_6_ibuf with
>    type IBUF, pin i on block B318_comp/s1_5_ibuf with type
IBUF, pin i on block
>    B318_comp/s1_4_ibuf with type IBUF, pin i on block
B318_comp/s1_3_ibuf with
>    type IBUF, pin i on block B318_comp/s1_2_ibuf with type
IBUF, pin i on block
>
>
> I'm searching what's wrong now.
>
> Thanks for your time. If you know something I apreciate a
lot your help.
>

Another thing to check is that you haven't got pins on both
blocks, i.e.
I/O buffers on the VHDL model and on the HandelC model.
That's unlikely,
but possible. If the VHDL was synthesised (which I guess it
wasn't if
it's a RAM), then you need to check that "add IOBs" is
disabled in the
VHDL synthesis software

regards

Alan

--
Alan Fitch
HDL Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification *
Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,
Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                          mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573                           Web:
http://www.doulos.com

The contents of this message may contain personal views
which are not the
views of Doulos Ltd., unless specifically stated.


Article: 53746
Subject: Re: programmer adapter for Xilinx XC9572
From: Petter Gustad <newsmailcomp4@gustad.com>
Date: 21 Mar 2003 10:41:19 +0100
Links: << >>  << T >>  << A >>
"Neeraj Varma" <neeraj@cg-coreel.com> writes:

> Hi Klaus - I think if Mauro wants to accomplish mass CPLD programming, a
> hardware programmer like the Xilinx HW-130 or a 3rd party programmer like
> the one from ALL-07 is more suitable than JTAG cable programming. However,
> adapters for particular packages and devices can be very expensive...

Are these much faster than programming using JTAG? Assuming you're not
using a slow serial or parallel cable (e.g. a JTAG Technologies BV
DataBlaster, Xilinx MultiLinx USB, etc.)

The cards have to be tested after the CPLD's have been mounted anyway.
Then why not program the PLD and test the card in the same step? Of
course you would use a less fragile connector and more capable
software.

Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter

Article: 53747
Subject: Re: source code for crc
From: Petter Gustad <newsmailcomp4@gustad.com>
Date: 21 Mar 2003 10:55:23 +0100
Links: << >>  << T >>  << A >>
"Benoit" <benoit.hamon@elios-informatique.fr> writes:

> So I'm looking for a free VHDL Source code using this method in FPGA.
> Can you help me please ?.

http://www.easics.com/webtools/crctool


http://groups.google.com/groups?safe=images&ie=UTF-8&oe=UTF-8&as_umsgid=87ptutz6wz.fsf%40filestore.home.gustad.com&lr=&hl=en

Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter

Article: 53748
Subject: FPGA FFT Questions
From: stenasc@yahoo.com (Bob)
Date: 21 Mar 2003 04:32:42 -0800
Links: << >>  << T >>  << A >>
Hi Folks,

Some questions for the experts.

1..What is the benefits of a complex fft rather than
a non-complex fft? What are the benefits and in
for what applications would each be used?
 
2...Is the fft output from an asic or fpga normally in
logarithmic or non-logarithmic form?

Thanks for any info

Bob Carter

Article: 53749
Subject: EPXA1 Development Kit Getting Started
From: Franz Hollerer <nospam@nospam.com>
Date: Fri, 21 Mar 2003 14:10:40 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hi,

I try to compile the hello example described in the
EPXA1 Development Kit Getting Started User Guide using
GNUPro.

If I call 'make debug' from the command line it works,
but if I use Quartus II v2.1 I get some non-informative error message:

> Design Debug: Software build was unsucessful. 0 errors, 0 warnings.

Can someone give me a hint what's going wrong?

Best regards,

Franz Hollerer



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