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Messages from 58175

Article: 58175
Subject: Re: How to edit encrypted NGC file produced using XILINX ISE 5
From: Shalin Sheth <Shalin.Sheth@xilinx.com>
Date: Wed, 16 Jul 2003 08:21:53 -0700
Links: << >>  << T >>  << A >>
You cannot see or edit the NGC file produced by XST the Xilinx synthesis 
tool.

Shalin-

Isaac wrote:
> Hi mates 
> Could any body tell me how to edit and see the encrypted NGC file
> produced by using XILINX ISE 5 version.
> 
> Cheers 
> 
> Rgds
> 
> ISAAC


Article: 58176
Subject: Xilinx ECS Schematic Entry
From: "Peter Mash" <pwtm2@cam.ac.uk>
Date: Wed, 16 Jul 2003 17:00:28 +0100
Links: << >>  << T >>  << A >>
Dear people,

I create a module, for example, a simple adder. It synthesises fine. I then
create a schematic symbol from it, but the ".sym" file contains very little
information, and when I place it in to a schematic module in the project, no
symbol appears.

Has anybody else had the same problem? I am using the latest ISE (5.2 with
SP 3) as part of the WebPack.

Regards to all

PETE MASH




Article: 58177
Subject: Re: I/Os with Cypress chip
From: "Brad Smallridge" <bsmallridge@dslextreme.com>
Date: Wed, 16 Jul 2003 09:25:40 -0700
Links: << >>  << T >>  << A >>
It would appear, however, that I can get the Global Signals to work as
inputs.  But when I do, then I loose an I/O.  That doesn't seem right.  Like
buying a three input OR gate and only being able to use two of the inputs at
any one time.

Brad



Article: 58178
Subject: Re: Xilinx ECS Schematic Entry
From: "Peter Mash" <pwtm2@cam.ac.uk>
Date: Wed, 16 Jul 2003 17:32:14 +0100
Links: << >>  << T >>  << A >>
Answer found:

It's because the schematic symbol generator doesn't support Verilog 2001

Regards

PETER MASH


"Peter Mash" <pwtm2@cam.ac.uk> wrote in message
news:bf3stb$2rr$1@pegasus.csx.cam.ac.uk...
> Dear people,
>
> I create a module, for example, a simple adder. It synthesises fine. I
then
> create a schematic symbol from it, but the ".sym" file contains very
little
> information, and when I place it in to a schematic module in the project,
no
> symbol appears.
>
> Has anybody else had the same problem? I am using the latest ISE (5.2 with
> SP 3) as part of the WebPack.
>
> Regards to all
>
> PETE MASH
>
>
>



Article: 58179
Subject: Re: Xilinx ECS Schematic Entry
From: "carmen lee" <>
Date: Wed, 16 Jul 2003 10:21:01 -0700
Links: << >>  << T >>  << A >>
ECS in ISE is terrible bad.   

1) graphic looks ugly
2) can't push pop hiarchy macros (the   most terrible thing) 
3) difficult to edit symbols 
4) it was for documentation, not for design entry
5) bugs ( like the one you report ), everytime open a macro 
   schematic, it gives an error, ask to overwrite,... 
6) difficult to name/rename buses and signals 
7) hard copy looks ugly too



Article: 58180
Subject: Re: JTAG standard connector
From: "..:: Gabster ::.." <gabsterblue@hotmail.com>
Date: Wed, 16 Jul 2003 13:39:46 -0400
Links: << >>  << T >>  << A >>
I will finally use my own pinout (VCC, GND, TCK, TDO, TDI and TMS all in a
row) since the flying leads make it very easy to plug with any pinout.

thanks

"Hal Murray" <hmurray@suespammers.org> wrote in message
news:vh9elr70b9td9a@corp.supernews.com...
> >    I'm making a pcb with a xilinx FPGA. I will obviously put a JTAG
header
> >on my board. I simply want to know what is the standard pinout for the
> >header. Looking a the specs for the Parallel IV cable from xilinx I found
> >the following pinout:
> ...
> > Conclusion, I don't know what to use. The pinout from xilinx seems space
> >wasteful. What would you put on your board?
>
> What are you going to connect it to?
>
> There are various semi-smart boxes that have an ethernet port (or
RS232/USB)
> and a JTAG connector.  The ones I've seen have a ribbon cable with lots of
> grounds.  I think the JTAG standards committee blessed this setup and
probably
> even has mechanical specs on the connector.  (I think I've seen a reset
signal
> on pin 12 or 14.)
>
> The wasteful grounds will let you use a longer cable before you run into
> signal ingegrity problems.
>
> If you are just using a JTAG pod with short individual wires setup to push
on
> 0.025 pins, use any connector that's convenient.
>
> -- 
> The suespammers.org mail server is located in California.  So are all my
> other mailboxes.  Please do not send unsolicited bulk e-mail or
unsolicited
> commercial e-mail to my suespammers.org address or any of my other
addresses.
> These are my opinions, not necessarily my employer's.  I hate spam.
>



Article: 58181
Subject: Digital Root circuit using tree of 4-bit CLA's with Cout fed into Cin
From: lrl@eth.net (lrl)
Date: 16 Jul 2003 10:57:30 -0700
Links: << >>  << T >>  << A >>
Hi,

In order to generate  hexadecimal Digital Root  of a number (i.e,
sum-of-hexdigits until it reduces to a single hex number - a nibble)

	For  e.g 0x123a = 0x1 + 0x2 +0x3 +0xa = 0x10 = 0x1 + 0x0 = 1 is the
hex digital root of (0x123a)

I am planning to use tree of 4-bit Carry-Look-Ahead adders with the
Cout fed into Cin of the same CLA.

Question: Can I directly fed back the Cout signal to Cin at each CLA
to get the Digital Root .  Will it not form a combinational loop? Due
to feedback will it affect the next level CLA's o/p.

Thanks
lrl

Article: 58182
Subject: Re: Graduation Day: My first 4-layer PCB
From: "..:: Gabster ::.." <gabsterblue@hotmail.com>
Date: Wed, 16 Jul 2003 13:58:25 -0400
Links: << >>  << T >>  << A >>
It's getting pretty clear how I'll route this board. Thanks to all. I hope
other rookies like me will read this post as it is very instructive.

Hal, can you tell me more about setting the input/output blocks
(IOBs)...this is something unknown to me.

"Hal Murray" <hmurray@suespammers.org> wrote in message
news:vha8reee823o6a@corp.supernews.com...
> >I'm made many 2-layer PCB's in the past years, but I'm about to start the
> >desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx
> >Spartan IIE XC2S300 in PQ208 package running at 12MHz), 3 power supply
> >regulators, an oscillator block, a PROM and a logic IC.
>
> I'll start by repeating Kolja's suggestion to get a copy of
> "High Speed Digital Design - A Handbook of Black Magic".
> Johnson and Graham.  List is $95.
>
> It won't solve this problem directly, but it will give you
> the background you need to think about this area.  It's also
> fun reading.  Every time I go to look something up I get sucked
> into rereading some other section.  It's got the right level
> of math for me.  The formulas are there if I ever need them,
> but it's got enough rules of thumb that I can (mostly) avoid
> the formulas.
>
> One thing to keep in mind is that your 12 MHz isn't the
> critical parameter, it's the edge rate on the signals.  You
> want to run the edges as slow/gentle as you can.  Set the
> IOBs to low drive current and such.
>
>
> If I was working on a board like this, I'd start by asking
> how I was going to get the power to the FPGA.
>
> Multiple power supplies are a lot simpler if you have a plane
> per power rail and another for ground.  Since you only have 2 layers
> for power planes, you are off by 2 from the simple case.
>
> I'm assuming that you can place the other parts so that the general
> layout is (say) 2.5 V parts on the left and 3.3 V parts on the right.
> If so, then you can "split" the power plane down the middle with a "cut"
> in the copper and get two planes on one layer.  Note that you have to
> think about any signals that cross that cut.  The mirror currents have
> to get from one side of the split to the other.  They can't jump
> across the cut.  (General idea is "don't do that".)
>
> That cut might run down the middle of the FPGA.
>
> That (hopefully) saves one plane, but you still have one to go.
>
> Is the routing on your board going to be "nice"?  At least around
> the FPGA?  Can you basically run most of the signals directly from
> the pads on the top layer over to where they connect?  (or do you
> have all sorts of signals crossing and tripping over eachother?)
>
> If the routing is clean, then the top layer under the chip isn't
> needed for routing.  I'd put a small plane in there for the core
> voltage.  It gets low inductance connections to all the core pins.
>
> Then I'd put bypass caps on the bottom, under the chip, inside
> the pads.  Again, that assumes that space isn't needed for routing.
> That's where they can get good connections to both the core "plane"
> and the ground plane.
>
> > 3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1F
per
> > power pin (1.8V and 3.3V) + one 10F per power supply (1.8V and 3.3V).
Is
> > that accurate? Should I do more? What should I avoid?
>
> That's a reasoanable ballpark.  Inductance is what you want to
> avoid.  Vias count, so do long traces from pads to vias.
>
> > 4) What is the concept surrounding islands on the power plane? What
should
> > that plane look like? What should I avoid? What the hell about it, this
> > plane is a mystery for me!!!
>
> A plane is just a convenient way to get low-inductance.  You have to
> find a way to position the planes and the chips (and bypass caps)
> so they can connect easily (rather than running long traces way
> over to there).
>
> Don't forget remote sense on the power regulator.  How much IR drop will
> you have between the regulator on the far corner of the board and the
> chip where the power gets used?  (Planes are low resistance too.)  This
> is especially important for the core voltage to the FPGA if you don't have
> a plane to dedicate to it.  Might be OK if you can make the feeder trace
> fat enough.  Just another thing for the checklist.
>
> -- 
> The suespammers.org mail server is located in California.  So are all my
> other mailboxes.  Please do not send unsolicited bulk e-mail or
unsolicited
> commercial e-mail to my suespammers.org address or any of my other
addresses.
> These are my opinions, not necessarily my employer's.  I hate spam.
>



Article: 58183
Subject: Re: Graduation Day: My first 4-layer PCB
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 16 Jul 2003 18:49:05 -0000
Links: << >>  << T >>  << A >>
>Hal, can you tell me more about setting the input/output blocks
>(IOBs)...this is something unknown to me.

Look in the data sheets. The LVTTL option has several sub-options
with different drive strengths.  Lower current takes longer to
charge up external caps (traces and other input pins), but it
makes less noise and EMI/SSO problems.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 58184
Subject: Re: "ML300 Embedded" Mapping Help
From: antti@case2000.com (Antti Lukats)
Date: 16 Jul 2003 12:21:02 -0700
Links: << >>  << T >>  << A >>
"tk" <tokwok@hotmail.com> wrote in message news:<bf3iqc$sh4$1@www.csis.hku.hk>...
> thx very much, antti !!!!!
> 
> > 1) I use Verilog (VHDL gives error in v2pdk_lib_utils or somewhere..)
> i also encounter the VHDL problem
> too bad, i'm not familiar with Verilog!!

same here :( 
 
> btw, how's ur progress with EDK ?

not much, tried a little to get the TFT working, but the
tft.c vs xtft.c files are all messed up, also something is wrong
with the timing or plb to line buffer - the screen I see is
all in stripes like 8 pixels ok, then 8 pixels dark.

I am little in the wait up mode, as the tft and linux will
most likely not used in the project I work for, more like
doing the research for the future.

> any good news for its support with Linux ?

same - used ELDK from www.denx.de to write hello.c and run it
on ml300 MVista linux, worked ok, and thats it.

when a EDK design (linux cap) comes will checkit again.

in the meanwhile need to get some hardware designed

currently was fighting with Microblaze and 16 Bit Flash memory
as usual when all things are right then it works right away
but it takes a lots of time to get things right :)

antti

Article: 58185
Subject: Re: vertex2 pci pinout
From: antti@case2000.com (Antti Lukats)
Date: 16 Jul 2003 12:24:34 -0700
Links: << >>  << T >>  << A >>
rjd@transtech-dsp.com (rob d) wrote in message news:<e44f5c31.0307160450.1cbce4d3@posting.google.com>...
> Does anyone know where I can get the pinouts needed for the Xilinx PCI
> core. I think that I can get away with a simple slave only interface
> (which I can write myself) but I don't want any surprises if I
> ultimately need the Xilinx core for mastering.
> 
> Thanks in advance
> 
> Rob

there are irdy and trdy pins on the packages (usually) connect them to 
irdy and trdy on pci thats almost all

antti

Article: 58186
Subject: Re: JTAG and Xilinx
From: Neil Glenn Jacobson <neil.jacobson@xilinx.com>
Date: Wed, 16 Jul 2003 12:58:35 -0700
Links: << >>  << T >>  << A >>


John Williams wrote:
> 
> I wrote:
> 
>> Specifically, will iMPACT puke if there's a non-xilinx device in the 
>> chain?  
> 
> 
> After RTFM the iMPACT manual claims it can handle this.  Anyone actually 
> done it and have any comments?

It works.  You can use it.  Some BSDLs may have syntax errors and you 
skip them by telling iMPACT you don't have a BSDL file when it asks and 
then tell iMPACT the instruction register length

> 
>> What about the XMD program that drives the JTAG port to do debugging 
>> for Microblaze and V2PRo PPC systems?
> 
> 
> Still curious about this one.
> 
> Cheers,
> 
> John
> 


Article: 58187
Subject: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 16 Jul 2003 16:28:45 -0400
Links: << >>  << T >>  << A >>
Before Stratix, Xilinx really did have the corner on DSP capability.
Stratix gives Altera its first real contender for heavy duty DSP.  There
are still some things that Virtex does (notably the SRL16 capability) that
have no parallel in stratix, but then the casual user is not going to have
much access to those features anyway (to take full advantage, you need to
design specifically for those features).  For example, the SRL16's can be
used as reloadable LUTs, which makes DA filters attractive for block
adaptive filters.  This option is precluded going with a non-Xilinx chip
simply because there is no equivalent function.  Stratix is a bit faster,
but you also have fewer multipliers for a given number of marketing
gates.  Best to evaluate the chips on their merits as applied to your
target application.  If you comfort zone is Altera, and you can make your
application work there without too much pain, it may be best to stay in
your comfort zone.

Michael S wrote:

> I know that respective regulars of this newsgroup don't like to give
> decisive answers to A vs. X type of questions, but... This last visit
> of the Xilinx representative was a shocker !
>
> A bit of the background. We are as pure Altera shop as it goes. As
> such we don't follow Xilinx products very closely. When we
> occasionally did the check we typically found out that for our
> applications there are no big differences between offerings of Xilinx
> and Altera so there was no reason to step out of the comfort zone of
> established routine. We believed that this situation will last forever
> - it's what the competition is invented for, isn't it ?
>
> I have to mention that up until recently we never faced the project
> that was very multiplication-intensive on its FPGA side. The project
> we are  trying to achieve now is exactly like this- very multiply
> (MAC) intensive almost 100% FIR filtering. As usual, initially we
> figured out a possible Altera solution. It was a bit pricey and
> required two (or four smaller) chips but we thought that it is the
> state of the art and so be it. But here come a representatives from
> Xilinx and showed as their Virtex-II Pro parts... As I mentioned above
> it was a shock: about three time as many multipliers as in similar
> size/similar price Stratix chip. Two and a half times more multipliers
> than in significantly bigger Startix chip !
> XC2P30 - 136 18x18 Dedicated multipliers
> EP1S30 - 48  18x18 Embedded multipliers (the price of the parts is
> similar to XC2P30)
> EP1S40 - 56  18x18 Embedded multipliers
>
> I suppose that Startix parts are a bit faster, but it doesn't make a
> difference for our application. Doing the computational part of the
> design in the distinct (faster) clock domain doesn't make much sense
> when the main (data acquisition) clock already runs at 190MHz. And for
> 190MHz VirtexII-Pro is o.k. For us as far as Stratix unable to run
> calculation at 380MHz its speed advantage doesn't care.
>
> Since I have no experience with Xilinx in general and with Virtex-II
> Pro in particular I am afraid I missed something. It's almost too good
> to be true. IMHO if there is no catch (availability ?) here the XC2P
> parts draws Stratix into irrelevance for nearly all DSP-intensive
> applications.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 58188
Subject: Re: what are libraries for??
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Wed, 16 Jul 2003 13:45:40 -0700
Links: << >>  << T >>  << A >>
Thomas Stanka wrote:
> Mike Treseler <mike.treseler@flukenetworks.com> wrote:
> 
>>If I have constants and functions to share between processes,
>>I use the default "work" library, as this is much less trouble
>>and more portable than naming and maintaining my own library.
> 
> 
> I don't think that this is very portable. If you reuse your code, you
> have to be very careful about constant names, there might be more
> packages including a constant with a specific name. Eg. you use a
> library bus_master and a library bus_slave, you don't have to care
> about constants names with the same name for master and slave IP.

Yes, there could be name conflicts, but this
would be discovered at compile time and is easily
corrected in the source file being edited.

The upside is that all the developers can CVS to/from
a single directory and compile with a very simple make procedure.

I agree that this scheme might become difficult
for a large number of developers.


   -- Mike Treseler


Article: 58189
Subject: Re: Xilinx --> WARNING:DesignRules:372
From: Ray Andraka <ray@andraka.com>
Date: Wed, 16 Jul 2003 17:19:06 -0400
Links: << >>  << T >>  << A >>
FPGA tools are not designed to handle async logic hazards.  Gating the
clock is putting an asynchronous circuit in your clock path.  You can wind
up with runt clock pulses or glitches on your clock which will cause
improper operation.  Gating also introduces a sizable skew between clock
nets, since the gated clock is distributed on general interconnect rather
than on the dedicated clock lines (not to mention the delay of the gate
itself).  If you are very careful, you can use gated clocks, however 'very
careful' includes managing the delays in both the logic and the routing,
forcing cover terms (keeping the tools from optimizing them out) among
other things.  Frankly, if you are designing with gated clocks, you are
most likely nowhere near saavy enough to handle doing it correctly within
the constraints of the tools.  Best advice is to stick to strictly
synchronous design, which means that all the clocks are from a common
freerunning clock net(s).

Basuki Endah Priyanto wrote:

> Hi,
>
> Anybody can give me more detailed explaination on the following message
> :
>
> WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net
>    iuser_ap_my_trans_i3_i6__n0049 is sourced by a combinatorial pin.
> This is not
>    good design practice. Use the CE pin to control the loading of data
> into the
>    flip-flop.
>
> What is the implication if I just ignore the warning message ?
>
> Thanks.
>
> BR,
> Buzz

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 58190
Subject: Re: Cyclone vs Spartan-3
From: Ray Andraka <ray@andraka.com>
Date: Wed, 16 Jul 2003 17:28:45 -0400
Links: << >>  << T >>  << A >>
I can totally sympathize withthe slow dodgy internet connections.  While I have
cable here in the office, and that is brought in through a firewall/router, I
can't get high speed access in North Central Pennsylvania where I like to spend
time in the summer (a few miles north of Williamsport).  There the options are
incredibly lousy phone lines or satellite.  Period.  The satellite option seems
to only be fast in one direction, and it is prohibitively expensive.  DSL, ISDN
and cable are not available out there, and probably will never be.  I am sure
there are plenty of other places in the country in the same situation.

David Brown wrote:

> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:3F04660E.33F1EF2@yahoo.com...
> > David Brown wrote:
> > >
> > > I fully support the option of being able to buy the CD - even for those
> of
> > > us with reliable internet connections, there are times where a single CD
> in
> > > the post can be more convenient.  And I agree that reliability is the
> main
> > > factor for the internet connection - a 57kbaud modem can download 150 MB
> > > overnight, but only if it is reliable enough!  But is it really that
> hard or
> > > that expensive to get a solid line?  I find it is an essential
> requirement
> > > for my work - speed is not critical (we have a 386 kbit ADSL line for
> the
> > > office), but reliability is.
> > >
> > > Incidently, you might like to try NetAnts for downloading over a dodgy
> line,
> > > although I'm sure everyone has there favourite download utility.
> >
> > I don't know about my line being "dodgy".  I just know that the
> > combination of ISP, phone line, modem, OS and browser software makes it
> > hard to get a 17 hour download to complete without error.  It is also a
> > PITA tying up the modem connection for a day while this is going on.  It
> > makes it very slow to browse or even get emails.
> >
> > As to the effort required to get a solid data line, there is virtually
> > *nothing* you can do if your voice capability is not affected.  I have
> > talked to the phone company before and they have made it clear that a
> > phone line is not a data line.  They guarantee no specific data rate.
> > DSL is not available in the second largest city in Maryland and Cable
> > Modem is a fixed installation, it can not be easily moved from one
> > computer to another.  Cable Modem also goes out in nearly every storm
> > along with the TV.
> >
> > I only wish I could get connected at 57 kbps!
> >
>
> Can't you use a firewall/router connected to a cable modem?  Of course, it
> won't fix the storm problem, and not every isp's contract will let you
> connect a whole network to their system.  Can you get ISDN there?  I have no
> real idea whether that is available in the US or not - it is popular in
> Europe for businesses, and used to be common for internet access before ADSL
> became so widespread.  Maybe you can get radio internet connections?  Many
> of these are pretty ropey, but there are some ISP's here in Norway that
> manage to do it well, so it's certainly possible.  Other than that, I can
> offer nothing but sympathy (and surprise - I knew the US had a problematic
> telephone system, but I didn't know it was that bad).

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 58191
Subject: Re: device selection for game system
From: Ray Andraka <ray@andraka.com>
Date: Wed, 16 Jul 2003 17:38:03 -0400
Links: << >>  << T >>  << A >>
I recall seeing recently someone with an FPGA (I think it is Xilinx
Spartan2) board for a gameboy advance.  I'll have to look around to see
where it was, but I did get the distinct impression it is commercially
available.


David Tucker wrote:

> I'm working on implementing a custom game boy advance cartrige with
> the following features:
>
>  - 4-16MByte flash rom (bank switched to a 24 pin buss)
>  - 32kbyte save ram (game state save, can be stored in flash rom if
> needed)
>  - usb-to-pc link
>  - in system reprogramability via usb
>  - hardware assist for MP3/OGG decoding or similar lossy compression
>   (target compression is 8bit, 2-8Kbit/sec, for 30min of audio in
> 2mbyte of rom)
>
> Space is a huge concern, my target board size is 1x2 inches.  Plus my
> target cost in quantitys of 1,000 or more is $10-$15 total for the
> board and everything.  Im looking at using the intell strata flash
> roms at ~$8 for a 4MByte chip in quantitys so that only leaves me
> ~$2-$7 for my remaining logic.  To keep costs down as well as size Im
> looking on implementing the rest of the logic in an FPGA or CPLD.
>
> Currently Im looking at the Altera MAX 3000a series of chips.  Is
> there enough power in the max chips to do what I want?  What chips
> would you recomend?  Should I just implement the controll logic in an
> ASIC and pick up an Atmel 8051 for the USB and MP3 decoder?
>
> thanks for your time,
>    David Tucker

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 58192
Subject: Re: vertex2 pci pinout
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Thu, 17 Jul 2003 07:46:10 +1000
Links: << >>  << T >>  << A >>
rob d wrote:
> Does anyone know where I can get the pinouts needed for the Xilinx PCI
> core. I think that I can get away with a simple slave only interface
> (which I can write myself) but I don't want any surprises if I
> ultimately need the Xilinx core for mastering.

You can probably download a data sheet from the IP cores (or IP 
central?) area on www.xilinx.com

Cheers,

John


Article: 58193
Subject: Re: Cyclone vs Spartan-3
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 16 Jul 2003 18:23:32 -0400
Links: << >>  << T >>  << A >>
Yes, one of the reasons that I have not gone with Cable or DSL (only
availble at my home rather than at my office) is because I am then stuck
with that one service unless I want to have two providers.  I have yet
to find a high speed provider that gives more than lip service to
providing dialup access when not in the main location.  I also have a
summer (or any other time of year when I want to get away) home and
oddly enough, I can get higher modem rates on the 10 mile long phone
line than I can here where I am only 1.2 miles from the CO, but working
through a concentrator (pair gain amplifier according to the phone
tech).  

This time next year I expect I will co-locate office and home in the
same city at least and will take a harder look at the high speed market
again.  



Ray Andraka wrote:
> 
> I can totally sympathize withthe slow dodgy internet connections.  While I have
> cable here in the office, and that is brought in through a firewall/router, I
> can't get high speed access in North Central Pennsylvania where I like to spend
> time in the summer (a few miles north of Williamsport).  There the options are
> incredibly lousy phone lines or satellite.  Period.  The satellite option seems
> to only be fast in one direction, and it is prohibitively expensive.  DSL, ISDN
> and cable are not available out there, and probably will never be.  I am sure
> there are plenty of other places in the country in the same situation.
> 
> David Brown wrote:
> 
> > "rickman" <spamgoeshere4@yahoo.com> wrote in message
> > news:3F04660E.33F1EF2@yahoo.com...
> > > David Brown wrote:
> > > >
> > > > I fully support the option of being able to buy the CD - even for those
> > of
> > > > us with reliable internet connections, there are times where a single CD
> > in
> > > > the post can be more convenient.  And I agree that reliability is the
> > main
> > > > factor for the internet connection - a 57kbaud modem can download 150 MB
> > > > overnight, but only if it is reliable enough!  But is it really that
> > hard or
> > > > that expensive to get a solid line?  I find it is an essential
> > requirement
> > > > for my work - speed is not critical (we have a 386 kbit ADSL line for
> > the
> > > > office), but reliability is.
> > > >
> > > > Incidently, you might like to try NetAnts for downloading over a dodgy
> > line,
> > > > although I'm sure everyone has there favourite download utility.
> > >
> > > I don't know about my line being "dodgy".  I just know that the
> > > combination of ISP, phone line, modem, OS and browser software makes it
> > > hard to get a 17 hour download to complete without error.  It is also a
> > > PITA tying up the modem connection for a day while this is going on.  It
> > > makes it very slow to browse or even get emails.
> > >
> > > As to the effort required to get a solid data line, there is virtually
> > > *nothing* you can do if your voice capability is not affected.  I have
> > > talked to the phone company before and they have made it clear that a
> > > phone line is not a data line.  They guarantee no specific data rate.
> > > DSL is not available in the second largest city in Maryland and Cable
> > > Modem is a fixed installation, it can not be easily moved from one
> > > computer to another.  Cable Modem also goes out in nearly every storm
> > > along with the TV.
> > >
> > > I only wish I could get connected at 57 kbps!
> > >
> >
> > Can't you use a firewall/router connected to a cable modem?  Of course, it
> > won't fix the storm problem, and not every isp's contract will let you
> > connect a whole network to their system.  Can you get ISDN there?  I have no
> > real idea whether that is available in the US or not - it is popular in
> > Europe for businesses, and used to be common for internet access before ADSL
> > became so widespread.  Maybe you can get radio internet connections?  Many
> > of these are pretty ropey, but there are some ISP's here in Norway that
> > manage to do it well, so it's certainly possible.  Other than that, I can
> > offer nothing but sympathy (and surprise - I knew the US had a problematic
> > telephone system, but I didn't know it was that bad).
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 58194
Subject: Re: Xilinx ECS Schematic Entry
From: Dave Blevins <blave@xilinx.com>
Date: Wed, 16 Jul 2003 15:45:34 -0700
Links: << >>  << T >>  << A >>


carmen lee wrote:

> ECS in ISE is terrible bad.

It's always helpful if you mention what version you're talking about. Is
this 3.1i? 4.1i? 5.1i?

> 1) graphic looks ugly

In what way? It's a vector-based graphic application... What would you
like to see changed?

> 2) can't push pop hiarchy macros

Push *will* work, if you ensure that the underlying schematic that
you're trying to push into has been explicitly Added to the project as a
Source, before attempting the push (this is done via Project Navigator's
Add Source function). Unfortunately Pop does not work - ECS needs some
source status information that ProjNav needs to provide .

The overall Push/Pop behavior will be improved in the release slated for
next year (let's call it "7.1i"), and it should work as you expect it to
after that. New schematics will be automatically added to the project
when they're created, and you'll be able to Pop back up to a schematic's
parent symbol.

> 3) difficult to edit symbols

In what way?

> 4) it was for documentation, not for design entry

No, it's for design entry. It works great for documentation too, but its
main reason for existence is to draw logic and interconnect.

> 5) bugs ( like the one you report ), everytime open a macro schematic,
> it gives an error, ask to overwrite,...

Have you contacted the Xilinx Hotline about this? I am not familiar with
this issue.

> 6) difficult to name/rename buses and signals \

In 5.1i, a "context" (right mouse button) menu item was added to make
this easier.

> 7) hard copy looks ugly too

I'm not sure what you mean by this either, but next year's version will
let you control the line width of printed objects. You'll also be able
to have a print-specific color scheme, in addition to the current
user-customizable schemes.


Below you'll find partial lists of the enhancements made in the current
version (5.1i), the upcoming version (6.1i), and next year's version
("7.1i"). These lists do not include bug fixes....

I think you'll see that we are continuing to significantly enhance the
ECS application with every release.

cheers,

Dave Blevins
Xilinx, Inc.

-----------------


ECS Enhancement Summaries


5.1i (i.e. current version of ISE)

- Significant improvements to Attribute Handling  creation, editing,
and control of attribute visibility on sheet
- Easier renaming of nets/buses
- Revised copy/paste algorithm handles net/instance names better
- Much better copy/paste behavior when copying/moving large groups of
objects
- Automated naming of nets connected to a named bus
- Zoom In/Zoom Out can be dynamically performed while in any Mode (via
<ctrl> drag)
- User-definable color schemes for schematics
- Context-sensitive context (right mouse button) menus

-------------------------

6.1i (to be released in the next few months)

Schematic Editor -

- The "Generate HDL Template from Symbol" Tool, also available in the
Symbol Editor, allows an HDL source file with inputs and outputs
corresponding to the currently selected symbol to be generated.
- Bustaps are automatically created when a wire is drawn between a bus
and a pin. This feature can be disabled if desired.
- "Quick" I/O Marker feature - in Add I/O Marker mode, clicking or
drawing a box around symbol pin(s) will automatically add a short wire
and I/O Marker of the correct direction to each pin.
- A group of selected Instances or I/O Markers can be aligned using the
Align command.
- The Last/Next View feature allows previously used viewpoints/zoom
levels to be recalled.
- New autoscrolling feature causes the viewpoint to automatically scroll
when the user drags the mouse cursor to the page edge during certain
operations (Zoom to Box, Add Line, Add Wire, etc.). The "hot zone" size
and scrolling speed can be adjusted via the Preferences dialog.
- "Snap To" feature for I/O Markers - when adding an I/O Marker, it will
snap to the nearest wire or symbol pin. Four small squares will be
displayed when the cursor is close enough for the snap to occur.
- The Text Alignment command allows a group of selected text items to be
aligned either left or right, or top or bottom as appropriate. Note: to
align a set of net names, the user must select the "Attribute windows
only" option in the Select Options pane before selecting the names.
- The "Symbol Info" command will display a data sheet, if one is
available, for the currently selected symbol in a document viewer
window.
- When moving a visible attribute (e.g. Instance Name), a line is drawn
from the attribute to the corresponding instance's origin, so that it's
always clear what the attribute is associated with.
 -Miscellaneous DRC improvements have been implemented.
- "Rename Selected Instance" makes renaming objects easier.
- A "Select" button has been added to the Find dialog, allowing found
item(s) to be selected directly from the Find function, rather than
having to close the dialog and then select the item(s).

Symbol Editor -

- When a pin is added, an attribute window for the corresponding pin
name is automatically added (optional). Both the relative position and
the distance from the pin of the attribute window are user-controllable.

RTL Viewer -

- The Viewer can now flatten sub-modules to show their contents, rather
than requiring the user to push into them. The user can select the size
of modules that should be flattened using the "Minimum Number of -
Instances Per Page" preference.
- The user can now cross-probe from RTL instances to the corresponding
HDL line numbers, where possible.
- Support for incremental synthesis has been added.
- Instance and Symbol names can now be added to RTL Views. Note that
these are temporary; RTL Views are stored in memory (not on disk)  and
are discarded when the RTL Viewer is closed.
- Finite State Machine symbol support has been added.
- Multiple-bit In/Out ports on instances are now notated with their
width.
- Double-clicking on an object in the Hierarchy View now causes that
object's underlying schematic to be generated.

-------------------------

Some Things Planned for 7.1i

- Improved macro/hierarchy push-pop operations
- Allow RTL views to be saved as read-only schematics, along with
instance/symbol name annotations if desired
- Optional: ECS windows can be "docked" into Project Navigator
- More DRC checks
- Printing options to allow changes to line widths - e.g. nets, buses,
etc.
- Separate color scheme for printing
- ...and many more...


.end.



Article: 58195
Subject: Altera ByteBlaster Standalone Programming Utility
From: Jim Flanagan <jflan@ieee.org>
Date: Wed, 16 Jul 2003 23:45:34 GMT
Links: << >>  << T >>  << A >>
[This followup was posted to comp.arch.fpga and a copy was sent to the 
cited author.]

Hi..
    I am searching for a 'standalone' command line utility that will 
allow me to program Altera CPLD parts using the ByteBlasterMV cable 
and WITHOUT using Max-Plus,etc.  The MaxPlus sw comes bundled with a 
small executable (with 'C' source) that will allow you to program using 
.RBF (raw binary files) but not .POF files.  Either I need to modify
the source to accomodate POF files (don't have the specification, any 
help?) or get a utility that will convert POF to RBF format.

In any event, I could use some direction.  The reason for the standalone
tool, is that I want to integrate the CPLD programming into a production 
environment and do not want an operator to have to run a program such
as MaxPlus.  

Any help would be appreciate... Thanks.

Jim

Article: 58196
(removed)


Article: 58197
Subject: Re: vertex2 pci pinout
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Wed, 16 Jul 2003 17:25:08 -0700
Links: << >>  << T >>  << A >>

Hello Rob,

I am fairly certain you won't find the pinout in the
IP data sheet.  There are a lot of pinouts and we have
not been publishing them in any format other than the
UCF constraints.  And for those, you need to have access
to the core.

The best thing for you to do is to look at the data sheet,
find the implementation you are interested in, and then
ask your local FAE or sales representative for the info.
They should be able to get it to you.  There's nothing
super secret about it...

Thanks,
Eric Crabill

Article: 58198
Subject: Re: Digital Root circuit using tree of 4-bit CLA's with Cout fed into Cin
From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Thu, 17 Jul 2003 01:04:33 GMT
Links: << >>  << T >>  << A >>

"lrl" <lrl@eth.net> wrote in message
news:c8f17d2e.0307160957.2d21c698@posting.google.com...
> Hi,
>
> In order to generate  hexadecimal Digital Root  of a number (i.e,
> sum-of-hexdigits until it reduces to a single hex number - a nibble)
>
> For  e.g 0x123a = 0x1 + 0x2 +0x3 +0xa = 0x10 = 0x1 + 0x0 = 1 is the
> hex digital root of (0x123a)
>
> I am planning to use tree of 4-bit Carry-Look-Ahead adders with the
> Cout fed into Cin of the same CLA.
>
> Question: Can I directly fed back the Cout signal to Cin at each CLA
> to get the Digital Root .  Will it not form a combinational loop? Due
> to feedback will it affect the next level CLA's o/p.

I believe that can be done.  Consider how a ones complement adder works.

Well, I would think that you would need G and P in, but other than that it
should be fine.

I thought about this some time ago wondering why anyone would build ones
complement machines, such as CDC did.  If they couldn't do a fast add that
would be a big disadvantage.   I then decided that CLA should work.

Now, it might be that there is a better way to do the problem you are asking
about, but that is a different question.

-- glen



Article: 58199
(removed)




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