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Messages from 58800

Article: 58800
Subject: Re: How to update LPM_ROM in ALTERA device quickly?
From: Andrew Paule <lsboogy@qwest.net>
Date: Fri, 01 Aug 2003 12:52:21 -0500
Links: << >>  << T >>  << A >>
It's possible, but difficult.  One of my old friends used to modify hex 
files (intel and Mot formats), and I've done SVF's and POF's, but you 
need to know the architecture of the chip far better than I do.

I'd either live with it, or get a faster computer - can you say SUN

Andrew

slamwu wrote:

>Hi all
>      I am running a project that has to use "embedded ROM" of ALTERA
>APEX20KE to execute code. With the aid of MegaWizard in Quartus, I 
>select LPM_ROM megafunction and specify an intel hex file for ROM 
>initialization. ROM is used as a black box in Synplify. Finally Quartus
>uses the netlist to place and route.
>      If I modify code in "embedded ROM", the whole project has to be
>complied again and it takes about 40 minutes. I wonder if anybody knows
>is it possible to "manually" modify SOF file or POF file without 
>compiling the whole project? Instead I know I can modify my APEX20KE 
>prototype by adding external rom. Hope that's not the final solution.
>
>                                                          Thanks a lot       
>
>  
>


Article: 58801
Subject: Re: 5 volt tolerant Xilinx parts
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Fri, 01 Aug 2003 11:02:28 -0700
Links: << >>  << T >>  << A >>
Rick,

Fair enough.  If it has to drive all the way to 5.0 V CMOS, then you have outlined
your constraints.

Too bad that they did not choose to be TTL compatible.

Austin

rickman wrote:

> Austin Lesea wrote:
> >
> > Rick,
> >
> > Any reason why you can not use the added series 100 ohm resistor method?  If
> > you select the drive levels/standards of the other devices, you may not even
> > need resistors at all.  In fact if they are 5V TTL drivers, then they will
> > not be able to souce current all the way to 5V, and no resistors are
> > required.
> >
> > That way you could also use Virtex II, or Spartan 3.
>
> This is for an PC/104 bus interface.  Some of the signals are bidir and
> even the rest have to be both directions since this board will support
> both master and slave operation.  Some signals are pullup up to 5 volts
> with 330 ohm resistors.  Will Virtex II drive that?  I am not willing to
> risk anything on the Spartan 3 working with a 5 volt bus.  They are
> currently not even 3.3 volt tolerant.
>
> > By the way, there is no max Icc standby in the ep1k30 data sheet.....just
> > typical.  Power on surge is not specified at all.  At least if we need a bit
> > of current on startup, we always specify it.
>
> If you call, Altera will give you power numbers.  Well, when I called
> they gave *me* numbers :)
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX


Article: 58802
Subject: Re: Size does matter
From: James Horn <jimhorn@svn.net>
Date: Fri, 01 Aug 2003 18:17:55 -0000
Links: << >>  << T >>  << A >>
Hi, Rob - how much core?  Would BGA packaging be OK?  Your PLCC and PQFP 
packages are around 30 mm squares.  You can get the XC2V3000 Virtex-II in 
a 676 pin PGA that's 27mm square - nearly 20% less board area.  At 3M 
gates / 14336 slices / 32256 logic cells / 1728 kbits of RAM / 96 
dedicated DSP multipliers and oodles more, I suspect it should be plenty 
for most applications especially for someone who hasn't pushed one of 
these puppies hard before (neither have I!).

I'm sure Altera (which I've used much more) can do as well for you too.  
Modern fine pitch BGAs are amazing packages!  And compared to the cost of 
designing the logic within it, your cost to a board house to mount it will 
be many dB below the noise level.

Best to you and your project -

Jim Horn (Just a happy user of both companies' parts)

Article: 58803
Subject: Re: Size does matter
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Fri, 01 Aug 2003 13:40:53 -0500
Links: << >>  << T >>  << A >>


Rob Judd wrote:

>Nicholas,
>
>No, manufacturability is the main concern. I don't have easy access to
>high volume production machinery, which is almost guaranteed to be
>necessary for most of the newer packages. If I can plug it in, great. If
>not, I need to be able to hand-solder it with a standard Weller iron.
>  
>
I'm hand soldering TQ144 and similar packages with .5 mm lead spacing by 
hand.
My procedure uses solder paste applied VERY sparingly with a ground down
hypodermic needle.  I think I'm using an 18 Ga needle now, and it is way too
large.  I lay a very thin bead of paste down along the pad rows.  I then 
position the
chip with curved-point tweezers and touch the soldering iron to one 
corner lead.
I then adjust position and solder the opposite corner lead.  if the 
alignment needs to
be touched up, I can "walk" the chip by reheating the corners 
alternately.  When alignment
is good, I then wipe the iron gently down the rows of pins, such that 
the iron tip is
touching the board lands and the end of the chip's pin.  This takes 
about a minute
per chip.  If you get the right amount of solder applied, bridges are 
rare.  If you
get them, very fine desoldering braid can be used to remove excess 
solder, then
the bridges will break by themselves.  Apply Iospropyl Alcohol (rubbing 
alcohol
works pretty well) or denatured alcohol to the chip, and brush with an old
toothbrush, then wash immediately with the spray hose on a kitchen sink, 
shooting
the water under the chip if possible.  (You want to get rid of the stray 
beads of
solder remaining between leads.)

Jon


Article: 58804
Subject: Re: How to use a TFT screen
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Fri, 01 Aug 2003 13:46:09 -0500
Links: << >>  << T >>  << A >>


Yves Deweerdt wrote:

> Hello all,
>
> I would like to reuse a 14 inch TFT screen of a IBM T21 laptop, this 
> LCD panel is a HT14X14-101.
> But I can't find any information about the pinout of the connector, or 
> what protocol I should use to drive this screen.
>
> Can anyone give me information on how to use this kind of screen?

Does the laptop still work?  Do you have a logic analyzer?  If so, you
can probe the signals and find out how the screen image is encoded
and serialized for the display.  Generally, the colors are all mixed
together (rgbrgbrgb) in a serial stream, but the stream may be sent
in blocks of 4 bits.  Often the top half and bottom half of the screen
is sent separately to the drivers above and below the board.
There are a couple of sync lines and a pixel clock.  there are also
several analog (contrast) and power lines, which may have voltages
generated in the controller board in the laptop.

Jon


Article: 58805
Subject: Re: DDS question. How to generate a square from a sine wave?
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 01 Aug 2003 12:02:14 -0700
Links: << >>  << T >>  << A >>


nospam wrote:
> So you take an 8 phase clock and run a DDS from each phase. 
Peter answers:
Not quite.
Here is a more detailed explanation I wrote in response to a similar question:
"I know I was too cryptic.
You understand normal DDS.
I create eight such registers and the inputs to these eight are:

N+A to the highest one, where N is the traditional input, and A is the
output of the top accumulator register.
So far it's traditional.

The remaining seven registers receive as inputs: N x 7/8 +A, Nx3/4+A,
Nx5/8+A etc. So they are not accumulators really only adders since they
all add to the same output value of the "main" accumulator. I really
need only their MSB registered bit, but flip-flops are free in FPGAs.)

Now I have eight outputs, all synchronous with the identical common clock,
but they will not go High all together. The ones with a small value of N
will lag behind.
I edge detect the eight outputs and use this signal to pick one of eight
clock phases, which I generated in two DCMs.
There are some pipelining issues, bu they are trivial.
I am in the process of breadboarding. Wish me luck.
The project is a 1 Hz to 1 GHz pulse generator with a 1-in-64000
resolution throughout the whole range. Using SerDes (MGT) outputs from
Virtex-IIPro."

Maybe this explains it better.
Peter Alfke

Article: 58806
Subject: Re: Size does matter
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 1 Aug 2003 19:29:55 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3F2A9152.CE7DFE2A@ob-wan.com>, Rob Judd  <judd@ob-wan.com> wrote:
>Nicholas,
>
>No, manufacturability is the main concern. I don't have easy access to
>high volume production machinery, which is almost guaranteed to be
>necessary for most of the newer packages. If I can plug it in, great. If
>not, I need to be able to hand-solder it with a standard Weller iron.

So you care about the ~1.27mm lead spacing as opposed to the .5mm spacing
you get on the PQFP style packages?

You might be in trouble then, Xilinx and Altera really don't seem to
like the old packaging except on older parts.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 58807
Subject: Re: reconfiguration VirtexE via JTAG (full or partial)
From: Chen Wei Tseng <chenwei.tseng@xilinx.com>
Date: Fri, 01 Aug 2003 13:42:07 -0600
Links: << >>  << T >>  << A >>
Sergey,

See response below.

1. iMPACT doesn't do this quite easily. You can use the debug bitstream
functionality and start shifting data in with the appropriate JTAG
instructions.

2. Yes, JPROG command does this.

3. XAPP290

Regards, Wei
Xilinx Applications

Serg_Y wrote:

> Hi
>
> I do not have expirience in Xilinx hardware and did not find (in DS,
> XAPP139, XAPP151) answer for the following questions:
>
> 1) does IMPACT (or other tool in ISE5) allow access to configuration
> registers (or issue JTAG comands like in figure 23 in XAPP151)? Is
> there any
> tool that allow to insert user comands in bitstream, or tool similar
> to
> IMPACT but more powerfull (compatible with Cable III)?
>
> 2) for full reconfiguration: Can one issue "shutdown sequence" (using
> JTAG)
> instead of reseting FPGA via PROGRAM pin? If "yes" what commands
> should be
> given to bitgen/impact or another tool? May be I made mistake in
> system
> design, but access to PROGRAM pin is dificult and I wish clear
> configuration
> memory (if posible) by JTAG comand.
>
> 3) partial reconfiguration (may be I'll need it late): Is there any
> "practical" example that explain how one should prepare and download
> "main"
> bitstream and "overlay" bitstream (suggesting that design rules for
> project
> are sutisfied)?
>
> I am sorry if the message was posted several times (i've tried several
> to post different ways).
>
> Thanks.
> Sergey.


Article: 58808
Subject: Re: reconfiguration VirtexE via JTAG (full or partial)
From: Chen Wei Tseng <chenwei.tseng@xilinx.com>
Date: Fri, 01 Aug 2003 13:57:15 -0600
Links: << >>  << T >>  << A >>
> 2. Yes, JPROG command does this.

Allow me to correct myself. JPROG is for V2 only. For VirtexE, you'll have
to toggle PROG.


Article: 58809
Subject: Re: DDS question. How to generate a square from a sine wave?
From: nospam <nospam@nospam.invalid>
Date: Fri, 01 Aug 2003 21:19:21 +0100
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote:

>Here is a more detailed explanation I wrote in response to a similar question:
 <snip>
>Maybe this explains it better.

Yep but I will have to think even more about this one to convince myself it
works :)


Article: 58810
Subject: Re: Size does matter
From: Rob Judd <judd@ob-wan.com>
Date: Sat, 02 Aug 2003 07:45:23 +1000
Links: << >>  << T >>  << A >>
Rick,

Yet another example of lack of imagination. Why can't these guys supply
such chips mounted on a small pluggable board?

Sheesh.

Rob


rickman wrote:
> 
> Rob Judd wrote:
> >
> > Hi,
> >
> > My application requires a lot of core but few physical i/o lines. Can
> > anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or
> > 80-pin pqfp package?
> >
> > Thanks,
> >
> > Rob
> 
> No, the best you will do is a VQFP100 or you will have to use a CPLD.
> The CPLDs come in some pretty small packages, but not a lot of density
> in them.
> 
> --
> 
> Rick "rickman" Collins
> 
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 58811
Subject: Re: Mentor Hyperlynx IBIS simulator (was Re: Spartan IIE max pin switching)
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 01 Aug 2003 14:48:20 -0700
Links: << >>  << T >>  << A >>
I asked:
> And what does a single-user license for Hyperlynx EXT cost?

Bassman59a@yahoo.com (Andy Peters) writes:
> Easily in four figures -- an order of magnitude more expense than
> Eagle.

I spent something like $1197 for Eagle, if memory serves.  So you're
saying that the Hyperlinx license costs in the *high* four figures?

> Of course, depending on your board's complexity (and what your
> engineering time is worth), that might be cheaper than a board spin.

Could well be.

Thanks,
Eric

Article: 58812
Subject: Re: How to update LPM_ROM in ALTERA device quickly?
From: "Subroto Datta" <sdatta@altera.com>
Date: Fri, 01 Aug 2003 22:21:24 GMT
Links: << >>  << T >>  << A >>
This is fairly easy. Compile the design once with smart recompile on. You
can turn this on from the Assign->Settings Menu. Choose
Compiler->Mode->Smart Compile button. From this point on if the mif is
modified, each time the design is compiled Quartus will only regenerate the
sof with the modified mif values.

- Subroto Datta
Altera Corp.

"slamwu" <slamwu@alumninet.nctu.edu.tw> wrote in message
news:bgdoal$1oqu$1@netnews.NCTU.edu.tw...
> Hi all
>       I am running a project that has to use "embedded ROM" of ALTERA
> APEX20KE to execute code. With the aid of MegaWizard in Quartus, I
> select LPM_ROM megafunction and specify an intel hex file for ROM
> initialization. ROM is used as a black box in Synplify. Finally Quartus
> uses the netlist to place and route.
>       If I modify code in "embedded ROM", the whole project has to be
> complied again and it takes about 40 minutes. I wonder if anybody knows
> is it possible to "manually" modify SOF file or POF file without
> compiling the whole project? Instead I know I can modify my APEX20KE
> prototype by adding external rom. Hope that's not the final solution.
>
>                                                           Thanks a lot
>



Article: 58813
(removed)


Article: 58814
Subject: Re: Speed Grade...
From: "Paul Leventis" <paul.leventis@utoronto.ca>
Date: Fri, 01 Aug 2003 22:33:34 GMT
Links: << >>  << T >>  << A >>
> Ten years ago, these numbers had some meaning (frequency or prop delay)
> but we all gave up on that. In most cases, a larger number means faster,
> but I would check that in the data sheet.

It depends on the manufacturer.  On Altera's FPGAs (at least, the recent
ones), a "-5" device is faster than a "-7" device.

Regards,

Paul Leventis
Altera Corp.



Article: 58815
Subject: Ground planes on 4-layer PCB
From: ":: Gabster ::" <gabsterblue@hotmail.com>
Date: Fri, 1 Aug 2003 19:03:46 -0400
Links: << >>  << T >>  << A >>
Hi,

    My FPGA PCB has 4 layers: ground, power and two signal layers. I'm
wondering if I should put a ground plane on the 2 signals layer. At first I
believe it wasn't required because of the ground layer then I thought about
EMI/RFI protection it could bring. What is the usual way to do it? If yes,
to what ground should I tie it: digital, analog or power?

thanks,
Gabriel



Article: 58816
Subject: Re: DDS question. How to generate a square from a sine wave?
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 01 Aug 2003 23:43:00 GMT
Links: << >>  << T >>  << A >>
Pardon me for using your post, Peter, I missed the original newsgroup post.
Comments at the end.

> Jacques athow wrote:
> >
> > I have a project that needs a 21.48MHZ clock input. But the problem is
> > that I dont have that type of oscillator. As the project is going to
> > be in an large FPGA , is it possible to generate using coregen and a
> > 40MHZ square source(the FPGA clock), a dds with adequate resolution
> > and that at a certain phase increment, would in turn generate the
> > 21.48MHZ needed but as a sinusoid.
> >
> > Now, in order to complete the design, the signal would remain in the
> > digital domain and pass through some clipping logic, which would give
> > a '1' when the sine value is greater than an arbritrary index. At the
> > output of this block, we would theoretically have a square wave. The
> > only inconvenience is that the generated square wave would be one that
> > doesn't possess a 50% duty cycle.
> >
> > Could we use the available DLL to reconstruct the clock, based from
> > the just created pseudo clock from the DDS?
> >
> > The tool used is coregen and we have a virtex 2 platform.
> > I would really appreciate some clues about this idea.
> >
> > Thanks.
> > Jac

How close do you need your 21.48MHz?  You could use the Virtex-II DCM to
produce a close frequency - 40MHz*29/27=42.96296MHz or twice 21.48148MHz.  A
simple divide by 2 gives you a pretty square wave that's only 69ppm off your
desired target frequency.  No DDS required.



Article: 58817
Subject: Re: Speed Grade...
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Fri, 01 Aug 2003 23:55:50 GMT
Links: << >>  << T >>  << A >>
Hi - 

Xilinx has done it both ways.  For families with a numerical
designation, e.g., 4000, a smaller number means a faster part.  For
families with names, e.g., Virtex or Spartan, a smaller number means a
slower part.  

This is reversed during months that have a "Y" in them.

Bob Perlman
Cambrian Design Works

On Fri, 01 Aug 2003 22:33:34 GMT, "Paul Leventis"
<paul.leventis@utoronto.ca> wrote:

>> Ten years ago, these numbers had some meaning (frequency or prop delay)
>> but we all gave up on that. In most cases, a larger number means faster,
>> but I would check that in the data sheet.
>
>It depends on the manufacturer.  On Altera's FPGAs (at least, the recent
>ones), a "-5" device is faster than a "-7" device.
>
>Regards,
>
>Paul Leventis
>Altera Corp.
>


Article: 58818
Subject: Re: PLL / DPLL phase question
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 01 Aug 2003 23:56:13 GMT
Links: << >>  << T >>  << A >>

"Jay" <se10110@yahoo.com> wrote in message
news:MPG.19944c08c648a2109896bb@news.surfcity.net...
<snip>
> Well, I cheated just a bit, I don't have a VCO, I have a motor control
> unit. I'm varying the voltage to the motor control unit to get a
> "frequency" out of it. My VCO "gain" is really the motor gain (RPM/Volt
> translated to Hz / volt).
</snip>

Rather than using an external phase comparator, could you sample the motor
signal to give you how "far" you are from your desired zero phase?  This
error magnitude would work to give a better frequency match.  If you know
how far off you are in phase, the integral of the frequency difference over
your period (1Hz to 50Hz) can be calculated to regain zero phase.  The motor
control slew rate will need to be part of the overall phase-locked-loop
design.

<snip>
> Using PWM would work for my application upto 11-12 bits(given a 40-60MHz
> input clock), but beyond that my PWM output frequency drops too low. I
> haven't solved this problem yet...dithering may work here.
</snip>

You could go to a sigma-delta style converter rather than a simple PWM.  I'm
not sure if someone has convenient reference code, but you can get extreme
precision in your control voltage as long as you filter out the high
frequency noise that the converter produces.  I've wanted to do something
with this approach using a single-package D-flipflop with nice analog rails
to give me a clean voltage (since FPGA outputs are affected by what else is
going on in the I/O or the core).

Given that the motor control may not react as quickly as one cycle, you may
not need high resolution and the PWM output may be fine.



Article: 58819
Subject: Re: PLL / DPLL phase question
From: Andrew Paule <lsboogy@qwest.net>
Date: Fri, 01 Aug 2003 20:02:16 -0500
Links: << >>  << T >>  << A >>
In pll's, you have either an m or an m and n divide registers.

Thad Smith wrote:

> Andrew Paule wrote:
>
>> Thad -
>>
>> sounds good in theory - but there has never been a 12 bit DAC with 12 
>> bits of reality - the LSB is junk with power supply noise and 
>> non-linearity.  The 12 bit DACs are really capable of 11 - 11.3 bits 
>> with GOOD (excellent) gound planes and linear regulators and a cold 
>> plate for temperature stability.
>
>
> For this application, the OP has error feedback, which removes the 
> need for long term stability, accuracy, and good linearity.  Noise 
> would be more of a problem, though.
>
>> The phase error means that his load into the m and n integer will not 
>> do well in this application - they only increment on cross.
>
>
> The m and n integer?  What do you mean here?
>
> Thad
>


Article: 58820
Subject: Re: PLL / DPLL phase question
From: Andrew Paule <lsboogy@qwest.net>
Date: Fri, 01 Aug 2003 20:10:15 -0500
Links: << >>  << T >>  << A >>
I think that you should just listen to Peter, and go straight digital 
out to either a DAC or some integration circuit - trying to model this 
as a PLL sounds easy, but you should just go straight digital

Andrew

John_H wrote:

>"Jay" <se10110@yahoo.com> wrote in message
>news:MPG.19944c08c648a2109896bb@news.surfcity.net...
><snip>
>  
>
>>Well, I cheated just a bit, I don't have a VCO, I have a motor control
>>unit. I'm varying the voltage to the motor control unit to get a
>>"frequency" out of it. My VCO "gain" is really the motor gain (RPM/Volt
>>translated to Hz / volt).
>>    
>>
></snip>
>
>Rather than using an external phase comparator, could you sample the motor
>signal to give you how "far" you are from your desired zero phase?  This
>error magnitude would work to give a better frequency match.  If you know
>how far off you are in phase, the integral of the frequency difference over
>your period (1Hz to 50Hz) can be calculated to regain zero phase.  The motor
>control slew rate will need to be part of the overall phase-locked-loop
>design.
>
><snip>
>  
>
>>Using PWM would work for my application upto 11-12 bits(given a 40-60MHz
>>input clock), but beyond that my PWM output frequency drops too low. I
>>haven't solved this problem yet...dithering may work here.
>>    
>>
></snip>
>
>You could go to a sigma-delta style converter rather than a simple PWM.  I'm
>not sure if someone has convenient reference code, but you can get extreme
>precision in your control voltage as long as you filter out the high
>frequency noise that the converter produces.  I've wanted to do something
>with this approach using a single-package D-flipflop with nice analog rails
>to give me a clean voltage (since FPGA outputs are affected by what else is
>going on in the I/O or the core).
>
>Given that the motor control may not react as quickly as one cycle, you may
>not need high resolution and the PWM output may be fine.
>
>
>  
>


Article: 58821
Subject: Re: DDS question. How to generate a square from a sine wave?
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 01 Aug 2003 18:24:32 -0700
Links: << >>  << T >>  << A >>
Neat idea. I suppose we all got blindsided and discussed much more
complicated solutions...
Peter Alfke
==========
John_H wrote:
> 
> 
> How close do you need your 21.48MHz?  You could use the Virtex-II DCM to
> produce a close frequency - 40MHz*29/27=42.96296MHz or twice 21.48148MHz.  A
> simple divide by 2 gives you a pretty square wave that's only 69ppm off your
> desired target frequency.  No DDS required.

Article: 58822
Subject: Re: PLL / DPLL phase question
From: Thad Smith <thad@ionsky.com>
Date: Fri, 01 Aug 2003 21:12:17 -0600
Links: << >>  << T >>  << A >>
Jay wrote:

> Well, I cheated just a bit, I don't have a VCO, I have a motor control 
> unit. I'm varying the voltage to the motor control unit to get a 
> "frequency" out of it. My VCO "gain" is really the motor gain (RPM/Volt 
> translated to Hz / volt).

That introduces some additional considerations.  A VCO would be fairly 
stable for a given control voltage.  Is this true of the motor?  If 
there are load variations, can the controller keep it within the narrow 
speed window to maintain your phase margin.  Even if the controller 
increases the drive to compensate for a load increase, it probably won't 
do anything to recover accumulated phase error.  If you absolutely need 
0.1 degree maximum phase error while the load changes, you might need a 
much stiffer motor drive, as well as immediate feedback from the motor 
to the controller, probably a high resolution rotary encoder.  If there 
is very little load change or your phase error limit can be exceeded at 
times, it won't be as bad.

Thad


Article: 58823
Subject: Re: 5 volt tolerant Xilinx parts
From: Spam Hater <spam_hater_7@email.com>
Date: Sat, 02 Aug 2003 03:22:51 GMT
Links: << >>  << T >>  << A >>
On Thu, 31 Jul 2003 21:27:46 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:

>I could have emailed this directly to Peter, but I thought it might be
>useful to others.  I have a socket on my board which requires 5 volt
>tolerance on a number of pins.  It also has to be reasonably low power
>meaning I can't power a high current surge on power up.  The part I
>currently have selected is the Altera EP1K30 which seems to do
>everything I need and should live with my 200 mA power on surge
>limitation.  But all the other parts on the board can be Xilinx.  So I
>would like to find a Xilinx alternative for this socket.  
>
>In the Xilinx camp I have considered a couple of devices which are 5
>volt tolerant.  
>
>Coolrunner - XCR3512XL - 3.3 volt, very low power, no RAM, current part. 
>SpartanXL - 3.3 volt, low power, distributed RAM only, old tools only. 
>Spartan2 - 2.5 volt, very high power, block RAM, current part.  
>
>Is this a correct summary?  Are there any parts that I have not listed
>that I should consider?  

Xilinx 95xx CPLDs.  Up to 512 macrocells, I believe.

>
>I have been given a very good price on the Coolrunner XCR3512XL, but
>even with 512 macrocells, including small FIFOs (8 bits x 16 words, two
>FIFOs) uses up half the chip.  
>
>The Spartan 2 is not an option due to the startup power.

The Spartan2 startup power is not all that bad.  Are you thinking of
the  Virtex?  That one has a nasty startup surge.

>
>If I am willing to work with the SpartanXL and I can get a good price on
>it, I could put that on the board.  I am not crazy about having to use
>older, not so well supported tools.  Having to use a different tool is
>the only real reason to not use the Altera part.  What tools are
>available exactly?  If I don't buy a third party VHDL synthesis tool, is
>there something equivalent to XST in the older "Classic" tools?  Are the
>"Classic" tools "paid for" only? 
>

Be warned.  The "entrance price" for a Spartan/SpartanXL synthesizer
is around $5K (US).  There.  Don't say I didn't warn you.

No, there are no other alternatives at this time.

Now, if Xilinx were to contact me off-line, I could help them with a
win-win solution for this.

>Any other chip family alternatives? 

Cypress?


Article: 58824
Subject: Re: Ground planes on 4-layer PCB
From: Spam Hater <spam_hater_7@email.com>
Date: Sat, 02 Aug 2003 03:25:28 GMT
Links: << >>  << T >>  << A >>
On Fri, 1 Aug 2003 19:03:46 -0400, ":: Gabster ::"
<gabsterblue@hotmail.com> wrote:

>Hi,
>
>    My FPGA PCB has 4 layers: ground, power and two signal layers. I'm
>wondering if I should put a ground plane on the 2 signals layer. At first I
>believe it wasn't required because of the ground layer then I thought about
>EMI/RFI protection it could bring. What is the usual way to do it? If yes,
>to what ground should I tie it: digital, analog or power?
>
>thanks,
>Gabriel
>

None of the above.

A plane (shield) for EMI/RFI should be tied to frame ground.

SH7





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