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Messages from 59100

Article: 59100
Subject: Re: Need help: getting 3.1i Coregen working on P4-system
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Fri, 08 Aug 2003 11:47:04 +0100
Links: << >>  << T >>  << A >>
On Thu, 07 Aug 2003 19:56:14 GMT, Bob_Myers@raytheon.com wrote:

>Hi;
>
>I've had to install 3.1i on a P4-based machine at work.  (Found the 
>instructions on
>replacing the default JRE image on the install disk --> worked great).
>
>However, I seem to be having a problem now with getting COREGEN to 
>work.  Seems that COREGEN is java-based, and runs with the JRE 
>distribution
>that is installed in the 3.1i structure. 
>
>Has anyone ever had to get COREGEN working on a P4-based machine?
>If so, what steps did you take to get it running?
>

Yes... (Why? my PC needed an emergency motherboard replacement with as
little disruption to the tool chain as possible)

Anyway  I found the answer on Xilinx website ... under "Chipscope"! It
wasn't mentioned at all under Coregen, but both require Java. The
problem is the version of JRE included with the 3.1 install, (1.1.7?)
which will not work with P4.

You need JRE 1.1.8 (or later) which is available for download from
Xilinx FTP site, if you have the correct login and password. When I
tried, I failed ... and asked Xilinx support ... apparently the FTP site
wouldn't let the support engineer in either! 

Fortunately the thing is also available from Sun 
http://java.sun.com/products/archive/
 - I don't know the full range of JRE versions that will work, so went
specifically for 1.1.8 which was buried under the obsolete/unsupported
stuff. Try
http://java.sun.com/products/archive/jdk/1.1.8_010/jre/index.html

Hope this helps,
- Brian



Article: 59101
Subject: Re: Spartan-IIE LVDS?
From: "dave garnett" <dave.garnett@metapurple.co.uk>
Date: Fri, 8 Aug 2003 11:58:56 +0100
Links: << >>  << T >>  << A >>
Read the bible - "High Speed Digital Design", by Johnson and Graham !

Dave

"Eric" <eric_usenet@yahoo.com> wrote in message news:bfab5081.0308072211.3143ae8f@posting.google.com...
> > Eric wrote:
> > >
> > > Hello! I'm trying to move 125 MB/sec bidirectionally off a daughter
> > > card, for a total of 250 MB/sec. I worry that even if I double the 8
> > > bit bus in each direction to 16-bits (32 data pins todal) I'll still
> > > be pushing a single-ended signal across a connector at 62.5 MHz. I
> > > can't go wider because I run out of pins on my QFP.
> > >
> > > I've started looking at LVDS, but it seems that xilinx has very little
> > > information on how to actually _use_ lvds in a project. National has
> > > some great app notes, but they're largely targeted at the national
> > > family of SERDES products. Can anyone offer any suggestions for
> > > high-speed multi-board data transfer between FPGAs? Has anyone ever
> > > tried building a SerDes in a spartan-IIE, and if so, what kinds of
> > > speeds have you been able to get?
> > >
> > > Thanks for the help!
> > >                  ...Eric
> Peter Alfke <peter@xilinx.com> wrote in message news:<3F32788A.4DDCA931@xilinx.com>...
> > Eric, what makes you think that 62 MHz I/O transfer is a problem?
> > You can easily go twice as fast...
> >
> > Peter Alfke, Xilinx
> > =========================
>
>
> I'm too poor to buy an IBIS simulator :) I've been reading all sorts
> of data sheets and app notes on LVDS that have made me worry about any
> sort of single-ended signals  one can reliably send over a short bus.
> I read that PCI has really tight timings and is evidently really hard
> to design for; it's only 33 MHz. Sure, it's a bus with multiple cards,
> but AGP is a single card in a single slot, and only runs at 66 MHz. I
> feared that if "real" EEs (instead of us biologists that just play
> them when we need equiment that doesn't exist) don't want to push a
> card interconnect above 66 Mhz, there must be a good reason.
>
> So I'm trying to figure out what I can reasonably expect from a
> 4-layer FR4 board and a 68-pin high-density mini-D connector. This is
> my first high-speed interconnect project, and it may just be paranoia.
> Are you suggesting I shouldn't lose too much sleep over a  ~125 MHz
> single-ended bus covering a distance of 6" or so? or should I stick to
> differential signaling for those types of speeds? I'd love to just
> make my bus wider, but I run out of IOs on my Spartan-IIE PQFP and I
> can't afford to have someone put down a BGA on a PCB.
>
> Ahh, the joys of low-cost student design ! :)
>
> Thanks again for all the help,
>                ...Eric



Article: 59102
Subject: Re: Compilation error
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Fri, 8 Aug 2003 12:19:26 +0100
Links: << >>  << T >>  << A >>

"YesMann" <waydak@hotmail.com> wrote in message
news:3f337f73@news.swissonline.ch...

[...]
> 3.   case cycle is
[...]
> 7.      WHEN  "000011" to "011101" => REG <= "000000";
[...]

> The  line 7 and 11 are considered as error : " Range must be a scalar
type".
> What can I specified the range  "000011" to "011101" in VHDL language ?

You can't.  However, you are using these values rather like numbers,
so it may be easier to convert them to integers for use in the case
statement:

  case to_integer(cycle) is
    ...
    when 3 to 29 => REG <= "000000";
    ...

Of course, the precise form of "to_integer" depends on what
numeric packages you are using, and the data type of "cycle".
If "cycle" is the output of a counter, and you have been
sensible and used ieee.numeric_std, and cycle is of type
UNSIGNED, then to_integer() is correct.



Article: 59103
Subject: Re: clock management on SPARTAN2
From: "Manfred Kraus" <news@cesys.com>
Date: Fri, 8 Aug 2003 13:22:00 +0200
Links: << >>  << T >>  << A >>
Every signal, that is used in a " if rising_edge " (also falling edge)
statement will be treated as if it was a clock signal. This means it gets a
clock buffer by default. To avoid this, use IBUFs  for the signals, you dont
want to have BUFGs.
.
.
component IBUF
port(I: in STD_LOGIC; O: out STD_LOGIC);
end component;

begin

-- force the usage of IBUF for Rd and Wr signals
-- Without the IBUF, XST uses an BUFGP by default.

U1: IBUF port map (I => Rd_in, O => Rd);
U2: IBUF port map (I => Wr_in, O => Wr);
.
.
.

Hint: You can replace the generic "IBUF" by a variant that meets your I/O
Standard.


-Manfred Kraus

-mkraus
-at
-cesys
-dot
-com





Article: 59104
Subject: Virtex-E power trace
From: stefanti@gmx.at (Stefan Tillich)
Date: 8 Aug 2003 04:42:43 -0700
Links: << >>  << T >>  << A >>
Hello,

We are currently trying to measure the power consumption of a Xilinx
Virtex-E FPGA on a custom-made circuit-board.

The FPGA is configured with a design which performs AES operations.
Power consumption is measured with a sensor resistor between the
FPGA's ground and the board's ground.

The trace shows activity of the AES design very clearly but when there
is no operation performed, then there is almost no transient current
flow.

In our opinion, at least some activity due to the loading of the clock
tree should be visible.

I'm using Xilinx ISE 5 WebPack for synthesis. Is it possible, that the
synthesizer generates some kind of power management for the design
(e.g. clock gating) so that there is nearly no power consumption, when
the design is not active? And if it does, is it possible to turn that
optimization behaviour off?

Best regards
Stefan Tillich

Article: 59105
Subject: Re: Confusing Xilinx Webpack warning
From: "Robert Finch" <robfinch@sympatico.ca>
Date: Fri, 8 Aug 2003 08:00:16 -0400
Links: << >>  << T >>  << A >>
"Prasanth Kumar" <lunix@comcast.net> wrote in message
news:N6mYa.85907$YN5.63517@sccrnsc01...
> When I synthesize the following test code in Webpack 5.1
> I get the following warnings. Am I misunderstanding
> something here? Note that the code below is a silly example
> as I tried to simplify my actual code to understand the
> warning by removing parts that don't cause the error.
>
> WARNING:Xst:646 - Signal <e> is assigned but never used.
> WARNING:Xst:646 - Signal <f> is assigned but never used.
> WARNING:Xst:646 - Signal <g> is assigned but never used.
> WARNING:Xst:646 - Signal <h> is assigned but never used.
>
> module test(a,b,c,d);
> input  [1:0] a, b;
> output       c, d;
>
> reg          c, d;
> reg          e, f, g, h;
>
> always@ (a or b)
> begin
>  e = a[1];
>  f = a[0];
>  g = b[1];
>  h = b[0];
>
>  c = e ^ g;
>  d = f ^ h;
> end
>
> endmodule
>

This kind of warning can happen if 'c' and 'd' turn out not to be used
(perhaps due to logic trimming by the synthesizer). If 'c' and 'd' get
trimmed then to the synthesizer it looks like 'e','f','g' and 'h' aren't
being used and it spits out that warning. Check the logic that 'c' and 'd'
drive to see if there's some way those signals might be trimmed.

Rob






Article: 59106
Subject: Re: Compilation error
From: "YesMann" <waydak@hotmail.com>
Date: Fri, 8 Aug 2003 14:51:40 +0200
Links: << >>  << T >>  << A >>


>   case to_integer(cycle) is
>     ...
>     when 3 to 29 => REG <= "000000";
>     ...
>
> Of course, the precise form of "to_integer" depends on what
> numeric packages you are using, and the data type of "cycle".
> If "cycle" is the output of a counter, and you have been
> sensible and used ieee.numeric_std, and cycle is of type
> UNSIGNED, then to_integer() is correct.
_______________________________

Thanks you for your response;
But if I process as your description, I have another message error:
"Type error in range expression";
What happened?

Thanks in advance





Article: 59107
Subject: Re: Compilation error
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Fri, 8 Aug 2003 14:17:18 +0100
Links: << >>  << T >>  << A >>
"YesMann" <waydak@hotmail.com> wrote in message
news:3f339ca9@news.swissonline.ch...
>
> >   case to_integer(cycle) is
> >     ...
> >     when 3 to 29 => REG <= "000000";
> >     ...
> >
> Thanks you for your response;
> But if I process as your description, I have another message error:
> "Type error in range expression";
> What happened?

Did you leave some of the "when" selectors as bit-strings?
If the case statement is testing an integer expression
such as to_integer(cycle), then all the selectors must be
of integer or integer range type.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 59108
Subject: Re: Size does matter
From: Rob Judd <judd@ob-wan.com>
Date: Fri, 08 Aug 2003 23:51:53 +1000
Links: << >>  << T >>  << A >>
Jay wrote:
> 
> Rob,
> 
> In article <3F2E0028.A07801D3@ob-wan.com>, judd@ob-wan.com says...
> > Add to that the need for an expensive IAR compiler for the AVR core and
> > it's pretty average. It's difficult to do a meaningful feature
> > comparison though, owing to the different architectures. I do know that
> > the EP1C6 and APA150 are very similar in price (when the config chip is
> > added into the equation). May check out the Atmel too, just to be sure
> > I'm not missing out on any bargains.
> 
> You have alternatives besides IAR.
> 
> The CodeVision compiler from http://www.hpinfotech.ro/ looks good, I
> have associates who used it and didn't have anything unpleasant to say.
> There is a version of the compiler that also supports the FPSLIC too. It
> supports a number of optimizations and also includes pragmas so you can
> optimize for speed or size.
> 
> There is also ImageCraft (www.imagecraft.com). I test drove the 30-day
> eval and found it had functionality, but wasn't laid out (in my opinion)
> as well as the above. Code produced looked OK I found CodeVision was
> better in some instances, but I didn't spend too much time trying to
> optimize for my test runs.
> 
> There is also AVR-GCC if you feel like dealing with GNU stuff...I have
> *major* problems with this toolchain since(among other issues) it does
> not support "dead code" removal which should rip out any pieces of
> compiled code that aren't referenced in your program. I have a small set
> of C routines that I use in many of my projects but often not all
> functions in the "common set" C file are used. GCC won't remove those
> (even if you mess around with the linker scripts).
> 
> Also, there aren't any pragmas for optimization (just your standard -o1
> -o2 -o3 switches) which means you have to segment code into seperate
> files to get it optimized the way you want (very sub-optimal).
> 
> GCC just wasn't meant for 8-bit micros, and I found plenty of fault with
> the code it generates too.
> 
> Anyway, you have some alternatives.

GCC? Bwahahaha. If only you knew my opinion of that crud.

I hadn't heard of Codevision, thanks for the tip.

Rob

Article: 59109
Subject: Re: Upgrading OS or WebPack
From: Rob Judd <judd@ob-wan.com>
Date: Fri, 08 Aug 2003 23:58:39 +1000
Links: << >>  << T >>  << A >>
Aart van Beuzekom wrote:
> 
> Hei,
> 
> I will start developing FPGA applications with WebPack. My problem is
> that my OS is WinNT, which is not supported by WebPack 5.2i. I've got a
> CD laying round here with WebPack version 4.2WP0.0.
> 
> Can anybody tell me if the advantages of v. 5.2i are so much that
> upgrading to Win2000 really is necessary?
> 
> My application will run on a Spartan-II device. Clock speed wil not be
> an issue, but efficient use of logic cells might be.

I can tell you why I upgraded from NT to W2K ... no support for USB.

Rob

Article: 59110
Subject: Re: Virtex-E power trace
From: Andrew Paule <lsboogy@qwest.net>
Date: Fri, 08 Aug 2003 09:45:02 -0500
Links: << >>  << T >>  << A >>
how many dB is you circuit capable of?

Maybe Peter (Alfke) will know how much current a minimal clock tree will 
take, but I would guess not much - these things are designed for LOW 
current operation.

Andrew

Stefan Tillich wrote:

>Hello,
>
>We are currently trying to measure the power consumption of a Xilinx
>Virtex-E FPGA on a custom-made circuit-board.
>
>The FPGA is configured with a design which performs AES operations.
>Power consumption is measured with a sensor resistor between the
>FPGA's ground and the board's ground.
>
>The trace shows activity of the AES design very clearly but when there
>is no operation performed, then there is almost no transient current
>flow.
>
>In our opinion, at least some activity due to the loading of the clock
>tree should be visible.
>
>I'm using Xilinx ISE 5 WebPack for synthesis. Is it possible, that the
>synthesizer generates some kind of power management for the design
>(e.g. clock gating) so that there is nearly no power consumption, when
>the design is not active? And if it does, is it possible to turn that
>optimization behaviour off?
>
>Best regards
>Stefan Tillich
>  
>


Article: 59111
Subject: Re: Spartan-IIE LVDS?
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Fri, 08 Aug 2003 14:48:33 GMT
Links: << >>  << T >>  << A >>
[snip]

> I read that PCI has really tight timings and is evidently really hard
> to design for; it's only 33 MHz. Sure, it's a bus with multiple cards,
> but AGP is a single card in a single slot, and only runs at 66 MHz. I
> feared that if "real" EEs (instead of us biologists that just play
> them when we need equiment that doesn't exist) don't want to push a
> card interconnect above 66 Mhz, there must be a good reason.

[snip]

The hard part in "33 MHz" PCI is a 7 ns path on the PCI IRDY# and TRDY#
control signals to output enables on the FPGA.  So, instead of a "33 MHz"
problem, you really have a 143 MHz" design challenge.  The issue is related
to propagation time within the FPGA and not related to signal integrity
issues.

BTW, Spartan-IIE fully supports 66 MHz and 64-bit PCI and is available in a
proven LogiCORE solution.
http://www.xilinx.com/partinfo/pci/xcvpci64_32ds.pdf

--------------------------------
Steven K. Knapp
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC



Article: 59112
Subject: Re: Block ram simulation
From: "Ian Poole" <ianpoole@wiltshiretaekwondo.com>
Date: Fri, 8 Aug 2003 16:12:20 +0100
Links: << >>  << T >>  << A >>
The gate level model includes the gsr signal. Add the gsr signal (inside the
dut) to your waveform! This is asserted for the first 100 ns of simulation
and prevents the BRAMS from operating, hence the first writes you do don't
work.

If you delay your stimulus by, say 150ns, everything will work.

BTW, I would strongly recommend using the following style for your stimulus
generation
process
begin
  read_addr  <= ...
  write_addr <= ...
  write_data <=  ...
  write_en    <= ...
  wait for 7 ns;

  --do something
  wait for 100 ns;

  --do something else
  wait for 100 ns;

  --do something else
  wait for 100 ns;

  --do something else
  wait for 100 ns;
  wait;
end process;

rather than trying to list your stimulii:
read_addr <= "100000000", "000100001" after 107 ns, "001000010" after 207
ns, "000000000" after 307 ns, "000000001" after 407 ns, "000000010" after
507 ns;

which is almost impossible to maintain, read, edit etc!

Ian


"Bo Esbech" <none@none.com> wrote in message
news:bgqjb8$621$1@news.net.uni-c.dk...
> The only difference between "your" code and the one posted is the read
> scheme. Yours is "write firste" where as the posted is "read firste". The
> testbench never writes to and reads from the same address in the same
clock
> cycle, so the read scheme can't explain why the last read value is
> incorrect. I have tried using your code and it has exactly the same
problem.
>
> A screenshot of the wave forms for behavioural and post-translate
simulation
> can be found at.
>
> http://www.student.dtu.dk/~s001467/simulation.jpg
>
>
> Bo Esbech
>
>
> "Mike Treseler" <mike.treseler@flukenetworks.com> skrev i en meddelelse
> news:3F3007B1.6060002@flukenetworks.com...
> > Christian Obel wrote:
> > > I am doing a project for a Virtex2 fpga with the Free ISE WebPACK 5.2i
> with
> > > all the latest patches. I am writing a piece of behavioral VHDL that
> will
> > > synthesize as dual ported block ram and a testbench to verify its
> behavior
> > > by writing three values to it and then read them back. This works all
> fine
> > > in a behavioral simulation, but when I advance to a post-translate or
> > > post-place & route simulation the last of the three values read ( the
> first
> > > written) is wrong. Can someone tell me what is wrong? Maybe it is
never
> > > written?
> >
> > Maybe you need to register the address.
> > http://groups.google.com/groups?q=sync_ram+entity+lpm_ram_dq
> >
> >   -- Mike Treseler
> >
>
>



Article: 59113
Subject: Re: Block ram simulation
From: "Bo Esbech" <none@none.com>
Date: Fri, 8 Aug 2003 17:42:44 +0200
Links: << >>  << T >>  << A >>
You are absolutely right. With a 100 ns delay before operating the Block Ram
the problem is gone. It is natural with some initialization time for the
Block Ram, but I don't understand way this isn't stated _very_ clearly in
the Virtex II User Manual or way the synthesis tool does not issue a warning
then i dicides to use block ram since the resulting hardware does not
comform fully with the VHDL specification. But that is another discussion.

Thanks a lot for your quick response.

Regards
Bo Esbech


"Ian Poole" <ianpoole@wiltshiretaekwondo.com> skrev i en meddelelse
news:bh0eos$8al$1$8300dec7@news.demon.co.uk...
> The gate level model includes the gsr signal. Add the gsr signal (inside
the
> dut) to your waveform! This is asserted for the first 100 ns of simulation
> and prevents the BRAMS from operating, hence the first writes you do don't
> work.
>
> If you delay your stimulus by, say 150ns, everything will work.
>
> BTW, I would strongly recommend using the following style for your
stimulus
> generation
> process
> begin
>   read_addr  <= ...
>   write_addr <= ...
>   write_data <=  ...
>   write_en    <= ...
>   wait for 7 ns;
>
>   --do something
>   wait for 100 ns;
>
>   --do something else
>   wait for 100 ns;
>
>   --do something else
>   wait for 100 ns;
>
>   --do something else
>   wait for 100 ns;
>   wait;
> end process;
>
> rather than trying to list your stimulii:
> read_addr <= "100000000", "000100001" after 107 ns, "001000010" after 207
> ns, "000000000" after 307 ns, "000000001" after 407 ns, "000000010" after
> 507 ns;
>
> which is almost impossible to maintain, read, edit etc!
>
> Ian
>
>
> "Bo Esbech" <none@none.com> wrote in message
> news:bgqjb8$621$1@news.net.uni-c.dk...
> > The only difference between "your" code and the one posted is the read
> > scheme. Yours is "write firste" where as the posted is "read firste".
The
> > testbench never writes to and reads from the same address in the same
> clock
> > cycle, so the read scheme can't explain why the last read value is
> > incorrect. I have tried using your code and it has exactly the same
> problem.
> >
> > A screenshot of the wave forms for behavioural and post-translate
> simulation
> > can be found at.
> >
> > http://www.student.dtu.dk/~s001467/simulation.jpg
> >
> >
> > Bo Esbech
> >
> >
> > "Mike Treseler" <mike.treseler@flukenetworks.com> skrev i en meddelelse
> > news:3F3007B1.6060002@flukenetworks.com...
> > > Christian Obel wrote:
> > > > I am doing a project for a Virtex2 fpga with the Free ISE WebPACK
5.2i
> > with
> > > > all the latest patches. I am writing a piece of behavioral VHDL that
> > will
> > > > synthesize as dual ported block ram and a testbench to verify its
> > behavior
> > > > by writing three values to it and then read them back. This works
all
> > fine
> > > > in a behavioral simulation, but when I advance to a post-translate
or
> > > > post-place & route simulation the last of the three values read (
the
> > first
> > > > written) is wrong. Can someone tell me what is wrong? Maybe it is
> never
> > > > written?
> > >
> > > Maybe you need to register the address.
> > > http://groups.google.com/groups?q=sync_ram+entity+lpm_ram_dq
> > >
> > >   -- Mike Treseler
> > >
> >
> >
>
>



Article: 59114
Subject: Re: Virtex-E power trace
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 08 Aug 2003 09:29:13 -0700
Links: << >>  << T >>  << A >>
I am sure the answer to your first question is: No.
But to convince yourself, just implement a toggling flip-flop, clocked
like everything else, and bring the Q out on a spare pin...
Peter Alfke

Stefan Tillich wrote:
> 
> Hello,
> 
> We are currently trying to measure the power consumption of a Xilinx
> Virtex-E FPGA on a custom-made circuit-board.
> 
> The FPGA is configured with a design which performs AES operations.
> Power consumption is measured with a sensor resistor between the
> FPGA's ground and the board's ground.
> 
> The trace shows activity of the AES design very clearly but when there
> is no operation performed, then there is almost no transient current
> flow.
> 
> In our opinion, at least some activity due to the loading of the clock
> tree should be visible.
> 
> I'm using Xilinx ISE 5 WebPack for synthesis. Is it possible, that the
> synthesizer generates some kind of power management for the design
> (e.g. clock gating) so that there is nearly no power consumption, when
> the design is not active? And if it does, is it possible to turn that
> optimization behaviour off?
> 
> Best regards
> Stefan Tillich

Article: 59115
(removed)


Article: 59116
Subject: Re: Clocking in a virtex 2 without using the clock trees : questions
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 08 Aug 2003 10:03:01 -0700
Links: << >>  << T >>  << A >>
A clock that drives 40 flip-flops should be distributed on a global
clock. Then you do not have to worry about the myriad aspects of clock
skew. Instead you have a delay, but that is a single parameter, and is
much easier to deal with.

Peter Alfke, Xilinx
=========
jean-francois hasson wrote:
> 
> Hi,
> 
> I have a serial bus coming in a Virtex II -5 in LVDS format at 80 MHZ
> with 3 data in parallel. The data change on the falling edge of the
> clock. The problem is that the clock is present only when data is
> transmitted (no DCM possible) and the pads used for the clock does not
> allow the use of a bufgp without an important routing delay. I am
> using the MAXSKEW constraint on the received clock and the best I can
> get is 450 ps (I can not use the local clock resources described in
> xapp609). This clock goes to approximately 40 FFs. I have, on this
> clock domain, among other things, a shift register so I have a FF to
> FF path. When having the min skew of 450 ps parts of the shift
> register are implemented in the same CLB so the output of a FF goes
> through the local routing matrix of the CLB and back to the input of a
> FF in the same CLB : I believe it must be the shortest and quickest
> path to go from one FF to another. My problem is that I wonder if the
> skew I have will always be smaller than the clock_to_out + prop_delay
> : I believe the max values are ok but what about typical ?
> 
> Thank you.
> 
> J.F. Hasson

Article: 59117
Subject: Re: Upgrading OS or WebPack
From: "Josep Duran" <j.duran@nospamteleline.es>
Date: Fri, 8 Aug 2003 19:48:45 +0200
Links: << >>  << T >>  << A >>
I am using Webpack 4.2 from time to time. (Windows 98)
I have done a few projects targeting 9536XL and Spartan-II XC2S200.

I am no expert, but I think 4.2 is quite usable.
Don't know about 5.2, some day I may upgrade my computer to XP.


Regards






Article: 59118
Subject: Virtex-II RocketIO: Serial ATA?
From: "Paul Gentieu" <paul.gentieu@finisar.com>
Date: Fri, 8 Aug 2003 11:16:47 -0700
Links: << >>  << T >>  << A >>
The Xilinx web page describing the RocketIO serdes mentions in 
passing that it can support Serial ATA. But I don't see any support 
for out-of-band signaling, and the serdes voltage swing and common-mode 
levels don't seem compatible either.  

So, it seems that significant 
external circuitry would be required, and it would be kludgy. Is there 
an appnote for doing this? Dedicated SATA Phy chips seem pretty hard to 
find.  

Of course, a real SATA-compatible transceiver in the next 
generation of the FPGA would be preferable... 

-Paul

Article: 59119
Subject: reconfiguration time
From: john.campbell@ngc.com (John Campbell)
Date: 8 Aug 2003 12:10:32 -0700
Links: << >>  << T >>  << A >>
Whats the fastest reconfiguration time I could expect from an xc2v2000?
-jc

Article: 59120
Subject: speeding up quartus
From: dshesnicky@yahoo.com (Don S)
Date: 8 Aug 2003 12:17:33 -0700
Links: << >>  << T >>  << A >>
I'm a sysadmin looking at a problem that a designer is having with
slow turn around times in Altera Quartus. The turn around time on a 
compile is about 1 hr on a AMD 1700+ with 1 gig of memory. Quartus 
version is 2.1 running on Win2K SP2.

The bulk of the time is spent in Logic Synthesis and the Fitter.
If we just bring up the task manager it shows that we have not tapped
the memory but the cpu is pegged.

There is apparently a way to lock down the layout of certain blocks
and/or do an incremental compile so that everything would not have to 
be re-synthesised but the designer says that it doesn't seem to work 
correctly. 

Any pointers would be greatly appreciated.

Don

Article: 59121
Subject: Synopsys search path
From: "cfk" <cfk_alter_ego@pacbell.net>
Date: Fri, 08 Aug 2003 20:39:59 GMT
Links: << >>  << T >>  << A >>
I have a new Synopsys installation that I am trying to get to synthesize
with Virtex2. I seem to have the default libraries in tcl syntax and a
script that I need to work with in non-tcl, so my issue is a tcl versus
Synopsys fpga_shell understanding. Here is my first question:

    Why would fpga_shell have trouble with the statement "set
dcfpga_xil_lib_path "/usr/synopsys/dcfpga/libraries/2003.06"

I'm getting nowhere with Synopsys (that story begins with "its not our
problem to install the software you bought from us" and ends with "here are
the latest and greatest scripts [that dont work]), so as Pricess Leia once
said "Help me Obe Wan Kenobe, youre my only hope?"

--
Charles Krinke
http://home.pacbell.net/cfk
cfk@pacbell.net



Article: 59122
(removed)


Article: 59123
Subject: Re: reconfiguration time
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 08 Aug 2003 14:28:28 -0700
Links: << >>  << T >>  << A >>
The XC2V2000 needs 6.8 million configuration bits. If you are in a
hurry, you will feed it with 8 bits in parallel @ 50 MHz, which is 400
Mbps. So it takes 17 milliseconds.
You may be able to push the 50 MHz up a bit, but not much.

Peter Alfke, Xilinx Applications
==============================
John Campbell wrote:
> 
> Whats the fastest reconfiguration time I could expect from an xc2v2000?
> -jc

Article: 59124
Subject: Re: Excalibur - lpm_syncram
From: sdatta@altera.com (Subroto Datta)
Date: 8 Aug 2003 14:34:18 -0700
Links: << >>  << T >>  << A >>
"Andrea" <aa@bb.cc> wrote in message news:<bgtt17$c8m$1@lacerta.tiscalinet.it>...
> Hi all,
> 
> I am developing a design using excalibur device (ExcaliburArm family -
> EPXA10F1020C3).
> I read on apex manual that ESB supports clock enable, but when I tried to
> instantiate an ALT_SYNCRAM with input clock enable (using MegaWizard Plug_in
> Manager) the elaboration prosess gives me this error:
> "Assertion error: Can't implement single port RAM for EXCALIBUR_ARM device
> family from altsyncram megafunction because clock enable ports are not
> supported in altram megafunction"
> 
> What's wrong?
> 
> Thanks in advance!!!
> 
> Andrea

Hi Andrea,

The clock enable is not supported by the single-port RAM megafunction.
 An easy work-around is to use the dual-port megafunction (via the
MegaWizard "memory compiler/RAM: 2-port" or the older
"storage/lpm_ram_dp+").  You can always tie the rdaddress and
wraddress together to get single-port RM behavior.

- Subroto Datta
Altera Corp.



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