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Messages from 59050

Article: 59050
Subject: Xilinx ISE WebPack 5.2 & VHDL : wait synthesis
From: max <m.cialdi_NO_SP@M_oksys.it>
Date: Thu, 7 Aug 2003 03:44:06 -0700
Links: << >>  << T >>  << A >>
I tried this source code: 

entity main is 
    Port ( clk , en : in std_logic; 
           sout : out std_logic); 
end main; 

architecture Behavioral of main is 
begin 
  process 
  variable a : std_logic; 
  begin 
    sout <= '0'; 
    a := '0'; 
    wait until rising_edge(en); 
    while en = '1' loop 
-- wait until rising_edge(clk); 
      wait until clk'event and clk = '1'; 
      a := not a; 
      sout <= a; 
    end loop; 
  end process; 

end Behavioral; 

and I obtain this error: 

Analyzing Entity <main> (Architecture <behavioral>). 
ERROR:Xst:825 - C:/Lavori/menfis/prova_xilinx/prova_2/main.vhd line xx: Wait statement in a procedure is not accepted. 

The question is: can I use wait or not? 
I found a lot of manual on the internet (eg. http://mikro.e-technik.uni-ulm.de/vhdl/anl-engl.syn/html/node8.html), and all of them sais that 'wait' is allowed in synthesis. 

thanks 



Article: 59051
Subject: Error Generate Statement
From: fpga_uk@yahoo.co.uk (Isaac)
Date: 7 Aug 2003 03:44:30 -0700
Links: << >>  << T >>  << A >>
Hi Fellows, 

I am just getting used to generate statement. Do begin with 8 bit
inverter is generated using Generate Command. Now I want to connect
the out put of one inverter to the input of other invertor or you can
say to cascade the 8 inverters. I will just apply input to the first
inverter and at every clock pulse output is tranfered sequentially to
other inverter.
I have written the VHDL code below But I am getting following error.
Help would be appreciated .


ERROR ---------------------------------------------------------------------
# Error: ELAB1_0008: generate.vhd : (31, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (32, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (33, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (34, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (35, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (36, 16): Cannot read output :
"Outputs".
# Error: ELAB1_0008: generate.vhd : (37, 16): Cannot read output :
"Outputs".

VHDL CODE ---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all; 	

entity Invert_8 is 
	port ( Inputs :std_logic_vector (1 to 8);
	clock : in std_logic ;
	Outputs : out std_logic_vector (1 to 8));
end Invert_8;

Architecture Behaviour of Invert_8 is 
component Inverter
	port ( I1 : std_logic ; 
	clock : in std_logic;
	O1 : out std_logic );
end component	;
signal	output1  : std_logic ;	
signal	output2  : std_logic ;
signal	output3  : std_logic ;
signal	output4  : std_logic ;
signal	output5  : std_logic ;
signal	output6  : std_logic ;
signal	output7  : std_logic ;
begin 
	
	InverterGenerated : for I in 1 to 8 generate 
		Inv : Inverter port map (Inputs(I),clock, Outputs(I));
	end generate ; 	

	process	 (clock)
		begin 
			if 	(clock'EVENT and clock ='1') then	
				output1 <= Outputs(1); 
				output2 <= Outputs(2);
				output3 <= Outputs(3);
				output4 <= Outputs(4);
				output5 <= Outputs(5);
				output6 <= Outputs(6);
				output7 <= Outputs(7); 
			end if ;
		end process	;
	InverterGenerated_1 : Inverter
	port map (
				Inputs(1),clock, Outputs(1)
			  );   
	InverterGenerated_2 : Inverter
	port map (
	I1 => output1,
	clock => clock, O1 => Outputs(2)
	);
	InverterGenerated_3 : Inverter
	port map (
	I1 => output2,
	clock => clock, O1 => Outputs(3)
	);
	InverterGenerated_4 : Inverter
	port map (
	I1 => output3,
	clock => clock, O1 => Outputs(4)
	);
	InverterGenerated_5 : Inverter
	port map (
	I1 => output4,
	clock => clock, O1 => Outputs(5)
	);			  
	InverterGenerated_6 : Inverter
	port map (
	I1 => output5,
	clock => clock, O1 => Outputs(6)
	);					  
	InverterGenerated_7 : Inverter
	port map (
	I1 => output6,
	clock => clock, O1 => Outputs(7)
	);
	InverterGenerated_8 : Inverter
	port map (
	I1 => output7,
	clock => clock, O1 => Outputs(8)
	);
 end Behaviour;
--
 library IEEE;
use IEEE.STD_LOGIC_1164.all; 	
 entity	Inverter is 
port ( I1 : std_logic ;
		clock : in std_logic;
		O1 : out std_logic  );
end Inverter;
Architecture Behav of Inverter is 

begin 
	process	(I1,clock)
	begin 
		if (clock'EVENT and clock='1') then 
			O1 <= not (I1);
		end if;
	end process	;
end Behav;

Article: 59052
Subject: Re: Offshore engineering
From: "Simon Peacock" <nowhere@to.be.found>
Date: Thu, 7 Aug 2003 22:52:33 +1200
Links: << >>  << T >>  << A >>
I think you'll find that this is a common problem.  In NZ we see companies
leaving all the time.
and places like India and China will always be cheaper.  but the likelihood
of them pirating your project is high too.. if they will steal 10k or 100k
of software think what they will do if your project proves worth keeping!!

But I think you'll find the knife is being held to your own throat by
yourself!

The more you try to cut costs, the more likely you are to get burned.  And
as companies look off shore more and more because of high labour rates in
the USA, more and more technology will be off shore.  But that's
globalization for you.  The ideal is not to build anything yourself but sell
ideas to other countries so they get polluted not you >:-)  only problem is
.. sooner or later, they will develop ideas and sell them back to you.

So.. if you want to keep your ideas.. then think local employ staff locally
if you can.. but keep the intellectual property in house.  will give you
something to sell during the next dot-com crash :-)

I myself think you should design local, and if it picks up.. manufacture
global.  It will cost more up front, but at least you know where your design
is going and can be reasonably assured that you will be making the profit
from your design.  But also only go to respectable manufactures.. so you
keep your design

Simon

"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:ChpYa.49$6x2.6678595@newssvr14.news.prodigy.com...
> I've been debating for several days whether or not to post this message.
> Well...here it goes, we'll see what develops.
>
> I read a disturbing article this last week in Time magazine.  It seems to
be
> available online at
> http://www.time.com/time/magazine/article/0,9171,1101030804-471198,00.html
.
> This article describes the alarming rate at which many types of jobs are
> being exported to countries such as India, where the work gets done for
darn
> near 1/10th. the cost, or less.
>
> Now, before anybody beats me over the head with a digital club, please
know
> that my intention here is to understand the trend and what it might mean
in
> general.  As a small business owner facing the need to hire engineers
> (FPGA/embedded) within the next six to twelve months I have to ask myself
if
> my competitors have exported these jobs?  If that were to be the case,
> competitive forces alone would almost dictate that I (and others in my
> position) look for offshore solutions.
>
> Of course this isn't an issue just in the U.S. I imagine it affects other
> markets where wages and the cost of living and doing business is higher
than
> for some of the offshore providers.
>
> What is interesting and ironic is that some of the technologies that have
> enabled this (I'm thinking Internet) were invented, funded, deployed and
> developed by the U.S.  Now, improved communications and all related
> technologies make the all but most barriers to doing business evaporate.
> The same applies to software, operating systems, tools, etc.
>
> That's another issue: software piracy.  The widespread offshore
availability
> of very expensive software for virtually nothing is certainly a factor in
> shifting the business equation in favor of these providers.  I've had to
pay
> tens of thousands of dollars for all of my development software and I know
> that there's someone out there who paid $6 (if at all) for what cost me
> $10K.  A level playing field it is not, by far.
>
> Where is this going?  I'm all for globalization and economic prosperity at
> every point on the globe, but there are ways of doing it right and, it
seems
> to me, this isn't one of them.  This feels like a nasty big knife cutting
> our own throats on a daily basis.  How do we do this so that everyone
wins?
> And, how does someone like me support his local talent pool without going
> out of business?
>
>
> -- 
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_"  =  "martineu"
>
>



Article: 59053
Subject: Re: Error Generate Statement
From: "Ansgar Bambynek" <a.bambynek_xxx_@avm.de>
Date: Thu, 7 Aug 2003 14:12:05 +0200
Links: << >>  << T >>  << A >>
Hi Isaac,

you are trying to read a port of type output.
>>> output1 <= Outputs(1);  and the following lines below.

This is not allowed in VHDL. So either change the port to type buffer

entity Invert_8 is
port ( Inputs :std_logic_vector (1 to 8);
clock : in std_logic ;
Outputs : buffer std_logic_vector (1 to 8));

(not recommended)

or use a temporary signal for mapping.
e.g.

signal tmp_out_s : std_logic_vector (1 to 8);
...

Outputs <= tmp_out_s;

InverterGenerated : for I in 1 to 8 generate
Inv : Inverter port map (Inputs(I),clock, tmp_out_s(I));
end generate ;
...

process (clock)
begin
if (clock'EVENT and clock ='1') then
output1 <= tmp_out_s(1);
...


BTW. your inverter is a ff since the output changes only during a
rising_edge of the clock.
These outputs are clocked again into a second ff within the following
process

> process (clock)
> begin
> if (clock'EVENT and clock ='1') then
> output1 <= Outputs(1);

I'm not sure if this is your desired behaviour.

HTH

Ansgar

--
Attention please, reply address is invalid, please remove "_xxx_" ro reply


"Isaac" <fpga_uk@yahoo.co.uk> schrieb im Newsbeitrag
news:889eb3fb.0308070244.cdb8e6e@posting.google.com...

> Hi Fellows,
>
> I am just getting used to generate statement. Do begin with 8 bit
> inverter is generated using Generate Command. Now I want to connect
> the out put of one inverter to the input of other invertor or you can
> say to cascade the 8 inverters. I will just apply input to the first
> inverter and at every clock pulse output is tranfered sequentially to
> other inverter.
> I have written the VHDL code below But I am getting following error.
> Help would be appreciated .
>
>
>
ERROR ---------------------------------------------------------------------
> # Error: ELAB1_0008: generate.vhd : (31, 16): Cannot read output :
> "Outputs".
> # Error: ELAB1_0008: generate.vhd : (32, 16): Cannot read output :
> "Outputs".
> # Error: ELAB1_0008: generate.vhd : (33, 16): Cannot read output :
> "Outputs".
> # Error: ELAB1_0008: generate.vhd : (34, 16): Cannot read output :
> "Outputs".
> # Error: ELAB1_0008: generate.vhd : (35, 16): Cannot read output :
> "Outputs".
> # Error: ELAB1_0008: generate.vhd : (36, 16): Cannot read output :
> "Outputs".
> # Error: ELAB1_0008: generate.vhd : (37, 16): Cannot read output :
> "Outputs".
>
> VHDL
CODE ---------------------------------------------------------------------
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
>
> entity Invert_8 is
> port ( Inputs :std_logic_vector (1 to 8);
> clock : in std_logic ;
> Outputs : out std_logic_vector (1 to 8));
> end Invert_8;
>
> Architecture Behaviour of Invert_8 is
> component Inverter
> port ( I1 : std_logic ;
> clock : in std_logic;
> O1 : out std_logic );
> end component ;
> signal output1  : std_logic ;
> signal output2  : std_logic ;
> signal output3  : std_logic ;
> signal output4  : std_logic ;
> signal output5  : std_logic ;
> signal output6  : std_logic ;
> signal output7  : std_logic ;
> begin
>
> InverterGenerated : for I in 1 to 8 generate
> Inv : Inverter port map (Inputs(I),clock, Outputs(I));
> end generate ;
>
> process (clock)
> begin
> if (clock'EVENT and clock ='1') then
> output1 <= Outputs(1);
> output2 <= Outputs(2);
> output3 <= Outputs(3);
> output4 <= Outputs(4);
> output5 <= Outputs(5);
> output6 <= Outputs(6);
> output7 <= Outputs(7);
> end if ;
> end process ;
> InverterGenerated_1 : Inverter
> port map (
> Inputs(1),clock, Outputs(1)
>   );
> InverterGenerated_2 : Inverter
> port map (
> I1 => output1,
> clock => clock, O1 => Outputs(2)
> );
> InverterGenerated_3 : Inverter
> port map (
> I1 => output2,
> clock => clock, O1 => Outputs(3)
> );
> InverterGenerated_4 : Inverter
> port map (
> I1 => output3,
> clock => clock, O1 => Outputs(4)
> );
> InverterGenerated_5 : Inverter
> port map (
> I1 => output4,
> clock => clock, O1 => Outputs(5)
> );
> InverterGenerated_6 : Inverter
> port map (
> I1 => output5,
> clock => clock, O1 => Outputs(6)
> );
> InverterGenerated_7 : Inverter
> port map (
> I1 => output6,
> clock => clock, O1 => Outputs(7)
> );
> InverterGenerated_8 : Inverter
> port map (
> I1 => output7,
> clock => clock, O1 => Outputs(8)
> );
>  end Behaviour;
> --
>  library IEEE;
> use IEEE.STD_LOGIC_1164.all;
>  entity Inverter is
> port ( I1 : std_logic ;
> clock : in std_logic;
> O1 : out std_logic  );
> end Inverter;
> Architecture Behav of Inverter is
>
> begin
> process (I1,clock)
> begin
> if (clock'EVENT and clock='1') then
> O1 <= not (I1);
> end if;
> end process ;
> end Behav;




Article: 59054
Subject: Re: power saving condition test ?
From: "Jim Wu" <jimwu88NOOOOSPAM@yahoo.com>
Date: Thu, 07 Aug 2003 13:47:12 GMT
Links: << >>  << T >>  << A >>
Sorry, my mistake. I was thinking in a case where another branch exists to
set a = 1. e.g

if (a&b) a <= 0;
else if (c) a <= 1;

is certainly not the same as

if (b) a <= 0;
else if (c) a <= 1;

Anyway, synthesis tools are supposed to remove any redundant terms in
equations. As for the power saving, in CMOS, ideally there shouldn't be
additional power consumption if a doesn't change value.

Jim Wu
jimwu88NOOOOOSPAM@yahoo.com


Robert Finch <robfinch@sympatico.ca> wrote in message
news:ZvhYa.4853$pq5.746907@news20.bellglobal.com...
> > If you write down the truth table, you will see the two equations are
not
> > equivalent.
>
> Ok,
>
> line a b new a
>      -----------
> 1   0 0 a (old a)
> 2   0 1 a (old a)
> 3   1 0 a (old a)
> 4   1 1 0 (new value for a=0)
>
> the only time 'a' changes is if both a and b are 1
> however, looking at line 2, it is safe to convert the table to the
> following:
>
>   a b new a
>   -----------
> 1 0 0 a (old a)
> 2 0 1 0 (new value for a=0) - no problem because old value already be zero
> 3 1 0 a (old a)
> 4 1 1 0 (new value for a=0)
>



Article: 59055
Subject: Re: Xilinx ISE WebPack 5.2 & VHDL : wait synthesis
From: "Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com>
Date: Thu, 07 Aug 2003 16:01:44 +0200
Links: << >>  << T >>  << A >>
max wrote:
> I tried this source code:
> 
> entity main is
>     Port ( clk , en : in std_logic;
>            sout : out std_logic);
> end main;
> 
> architecture Behavioral of main is
> begin
>   process
>   variable a : std_logic;
>   begin
>     sout <= '0';
>     a := '0';
>     wait until rising_edge(en);
>     while en = '1' loop
> -- wait until rising_edge(clk);
>       wait until clk'event and clk = '1';
>       a := not a;
>       sout <= a;
>     end loop;
>   end process;
> 
> end Behavioral;
> 
> and I obtain this error:
> 
> Analyzing Entity <main> (Architecture <behavioral>).
> ERROR:Xst:825 - C:/Lavori/menfis/prova_xilinx/prova_2/main.vhd line xx: Wait 
> statement in a procedure is not accepted.
> 
> The question is: can I use wait or not?
> I found a lot of manual on the internet (eg. 
> http://mikro.e-technik.uni-ulm.de/vhdl/anl-engl.syn/html/node8.html), and all of 
> them sais that 'wait' is allowed in synthesis.
> 
> thanks
> 

Your code is NOT a synthesable code.

Don't use 'wait' for synthesis code, but use 'wait' for your testbench 
tester.

A synthesisable code will follow the rules:
- reset signal can be asynchro. or synchro.
- enable signal is ever synchro.
- if possible use only signal (don't use variable for synthesable code)

LOOK:

  entity main is
      Port ( clk , en : in std_ulogic;
             sout : out std_ulogic);
  end main;

  architecture Behavioral of main is
  signal a : std_ulogic;
  begin
    process (clk)
    begin
      if rising_edge(clk) then
        if en = '1' then
          a <= not a;
          sout <= a;
        end if ;
      end if;
    end process;

  end Behavioral;

PS: 'wait' and 'variable' are GREAT for simulation
     try http://www.amontec.com/vhdl_part.shtml

Laurent Gauch
www.amontec.com



Article: 59056
Subject: Xilinx Error Msg- Help Required
From: kalimuddin@hotmail.com (Muhammad Khan)
Date: 7 Aug 2003 07:27:12 -0700
Links: << >>  << T >>  << A >>
Hello Friends

I am getting following errors, Does any one know how to resolve this error.


Reading NGO file
"C:/Project/StepImp/simpleQ/gen6/
xnodes/nodes.ngc" ...
Reading component libraries for design expansion...
Loading design module
"C:\Project\StepImp\simpleQ\gen6\
xnodes/nodes.ngc"...
FATAL_ERROR:NgdBuild:basnbmain.c:1910:1.71.4.1 - Design is empty.   Process will
   terminate.  To resolve this error, please consult the Answers Database and
   other online resources at http://support.xilinx.com. If you need further
   assistance, please open a Webcase by clicking on the "WebCase" link at
   http://support.xilinx.com
ERROR: NGDBUILD failed
Reason: 



Rgd 

Khan

Article: 59057
Subject: Spartan-IIE LVDS?
From: eric_usenet@yahoo.com (Eric)
Date: 7 Aug 2003 08:06:09 -0700
Links: << >>  << T >>  << A >>
Hello! I'm trying to move 125 MB/sec bidirectionally off a daughter
card, for a total of 250 MB/sec. I worry that even if I double the 8
bit bus in each direction to 16-bits (32 data pins todal) I'll still
be pushing a single-ended signal across a connector at 62.5 MHz. I
can't go wider because I run out of pins on my QFP.

I've started looking at LVDS, but it seems that xilinx has very little
information on how to actually _use_ lvds in a project. National has
some great app notes, but they're largely targeted at the national
family of SERDES products. Can anyone offer any suggestions for
high-speed multi-board data transfer between FPGAs? Has anyone ever
tried building a SerDes in a spartan-IIE, and if so, what kinds of
speeds have you been able to get?

Thanks for the help!
                 ...Eric

Article: 59058
Subject: How to find the intersection of two vectors?
From: zhenxu2000@hotmail.com (Zhen)
Date: 7 Aug 2003 08:36:10 -0700
Links: << >>  << T >>  << A >>
I have a question:
There are two vectors, V1 and V2. V1 is a 1*20 vector and V2 is a 1*30
vector. V is the intersection of V1 and V2. We already have known that
V only can be either a null vector or a 1*1 vector(that is at most
there is one element in V1 and V2 is the same). for example:V1 =
[2,5,6,8,9,42,...], V2=[21,24,4,9,35...]then V=[9].
So the input is: V1 , V2,
output: V (0, if the intersection is null)
Can this function be implemented in hardware? Can it be implemented in
a chip? which chip can I use? what is the cost? what is the delay?
Thanks,

Article: 59059
Subject: Re: Offshore engineering
From: "Steve Casselman" <sc_nospam@vcc.com>
Date: Thu, 07 Aug 2003 15:46:23 GMT
Links: << >>  << T >>  << A >>
> What is interesting and ironic is that some of the technologies that have
> enabled this (I'm thinking Internet) were invented, funded, deployed and
> developed by the U.S.  Now, improved communications and all related
> technologies make the all but most barriers to doing business evaporate.
> The same applies to software, operating systems, tools, etc.

I think the web browser and http was developed by someone at CERN and then
"developed" by Netscape. ARPA net was only developed so the US could fight
the USSR and would not have been funded by any US company. "No one is going
to use it" was what you heard back then. The Internet was made possible by
the whole world in spite of the US who would have kept it for the Military
if they could.

>
> That's another issue: software piracy.  The widespread offshore
availability
> of very expensive software for virtually nothing is certainly a factor in
> shifting the business equation in favor of these providers.  I've had to
pay
> tens of thousands of dollars for all of my development software and I know
> that there's someone out there who paid $6 (if at all) for what cost me
> $10K.  A level playing field it is not, by far.

What makes you think that they only steal software over seas? That is
laughable. And it is very much a US frame of mind.

"The US is great! Everything we do is the right thing. We are never wrong.
God is on our side. Other countries are full of heathens and thieves. People
in other countries have no ethics they are just out to get us. We have all
brains and they are just pretending to be friendly to get our technology.
They send students over here just to rip us off."

The fact is we use a lot of resources and that costs a lot of money. I come
home and have beer in a disposable can watch hours of advertizing on TV and
drive a car where ever I go. I demand enough money to do this and so does
everyone else in the US. I eat meat at every meal from animals that take 10
pounds of grain to produce 1 pound of meat. They don't do that in India or
China. Their cost of living is lower and so they demand less money.

So you get what you pay for. Treat the international market like any other.
Shop around ask for references. If you feel better with someone who sits in
your office that you can talk to every day go for. If you have somehthing
that can be farmed out then do that. But don't think that everyone who works
for less money is doing it because they are ripping off whatever they need.

Steve




Article: 59060
Subject: Re: How to find the intersection of two vectors?
From: "John_H" <johnhandwork@mail.com>
Date: Thu, 07 Aug 2003 15:58:56 GMT
Links: << >>  << T >>  << A >>
Since you can describe it so easily, yes it can be implemented in hardware.

The question left unanswered is how much speed do you want at the cost of
size?

If the vectors are loaded a byte at a time, the comparisons could be made as
the vectors are loaded.
A broad-side identity compare of 20 values versus 30 values could be done in
one clock but the number of compares are huge.

Stepping through each comparison - one per clock cycle - would take up to
600 clock cycles to achieve a match.

Does this homework have a desired outcome in area or speed?


"Zhen" <zhenxu2000@hotmail.com> wrote in message
news:7b390929.0308070736.128be22@posting.google.com...
> I have a question:
> There are two vectors, V1 and V2. V1 is a 1*20 vector and V2 is a 1*30
> vector. V is the intersection of V1 and V2. We already have known that
> V only can be either a null vector or a 1*1 vector(that is at most
> there is one element in V1 and V2 is the same). for example:V1 =
> [2,5,6,8,9,42,...], V2=[21,24,4,9,35...]then V=[9].
> So the input is: V1 , V2,
> output: V (0, if the intersection is null)
> Can this function be implemented in hardware? Can it be implemented in
> a chip? which chip can I use? what is the cost? what is the delay?
> Thanks,



Article: 59061
Subject: Excalibur - lpm_syncram
From: "Andrea" <aa@bb.cc>
Date: Thu, 7 Aug 2003 18:02:46 +0200
Links: << >>  << T >>  << A >>
Hi all,

I am developing a design using excalibur device (ExcaliburArm family -
EPXA10F1020C3).
I read on apex manual that ESB supports clock enable, but when I tried to
instantiate an ALT_SYNCRAM with input clock enable (using MegaWizard Plug_in
Manager) the elaboration prosess gives me this error:
"Assertion error: Can't implement single port RAM for EXCALIBUR_ARM device
family from altsyncram megafunction because clock enable ports are not
supported in altram megafunction"

What's wrong?

Thanks in advance!!!

Andrea



Article: 59062
Subject: Re: Spartan-IIE LVDS?
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 07 Aug 2003 09:04:26 -0700
Links: << >>  << T >>  << A >>
Eric, what makes you think that 62 MHz I/O transfer is a problem?
You can easily go twice as fast...

Peter Alfke, Xilinx
=========================
Eric wrote:
> 
> Hello! I'm trying to move 125 MB/sec bidirectionally off a daughter
> card, for a total of 250 MB/sec. I worry that even if I double the 8
> bit bus in each direction to 16-bits (32 data pins todal) I'll still
> be pushing a single-ended signal across a connector at 62.5 MHz. I
> can't go wider because I run out of pins on my QFP.
> 
> I've started looking at LVDS, but it seems that xilinx has very little
> information on how to actually _use_ lvds in a project. National has
> some great app notes, but they're largely targeted at the national
> family of SERDES products. Can anyone offer any suggestions for
> high-speed multi-board data transfer between FPGAs? Has anyone ever
> tried building a SerDes in a spartan-IIE, and if so, what kinds of
> speeds have you been able to get?
> 
> Thanks for the help!
>                  ...Eric

Article: 59063
Subject: Re: Does Xilinx Webpack 5.2 work on WinNT SP6?
From: Steve Lass <lass@xilinx.com>
Date: Thu, 07 Aug 2003 10:12:28 -0600
Links: << >>  << T >>  << A >>
Giuseppeł wrote:

>From the 5.0 version, ISE doesn't support Nt.
>You have to upgrade to Win2000 or Xp if you want to upgrade.
>Another way is to use Red Hat Linux and wine but I never tried it.
>I hear that the new release 6.x, that will be available in the end of 2003,
>support Linux native, but I'm not sure.
>
ISE 6.1i will be available in September and will support native Linux. 
 The WebPACK, however,
will not be available on Linux this year.

Steve

>
>Regards
>Giuseppe
>
>"Jim Wu" <jimwu88NOOOOSPAM@yahoo.com> ha scritto nel messaggio
>news:QSdYa.15959$mZ6.13063@nwrdny02.gnilink.net...
>  
>
>>I am currently using Xilinx Webpack 4.1 on a WinNT (SP6) machine and
>>thinking to upgrade to version 5.2. The web site does not say v5.2
>>    
>>
>supports
>  
>
>>WinNT. I was wondering if anyone has tried the latest webpack  on WinNT.
>>
>>Thanks
>>Jim
>>
>>
>>    
>>
>
>
>  
>


Article: 59064
Subject: Re: Patent granted for "system on a chip" framework?
From: y_p_w@hotmail.com (y_p_w)
Date: 7 Aug 2003 09:24:01 -0700
Links: << >>  << T >>  << A >>
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<4ofYa.15$BU7.2095256@newssvr14.news.prodigy.com>...
> No surprise to me.  Some guy out of MIT got a patent for the mechanics of
> the human arm (actually, any articulation-muscle mechanism on any animal on
> earth for the last several billion years).

That actually makes some sense, if the purpose was to create a
mechanical replica - i.e. prosthetics or a robot arm.  This new
patent would seemingly describe a set of techniques that most
engineers would never thought of patenting because they were
(more or less) in the public domain.

> Face it, patents are business tools.  They have nothing to do with invention
> any more.  Very few things any more are inventions, most are
> implementations.  Most are things that good engineers should be able to
> produce given a problem and related constraints.
> 
> Oh well.

I wouldn't have any problems if someone actually took this idea from
the world of FPGAs - extended it to SoC - and then patent the idea
before anyone else had used it.  However - this doesn't seem to be
the case.

I really hope this doesn't turn into the SCO Unix vs Linux fight.

Article: 59065
Subject: Re: Patent granted for "system on a chip" framework?
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Thu, 07 Aug 2003 16:32:34 GMT
Links: << >>  << T >>  << A >>
"y_p_w" <y_p_w@hotmail.com> wrote in message
news:591da479.0308070824.769ead96@posting.google.com...
> "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:<4ofYa.15$BU7.2095256@newssvr14.news.prodigy.com>...
> > No surprise to me.  Some guy out of MIT got a patent for the mechanics
of
> > the human arm (actually, any articulation-muscle mechanism on any animal
on
> > earth for the last several billion years).
>
> That actually makes some sense, if the purpose was to create a
> mechanical replica - i.e. prosthetics or a robot arm.  This new
> patent would seemingly describe a set of techniques that most
> engineers would never thought of patenting because they were
> (more or less) in the public domain.

Well, not in this case, at least in my opinion.  It describes something they
call "series elastic" actuators.  Translation: store energy in a spring (or
spring-like element) as opposed to having the motors directly drive the
joint.  In other words, a tendon.  Using springs to store energy (or control
force) has been in use for a long, long time, I think.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"





Article: 59066
Subject: Re: How to find the intersection of two vectors?
From: "Jim Wu" <jimwu88NOOOOSPAM@yahoo.com>
Date: Thu, 07 Aug 2003 16:35:15 GMT
Links: << >>  << T >>  << A >>
Given the assumption that there is at most one intersection, you can
actually combine the two vectors into an 1x50 vector and count which number
appears twice.

Jim Wu
jimwu88NOOOOSPAM@yahoo.com


"John_H" <johnhandwork@mail.com> wrote in message
news:4HuYa.21$OX.9443@news-west.eli.net...
> Since you can describe it so easily, yes it can be implemented in
hardware.
>
> The question left unanswered is how much speed do you want at the cost of
> size?
>
> If the vectors are loaded a byte at a time, the comparisons could be made
as
> the vectors are loaded.
> A broad-side identity compare of 20 values versus 30 values could be done
in
> one clock but the number of compares are huge.
>
> Stepping through each comparison - one per clock cycle - would take up to
> 600 clock cycles to achieve a match.
>
> Does this homework have a desired outcome in area or speed?
>
>
> "Zhen" <zhenxu2000@hotmail.com> wrote in message
> news:7b390929.0308070736.128be22@posting.google.com...
> > I have a question:
> > There are two vectors, V1 and V2. V1 is a 1*20 vector and V2 is a 1*30
> > vector. V is the intersection of V1 and V2. We already have known that
> > V only can be either a null vector or a 1*1 vector(that is at most
> > there is one element in V1 and V2 is the same). for example:V1 =
> > [2,5,6,8,9,42,...], V2=[21,24,4,9,35...]then V=[9].
> > So the input is: V1 , V2,
> > output: V (0, if the intersection is null)
> > Can this function be implemented in hardware? Can it be implemented in
> > a chip? which chip can I use? what is the cost? what is the delay?
> > Thanks,
>
>



Article: 59067
Subject: Re: Offshore engineering
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Thu, 07 Aug 2003 16:55:51 GMT
Links: << >>  << T >>  << A >>
"Steve Casselman" wrote:

> The Internet was made possible by
> the whole world in spite of the US who would have kept it for the Military
> if they could.

This is not true.  But this isn't what I wanted to see discussed here.

> What makes you think that they only steal software over seas? That is
> laughable. And it is very much a US frame of mind.
>
> "The US is great! Everything we do is the right thing. We are never wrong.
> God is on our side. Other countries are full of heathens and thieves.
People
> in other countries have no ethics they are just out to get us. We have all
> brains and they are just pretending to be friendly to get our technology.
> They send students over here just to rip us off."


This is precisely the sort of answer I did not want to see.  Please, no
insults or attacks.

Of course I know that software piracy is rampant in the US as well.  We
probably invented that too!  However, in some parts of the world virtually
nobody buys sofware, ever.  I've seen this first hand, in two continents.
While travelling I've seen "services" that sell just about any software you
want for three to six bucks.  The fact that such deals are common-knowledge
(to locals) has to mean something.

> But don't think that everyone who works
> for less money is doing it because they are ripping off whatever they
need.

Again, you got me all wrong.  I'm sorry if I didn't make my post clear
enough for everyone to understand.  Please don't take me as an
ego/USA-centric whacko.  That I am not.  By far.  I'm well travelled, speak
4 1/2 languages and even have family in several continents.  I love my
country, but I also know, understand and accept that it has much wrong with
it and much to be ashamed of.  But, who doesn't?

This matter of global high-tech resource availability is something that will
fundamentally change our lives.  Within my small little sliver of the world
I'm trying to understand what it means and how to deal with it.  How to use
it or not.  I'm having web site design work done offshore for $1,000 that
would cost $20K to $50K to have done in the US.  It sort of hurts because I
know that someone here isn't getting the work.

To be somewhat on topic, I can get FPGA work done offshore for 1/10th of
what it would cost to hire one FPGA guy here.  Or, seen another way, I could
have a team of ten FPGA guys offshore for the same cost of one guy locally.
That's mind boggling.  Large companies are exporting whole departments.  You
follow this to conclusion and, I begin to have doubts about coaxing my son
towards technical fields (he's 4 1/2, so this will be a reality to contend
with in his adult life).


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"





Article: 59068
Subject: Re: Error Generate Statement
From: lishu99@yahoo.com (Lis Hu)
Date: 7 Aug 2003 10:19:21 -0700
Links: << >>  << T >>  << A >>
The error messages refer to the fact that "outputs" is declared
an output of the entity invert_8, and so you can't use their values
to assign to another signal within the entity in these lines:

> 	process	 (clock)
> 		begin 
> 			if 	(clock'EVENT and clock ='1') then	
> 				output1 <= Outputs(1); 
> 				output2 <= Outputs(2);
> 				output3 <= Outputs(3);
> 				output4 <= Outputs(4);
> 				output5 <= Outputs(5);
> 				output6 <= Outputs(6);
> 				output7 <= Outputs(7); 
> 			end if ;
> 		end process	;

Article: 59069
Subject: Re: Offshore engineering
From: Sander Vesik <sander@haldjas.folklore.ee>
Date: Thu, 7 Aug 2003 18:54:35 +0000 (UTC)
Links: << >>  << T >>  << A >>
Martin Euredjian <0_0_0_0_@pacbell.net> wrote:
> 
> Of course I know that software piracy is rampant in the US as well.  We
> probably invented that too!  However, in some parts of the world virtually
> nobody buys sofware, ever.  I've seen this first hand, in two continents.
> While travelling I've seen "services" that sell just about any software you
> want for three to six bucks.  The fact that such deals are common-knowledge
> (to locals) has to mean something.

The "apparent" problem would be resolved if the countries withdrew from Berne
convention (are you sure they are in it?) - of course this would be followed
by massive taxes on any exports to US and general political nastiness (up to
and including funding of anybody who will want to overthrow the regime), but
it is an option in principle. There are also cases like say certain 7 countries
to which US companies are incapable of legaly selling software licences to...

[snip]

> To be somewhat on topic, I can get FPGA work done offshore for 1/10th of
> what it would cost to hire one FPGA guy here.  Or, seen another way, I could
> have a team of ten FPGA guys offshore for the same cost of one guy locally.
> That's mind boggling.  Large companies are exporting whole departments.  You
> follow this to conclusion and, I begin to have doubts about coaxing my son
> towards technical fields (he's 4 1/2, so this will be a reality to contend
> with in his adult life).

This cuts both ways... Why would non-technical jobs remain over time if all
techincal ones have left? conversly, similar forces will work over time in
the places they are now moving. The simple way to look at it is that wages
in the US have been hyperinflated compared to the rest of the world and its
simple economic forces at work - a 2-to-1 devaluation of dollar while
keeping wages constant would do wonders to decrease such movements.

-- 
	Sander

+++ Out of cheese error +++

Article: 59070
Subject: Re: Error Generate Statement
From: smukthav@yahoo.com (Sandeep)
Date: 7 Aug 2003 12:05:02 -0700
Links: << >>  << T >>  << A >>
You cannot read the output ports. There are two ways you can solve
this....make the signals on the entity "Outputs" as type inout or
create an internal signal Outputs and assign the internal signal to
the Outputs. The second approach though is tedious doesnt actually
create anymore extra logic. The first approach sometime confuses the
synthesis tool when trying to resolve in/out and may infer tri-state
logic if it cannot figure out.
fpga_uk@yahoo.co.uk (Isaac) wrote in message news:<889eb3fb.0308070244.cdb8e6e@posting.google.com>...
> Hi Fellows, 
> 
> I am just getting used to generate statement. Do begin with 8 bit
> inverter is generated using Generate Command. Now I want to connect
> the out put of one inverter to the input of other invertor or you can
> say to cascade the 8 inverters. I will just apply input to the first
> inverter and at every clock pulse output is tranfered sequentially to
> other inverter.
> I have written the VHDL code below But I am getting following error.
> Help would be appreciated .
> 
> 
> ERROR ---------------------------------------------------------------------
> # Error: ELAB1_0008: generate.vhd : (31, 16): Cannot read output :
> "Outputs".
> # Error: ELAB1_0008: generate.vhd : (32, 16): Cannot read output :
> "Outputs".
> # Error: ELAB1_0008: generate.vhd : (33, 16): Cannot read output :
> "Outputs".
> # Error: ELAB1_0008: generate.vhd : (34, 16): Cannot read output :
> "Outputs".
> # Error: ELAB1_0008: generate.vhd : (35, 16): Cannot read output :
> "Outputs".
> # Error: ELAB1_0008: generate.vhd : (36, 16): Cannot read output :
> "Outputs".
> # Error: ELAB1_0008: generate.vhd : (37, 16): Cannot read output :
> "Outputs".
> 
> VHDL CODE ---------------------------------------------------------------------
> library IEEE;
> use IEEE.STD_LOGIC_1164.all; 	
> 
> entity Invert_8 is 
> 	port ( Inputs :std_logic_vector (1 to 8);
> 	clock : in std_logic ;
> 	Outputs : out std_logic_vector (1 to 8));
> end Invert_8;
> 
> Architecture Behaviour of Invert_8 is 
> component Inverter
> 	port ( I1 : std_logic ; 
> 	clock : in std_logic;
> 	O1 : out std_logic );
> end component	;
> signal	output1  : std_logic ;	
> signal	output2  : std_logic ;
> signal	output3  : std_logic ;
> signal	output4  : std_logic ;
> signal	output5  : std_logic ;
> signal	output6  : std_logic ;
> signal	output7  : std_logic ;
> begin 
> 	
> 	InverterGenerated : for I in 1 to 8 generate 
> 		Inv : Inverter port map (Inputs(I),clock, Outputs(I));
> 	end generate ; 	
> 
> 	process	 (clock)
> 		begin 
> 			if 	(clock'EVENT and clock ='1') then	
> 				output1 <= Outputs(1); 
> 				output2 <= Outputs(2);
> 				output3 <= Outputs(3);
> 				output4 <= Outputs(4);
> 				output5 <= Outputs(5);
> 				output6 <= Outputs(6);
> 				output7 <= Outputs(7); 
> 			end if ;
> 		end process	;
> 	InverterGenerated_1 : Inverter
> 	port map (
> 				Inputs(1),clock, Outputs(1)
> 			  );   
> 	InverterGenerated_2 : Inverter
> 	port map (
> 	I1 => output1,
> 	clock => clock, O1 => Outputs(2)
> 	);
> 	InverterGenerated_3 : Inverter
> 	port map (
> 	I1 => output2,
> 	clock => clock, O1 => Outputs(3)
> 	);
> 	InverterGenerated_4 : Inverter
> 	port map (
> 	I1 => output3,
> 	clock => clock, O1 => Outputs(4)
> 	);
> 	InverterGenerated_5 : Inverter
> 	port map (
> 	I1 => output4,
> 	clock => clock, O1 => Outputs(5)
> 	);			  
> 	InverterGenerated_6 : Inverter
> 	port map (
> 	I1 => output5,
> 	clock => clock, O1 => Outputs(6)
> 	);					  
> 	InverterGenerated_7 : Inverter
> 	port map (
> 	I1 => output6,
> 	clock => clock, O1 => Outputs(7)
> 	);
> 	InverterGenerated_8 : Inverter
> 	port map (
> 	I1 => output7,
> 	clock => clock, O1 => Outputs(8)
> 	);
>  end Behaviour;
> --
>  library IEEE;
> use IEEE.STD_LOGIC_1164.all; 	
>  entity	Inverter is 
> port ( I1 : std_logic ;
> 		clock : in std_logic;
> 		O1 : out std_logic  );
> end Inverter;
> Architecture Behav of Inverter is 
> 
> begin 
> 	process	(I1,clock)
> 	begin 
> 		if (clock'EVENT and clock='1') then 
> 			O1 <= not (I1);
> 		end if;
> 	end process	;
> end Behav;

Article: 59071
Subject: Re: Error Generate Statement
From: Keith Williams <krw@attglobal.net>
Date: Thu, 7 Aug 2003 15:24:00 -0400
Links: << >>  << T >>  << A >>
In article <d9db536c.0308071105.115657b4@posting.google.com>, 
smukthav@yahoo.com says...
> You cannot read the output ports. There are two ways you can solve
> this....make the signals on the entity "Outputs" as type inout or
> create an internal signal Outputs and assign the internal signal to
> the Outputs. The second approach though is tedious doesnt actually
> create anymore extra logic. The first approach sometime confuses the
> synthesis tool when trying to resolve in/out and may infer tri-state
> logic if it cannot figure out.

You can also assign the entity "outputs" as type buffer.  I recommend 
the internal signal method though.

-- 
  Keith

Article: 59072
Subject: Need help: getting 3.1i Coregen working on P4-system
From: Bob_Myers@raytheon.com
Date: Thu, 07 Aug 2003 19:56:14 GMT
Links: << >>  << T >>  << A >>
Hi;

I've had to install 3.1i on a P4-based machine at work.  (Found the 
instructions on
replacing the default JRE image on the install disk --> worked great).

However, I seem to be having a problem now with getting COREGEN to 
work.  Seems that COREGEN is java-based, and runs with the JRE 
distribution
that is installed in the 3.1i structure. 

Has anyone ever had to get COREGEN working on a P4-based machine?
If so, what steps did you take to get it running?

-bob

Article: 59073
Subject: Re: two questions
From: "Robert Finch" <robfinch@sympatico.ca>
Date: Thu, 7 Aug 2003 16:30:39 -0400
Links: << >>  << T >>  << A >>
> I've got two quick question. I don't have FPGA yet, but I want someone to
> offer me some quick comments
>
> 1. I have got to do some 64 bit integer comparison, actually I have to do
up
> to 64 comparisons at the same time, the output is whether there is any
pair
> that equals.
>

Assuming this means looking for any pair of equal values within a set of 64,
64 bits values:
I think this requires 1x64(compare one value to the other 64)x64(64
different values)x64(bits) = 262,144 bits for comparison. (plus bits
overhead for combining the results) Divide by four since two bits could be
handled per logic cell = about 64k logic cells. That's a lot of logic cells.

Does it have to be done in a single cycle ? The sheer size might make it
slower than using a registered approach that takes multiple cycles. It might
be possible to obtain the same performance using a lot fewer compares across
multiple clock cycles.

Is it okay if there is a latency > one cycle ? In that case it might be
possible to obtain a result every clock cycle, but the first result might
not be available until several clocks have passed.

Perhaps the values could be sorted somehow first, then it's only neccessary
to compare the two middle values. (But the sort itself might use a lot of
logic)

Rob




Article: 59074
Subject: Re: Xuart Lite Linux driver
From: Jon Masters <jonathan@jonmasters.org>
Date: Thu, 07 Aug 2003 21:32:24 +0100
Links: << >>  << T >>  << A >>
Peter Ryser wrote:
> A clarification. The Ethernet SGDMA does not work because the driver support in
> Linux is missing and is currently being added.
> 
> EMAC SGDMA hardware is available and can be included in designs.

http://www.smsc.com/main/catalog/lan91c111.html

I quite like this real physical part myself. :-).

Jon.




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