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<sc01@hotmail.com> wrote in message news:5vFob.60444$1C5.41226@nwrdny02.gnilink.net... > Hi, > Does anyone know how I can convert my verilog code to VHDL? I would ask in comp.lang.verilog or comp.lang.vhdl -- glenArticle: 62551
Mike Treseler wrote: > Kevin Neilson wrote: > >> Can anybody else explain how Shannon's information >> theory applies to black holes? > > > Sounds like just the place for a > First In Never Out (FINO) transmit buffer. > > -- Mike Treseler > Is that FINO or AMONTILLADO? jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 62552
On Fri, 31 Oct 2003 20:43:36 -0500, "Clay S. Turner" <physics@bellsouth.net> wrote: >"Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message >news:3FA3000A.45C10F96@xilinx.com... >>> >> How many bits can fit on the surface of a black hole? (2003) > >Actually the entropy of a black hole works out to be about 10^66 bits/ cm^2. > >Clay I've worked with people denser than that. Or so it seemed, anyway... Eric Jacobsen Minister of Algorithms, Intel Corp. My opinions may not be Intel's opinions. http://www.ericjacobsen.orgArticle: 62553
"Ed J" <jed@privacy.net> wrote in message news:<fvyob.18006$YO5.8966216@news3.news.adelphia.net>... > I writing VHDL for a Xilinx Virtex-II Pro FPGA application, and software for > its embedded PowerPC. The PowerPC doesn't have hardware floating point, and > floating point emulation in software is too slow for my purpose. So, I'm > looking for a way to add floating point in the FPGA fabric through VHDL or > black boxes. I need IEEE floating point operations such as add, subtract, > multiply, divide. I also need some math functions like sine, cosine, square > root, etc. > > Is there a (free) standard package in VHDL that I can use for this? Third > party support? > > I'm a newbie on a budget, so I'm looking for the cheapest, quickest > solution. > > Any advice would be appreciated. > > Ed. Hi Ed I was given these links recently, http://www.quixilica.com/products_qxfpu.htm http://www.nallatech.com/solutions/products/software_fpga_ip/fpga_ip/fpc/index.asp http://www.dcd.pl/ http://www.opencores.org/projects/ opencores would be free, quixilica, nallatech probably aren't. You could check out adding a lowcost DSP (TI,ADI,Zoran etc) or a highend controller with FPU as coprocessor. I think the days of Weitek math engines is long gone. johnjaksonATusaDOTcomArticle: 62554
"jakab tanko" <jtanko@ics-ltd.com> wrote in message news:<bmp871$22k$1@news.storm.ca>...
> Hi all,
>
> I have updated my Xilinx software to 6.1 a few days ago and it
> looks like I am in for a ride; the design that worked well under
> the previous version (5.2 with all service packs) wouldn't even
> go through PAR anymore!! I managed to work around this
> by setting thr effort level to maximum for the place&route but
> when I program the FPGA (XC2V4000-5) with this new bitstream
> my board doesn't work anymore!!?
> Anybody having similar problems?
> I guess I shoild have known better: the service pack for this latest
> software creation arrived before the CD with the software did!
> In my humble oppinion the best software from Xilinx was 4.2,
> it's all downhill from there; it seems that a nice GUI is valued more than
> a decent and consistent PAR algorithm these days.
> ---
> jakab
I have had problems with 5.1,5.2 and 6.1 on XC2V4000 and
XC2V6000 designs. My original designs were done on 4.x. I believe
that the problem is in migrating the 4.2 designs to 6.1.
I use 4.2 to synthesize and route, and Impact 5.2 to program
the FPGAs.
I have reported every problem to Xilinx.
New designs that are originated using 6.1 work OK.
Bill Hanna
Article: 62555
> Does anyone have any examples (CPLD or FPGA), or web links to tutorial
> type examples of such a project?
>
www.fpga4fun.com might help you
RaM
Article: 62556Do not forget to mention level of description (RTL or structural). The latter should be simpler.Article: 62557
"Peter Alfke" <peter@xilinx.com> ha scritto nel messaggio news:3FA14829.68001BC7@xilinx.com... > Why would this be better for small devices Because batteries are big, expensive and unreliable. > Well, you need a $1.00 watch battery... $1 watch battery doesn't last much at 85 degrees C. And when it's finished (hopefully without exploding or corroding the circuit with his acid), the customer needs to send back the device to me, because the key is lost. I think the public/protected key technique is far more reliable and simple. -- LorenzoArticle: 62558
Hi! > As such I shouldn't need wait states, but it is something I've been concious > about and keeping in the back of my mind... knowing full well that > murphie's law will present a nice wishbone slave that I desire to use at > some stage in the future which will require waitstates... I'm just not > excatly sure how to deal with it, considering I can't stall the HC11 bus. As long as you are aware of the limitations, it's OK. > As part of my research and investigations today I discovered an asynchronous > wishbone master on www.opencores.org which appears to be developed by > yourself (http://www.opencores.org/cores/wb_tk/wb_async_master.shtml). Yeah, I know ;-). > Is this correct? It appears that the version on the opencores website is a > lot simplier than the version you presented in your posting. Reading > through the source for the one on opencores.org has cleared a lot of things > up for me and "turned a couple of lightbulbs on" in my mind.. What's the > main differences between the two? I'm having difficulty following the one > in the newsgroup posting while I can pretty much follow the one on > www.opencores.org. The difference is that the one I've shown here actually works. I didn't have time to update the cores on OpenCores, but as I started using them I've found a lot of problems, and in the case of this core for example, I had to completely re-write the whole thing. The old one pretty much goas along the lines of your implementation, and as such, has the same fundamental problems. I know the presented core is a bit confusing, so here are some of the ideas I've used: You have to make sure, you generate exectly one WB cycle for each async bus cycle. That requirement makes the handling of read and write cycles different. For a write cycle, you have to make sure, you use the right data from the async bus in the write cycle on the WB bus. In the general case, the write data is valid at the rising edge of the (negated) control signals of the async bus. This means, that you have to delay the write cycle on the WB side until the write has been finished on the async side. For reads, however you have to start the WB cycle in parallel with the async cycle to make sure you have the right data available at the end of the cycle. Also, in the general case, at the beginning of the read cycle you might not have a valid address on the address-bus, so you might have to wait some time before starting the read-operation. All in all, you need delayed writes and parallel reads. This requirement make the interface quite complicated, because writes happen after the fact. What if the async side initiates another cycle while you're performing that delayed write? You'll have to wait until the current WB bus activity ends, and start the operation only afterwards. The way you handle this wait is again, a bit different for reads and writes, but this fact alone makes correct async-side wait-state generation a must. Another thing to consider is what happens if the async master does not honor your wait states and ends the cycle prematurely. That's an error, of course, but you at least have to recover from it somehow. And finally I've added two different type of wait-state generations: one is a handshake-type, the one used in for example the EPP printer port communication, and the other is the normal open-collector type wait signal used in most uC busses. > The testbench support code in the http://www.opencores.org/cores/wb_tk > project has also helped me out. The use of a VHDL function to wrap up the > inner workings of a bus cycle should stop me from duplicating all those > lines of code in my testbench for every read/write I perform on the bus... Just a side-note: I had test-banches for the old core, and it looked OK to me. At the moment I've added it to a real HW, problems started. Createing good test-benches is really hard. You can test only for what you've thought about and chances are, you got those things right in the design. Real life however tests your design on it's own way, and at the end of the day, that's the test that should pass, not (only) your test-bench. Regards, Andras TantosArticle: 62559
In article <Z9Rob.83415$vO5.3037135@twister1.libero.it>, Lorenzo Lutti <lorenzol@despammed.com> wrote: >> Why would this be better for small devices > >Because batteries are big, expensive and unreliable. > >> Well, you need a $1.00 watch battery... > >$1 watch battery doesn't last much at 85 degrees C. And when it's >finished (hopefully without exploding or corroding the circuit with his >acid), the customer needs to send back the device to me, because the key >is lost. > >I think the public/protected key technique is far more reliable and >simple. How do you PROTCET the secret in the FPGA. THAT is the key. Once you can get a secret in the FPGA, the rest is easy, and private key (eg DES) is actually better for that. AS for keeping the secret in the FPGA, the two options are antifuze/EEPROM style or battery style. And battery -backup is much more effective/easy as it doesn't require process changes. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 62560
>>I need to check a vaue after AVAIL rises to '1'. > Don't forget that "wait until" is EDGE triggered. It > will wait forever if AVAIL is stuck at '1'. And to add to what Jonathan said, if you want to do a level check, do the following: if (Avail /= '1') then wait until AVAIL = '1'; end if ; Read wait as stop. Wait always stops for at least one delta cycle. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 62561
I'd like to thank everybody who answered my questions. Very helpful group here! I've downloaded some tools and ordered some books, and I'll just hope not to disturb the horses. BTW, is there some convenient list "ranking" the various FPGA families available, in terms of size (however that might be measured), and cost? Also, where do CPLDs end and FPGAs begin? Is there some fundamental difference in architecture that draws the line, or is it just a size thing, or??? Are all CPLDs smaller than all FPGAs? (again, however that might be measured) Thanks again, MikeArticle: 62562
X-HDL: http://www.x-tekcorp.com/xhdl3.htm The demo doesn't allow you to save it, though. <sc01@hotmail.com> wrote: :Hi, :Does anyone know how I can convert my verilog code to VHDL? : :Stanley :Article: 62563
Hi, Is there a chance to use 32bit Nios with 16 bit external SRAM? When I add 16bit RAM in SOPC, I got upper and lower words written with the same value. For example: Nios32_ram16bit.A +m40000 #00040000: 35C0 35C0 6C40 6C40 3000 3000 736F 736F #00040010: 3301 3301 0038 0038 0038 0038 7FDF 7FDF #00040020: 7817 7817 9801 9801 9800 9800 9853 9853 #00040030: 9800 9800 7FF2 7FF2 3208 3208 0430 0430 Have you got any ideas how to do it? BTW: Device is EP1C6 -- JerryArticle: 62564
Hi, To configure a Spartan-IIE FPGA, I use a XCF02S PROM. The configuration file in the PROM uses 89% of the memory (this is constant on my 300k gates FPGA). I'm wondering if it is possible to use the remaining memory of the PROM as a way to store my own data, just like if there was a EEPROM attached to the FPGA? thanksArticle: 62565
"Matt North" wrote: >>in the FPGA game, perfectly good code does not equate to a working >>design. > > This is because languages like VHDL are HARDWARE description languages, you > code should be > written is such a way that a synthesis tool can recognise it as a counter, > memory, mux etc. > The tool will then have a better chance at optimise your design. I wasn't refering to synthesis or inference with the above statement. A design within an FPGA is a combination of sound logic (the "program" does what it is supposed to), correct inferred synthesizable logic, explicitly instantiated structures, timing specifications, routing and placement. Generally speaking, standard portable HDL might cover the logic and inference part. I said "might" because you might have to prod it this or that way in order to get 100% inference to your satisfaction. The minute you start to explicitly instantiate primitives you are no longer portable (meaning across device/vendor boundaries). But, now you have the logic you wanted, and, all of this can live within HDL files. But your design might not work. Example: A pipelined adder feeding a multiplier. The HDL is simple. Now, let's say you want it to run at 180MHz. This is a case of "perfectly good code does not equate to a working design" as I said. In order to achieve this level of performance you have to resort to a whole host of timing specification as well as strict floorplanning. The PERIOD constraint is not good enough. You need to use specific connectivity from switch boxes into and out of the mulipliers (about 560ps delay), for example. The HDL description might be perfectly sound ... (descriptively) first clock add a to b produce c second clock add c to d produce e third clock add e to f produce g fourth clock multiply g by h produce result. ... but, despite the code being "perfectly good" this alone won't work. In the sofware world the only parallel I can draw is perhaps with code that might try to access a resource before it is ready. Even though the access logic and algorithm might be perfect, the time factor (or readiness factor) still has to be a part of the whole package. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 62566
>Is there a chance to use 32bit Nios with 16 bit external SRAM? Ehhh... It was completely my fault. I forgot that RAM pin A0 is connected to A1/A17 _not_ to A1 (on Nios EP20K200 board). Now everything is working perfectly :-) -- JerryArticle: 62567
Hi Petter, > I think it's wrong to check for the distribution. One should check for > the functionality required by the tool. If you require a certain > thread library, check for that and report that installation fails > since the specific thread library is not present. The trouble is that you can check for version numbers and such, but not on actual capabilities when you get a distribution shoved in your face. Red Hat 9.0 reports a certain version number for their Posix threads library that is basically the same as the version number reported by the 8.x versions. However, this 9.0 version uses significantly different kernel calls than the 8.x series. How to determine what a library does under the hood... If you've got a good idea that does not involve compiling code and see whether it coredumps, I'll take it. IMHO, Quartus under Linux is pretty flexible when it comes to distributions. I've been using Quartus using Gentoo Linux on a 2.6.0-testX-mmY kernel for the last few months and I haven't had a single problem so far. The main issue that Altera has with Linux distros is supportability - which I have waived ;-) There's only so much useful Linux knowledge you can cram into a support engineer in any given timespan to solve issues, and I think that they made a fairly good, (maybe slighly US-centric) choice. Best regards, BenArticle: 62568
I think you will find that you have over committed the pinout of the device. For some reason this isn't always classified as a fatal error :-) Simon "kryten_droid" <kryten_droid@ntlworld.com> wrote in message news:DHxob.1172$yH4.711@newsfep1-gui.server.ntli.net... > I have an XC2S300E-pq08 which the data sheet says has 146 user I/O max. > > However, the PAR says: > > Number of bonded IOBs: 144 out of 142 101% > > There are still quite a few I/O pins left on my dev board. > > I'm puzzled that it seems I can use any I/O pins but > less than all of them at the same time. > > Is this the case or am I missing something fundamental? > > Thanks in advance, > > K. > > > Command Line : map -p XC2S300E-pq208-6 -cm area -k 4 -c 100 -tx off > Target Device : x2s300e > Target Package : pq208 > Target Speed : -6 > Mapper Version : spartan2e -- $Revision: 1.58 $ > Mapped Date : Fri Oct 31 01:02:35 2003 > >Article: 62569
Hello Everyone, I am interested in buying ntsc video decoder and encoder ic's for a personal project. Specifically, I am looking for the simplest possible ic's that take in an analog signal and output a ccir656/601 8 bit stream (and vice versa). No YCbCr->RGB color conversion or video scaling capability is required, and simple luma/chroma separation would suffice. Does anyone here have some applicable experience ? If so, please point me to a good vendor for these, and, if you can, a ball-park estimate of a price for these. Thanks in advance, Ljubisa BajicArticle: 62570
On 1 Nov 2003 19:23:43 -0800, eternal_nan@yahoo.com (Ljubisa Bajic) wrote: >Hello Everyone, > >I am interested in buying ntsc video decoder and encoder ic's for a >personal >project. Specifically, I am looking for the simplest possible ic's >that take >in an analog signal and output a ccir656/601 8 bit stream (and vice >versa). No YCbCr->RGB color conversion or video scaling capability is >required, and simple luma/chroma separation would suffice. Does anyone >here have some applicable experience ? If so, please point me to a >good vendor for these, and, if you can, a ball-park estimate of a >price for these. > >Thanks in advance, >Ljubisa Bajic hello, Try an AD7176 for the Encoder (www.analog.com). Decoders ... skip the AD7183, TVP5145 is ok but draws a lot of power and has more than you need , the new TVP5150A is very tiny however I am just designing first board with this part (www.ti.com) , SAA7111A but may be harder to get (www.philips.com) , VPX3226 is very cool (www.micronas.com) , there are other options for special requirements. www.arrow.com or www.avnet.com will provide pricing ... symmetry electronics for micronas ... most of these parts are $10-20 depending upon volume. Good Luck, Khim Bittle www.cliftonsystems.com Specializing in video acquistion & processing and cool video widgets with the Altera Cyclone.Article: 62571
I am under the impression that PDA's only have 16 bit PCMCIA interface. The Annapolis device is a card bus, which is really PCI in disguise. What do you use to host this card, a PC or a PDA? It's worth asking Annapolis if they had done a driver for this card. <sc01@hotmail.com> wrote in message news:<rxFob.60464$1C5.25144@nwrdny02.gnilink.net>... > Hi, > Has anyone used or written any WinCE driver for this card? > (Wildcard from Annapolis Micro System www.annapmicro.com) > Where can I possibly find one? > > Any information would be greatly appretiated. > > StanleyArticle: 62572
Mike Silva wrote:
> BTW, is there some convenient list "ranking" the various FPGA families
> available, in terms of size (however that might be measured), and
> cost?
Howdy Mike,
Unfortunately, as broad as your question is, I don't really have a
choice but to answer it in a broad way: part numbers with big numbers
printed on them tend to cost more than the ones with small numbers...
seriously! Prices range from under $10 to over $1k. Prices on these
parts are just like any other mass produced IC... they are volume
driven. Just look at the useless prices that the silly Xilinx product
managers put in their press releases.
The only thing that is a little strange is that only the very newest
products cost a lot. The parts that were introduced a year or so ago
tend to be less expensive (and much better supported) than parts from
three or four years ago. Not to mention the newer parts have
considerably more features and resources per dollar spent.
Definitely go with the newest generation you can afford.
Lastly, some vendors have a line of high (performance/feature/resource)
parts and a line with not-quite-so-high (performance/feature/resource).
Unless you're doing something pretty crazy, you probably don't need
the high line. As an example, earlier this year, I designed a 12 port
Ethernet packet manager, complete with overflow handling, in a Xilinx
Spartan IIE (XC2S150E) [that's on the not-quite-so-high line of
products]. It runs at 100 MHz and handles over 700 Mbps per second in
each direction.
At the opposite end of the spectrum, I have a co-worker that is
currently implementing some logic that brings in data at 2.488 Gbps and
processes it at 311 MHz. He's using a Virtex-2Pro [one of the high
performance parts], mainly because the Spartan line won't handle the 311
MHz clock rate.
> Also, where do CPLDs end and FPGAs begin? Is there some fundamental
> difference in architecture that draws the line, or is it just a size
> thing, or??? Are all CPLDs smaller than all FPGAs? (again, however
> that might be measured)
As you appear to have surmised, there are some very high end CPLDs that
would, in some cases, do more than low-end FPGA's. In
almost-too-general-to-be-useful terms, CPLD's tend to be designed for
wide input functions and relatively low propagation (and easy to
predict) delays. Most (all?) modern FPGA's are build on sea of
four-input lookup tables. Lookup tables can be cascaded (where the
variability compared to CPLD's comes in) to create huge functions.
People may find exception to some of these statements, it is the general
concept that I'm trying to get across.
We've found that FPGA's can be used to do most things that CPLD's do
[except FPGAs must be programmed upon power-up], but not the reverse.
Have fun,
Marc
Article: 62573":: Gabster ::" <gabsterblueNOMORESPAM@hotmail.com> wrote in message news:3mWob.28776$RG1.1588319@wagner.videotron.net... > To configure a Spartan-IIE FPGA, I use a XCF02S PROM. The configuration file > in the PROM uses 89% of the memory (this is constant on my 300k gates FPGA). > I'm wondering if it is possible to use the remaining memory of the PROM as a > way to store my own data, just like if there was a EEPROM attached to the > FPGA? I think you asked before, and didn't get any answers. Is the XCF02S an EEPROM? If so, and if you can address where you want to write, I don't see why it wouldn't work. There is probably some risk of accidentally erasing the configuration data. I believe the FPGA's stop reading when they reach the end of the configuration data, so extra data in the PROM wouldn't bother them. How about Flash memory? That would seem more designed for storing such data. -- glenArticle: 62574
You can check here http://www.fpga4fun.com/SerialInterface.html for some simple sample code on how to make a minimal serial interface. "Andrew Steer" <andrew.steerATphilips.com@dev.null> wrote in message news:3FA26B56.8A5EBF5@dev.null... > Hi, > > I'm new to this newsgroup, and also a relative FPGA newbie (though have > lots of hardware and software experince). If I should need the FAQ, > please kindly point me in the right direction. > > I would like to implement a minimal RS232 interface on my Cyclone > device. I only require TxD and RxD signals (I've got an RS232 level- > shifter IC on board). I only require a bare-bones implementation as I > need to communicate merely sufficient data to configure up to 16 8-bit > registers on my Cyclone chip. Flow-control / buffer overruns should not > be an issue. > > It would be nice to have a terminal-like behaviour from the Cyclone > (and enter commands like "R13:240" to set register 13 to value 240). A > terse (and technically simpler) command structure such as "0af8[enter]" > meaning: "set register 0x0a to 0xf8" would be perfectly adequate for > the time being. > > What is the best way to implement this function? Is there code I can > download from the website? > > I'm using the Quartus II software, and using a mixture of Graphical > (Block) Design Files and AHDL. > My present application does not require or use any Nios core. > > I see downloadable UARTs on the site, but they are far more fully- > functioned than I need, and apparently require licensing, which seems > far too complicated and involved for a one-off project. > > > Thanks for any suggestion, > > Andrew > > > SPAMTRAP: Please be sure to de-munge address if replying by email.
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