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Thanks Hong Shan Neoh 1) In DSPBuilder how can we realize below equation ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1) 2) The subsystem will be blank with input and output port only even when we link it with the VHDL code If you have any training material or examples which is helpful can you forward me to my mail ID with thanks Satish K hsneoh@netscape.net (Hong Shan Neoh) wrote in message news:<2ff2f33d.0312181432.5aa8ac63@posting.google.com>... > DSP Builder is a tool which converts Simulink model (*.MDL) to VHDL. > For conversion of MATLAB m-scripts to VHDL, you have to first > translate > the matlab code to DSP Builder blocksets in Simulink. For instance, > the 'if-else' statements can be converted to mux blocks. 'For loops' > can be > converted to counters with comparators. Variables can be just plain > registers. > > If you would like more examples of how to do this using DSP Builder, > please > send me an email at hneoh@altera.com > > You may also want to look at AccelChip's website. They have a tool > which allows you to go directly from MATLAB code to synthesizable HDL. > > Regards, > Hong Shan > hneoh@altera.com > > > satishkmys@yahoo.com (Satish K) wrote in message news:<380e8c67.0312180513.36368710@posting.google.com>... > > Dears > > > > Can anybody help me in realizing below Mathlab code to VHDL > > This is just a deceptive one, Tried in both DSPBuilder or > > SystemGenerator. > > > > If not possible by tool ,can anybody help me in hinting in Converting > > this to VHDL. > > > > Have many doubt's in DSPBuilder > > How to insert the FOR loop in DSP Builder and Variable and > > assignment's realized form it. > > Thanks in advance. > > Satish > > > > ---------mathlab code------------- > > > > % Inputs : Signal : 256 Samples, 16 bits each > > % constants Any value may be assigned to them for time being > > % XP : 256 * 16 Bits () > > % YP : 256 * 16 Bits > > % A > > % B > > % C > > % Rmin > > % Rmax > > % dR > > % D > > > > > > % Array : array 65536*16 or block RAM > > > > fftSig = fftshift(fft(fftshift(signal)),512)); > > > > for k = 1:256, > > for k2 = 1:256 > > tst =sqrt(( XP (k2)-A).^2+ (YP(k)-B)^2 +C^2); > > if (tst > Rmin & tst < Rmax-dR); > > IL = (tst ?Rmin)/dR+1; > > Ind = floor (IL); > > Q =IL-Ind; > > px = fftSig(Ind)+Q .*? > > (fftSig(Ind+1)-fftSig(Ind)); > > INDEX = k + (k2 ? 1)*256; > > ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1) > > End > > End > > end > > --------------------------------------------Article: 64176
Eric Smith wrote: > "Manfred Kraus" <makra7960@tiscali.de> writes: > >>Same situation here in Germany. I ordered Spartan-3 FPGAs in >>September. My distributor cannot tell me when I'll get them. It seems >>that Xilinx serves the "big players" first and does not care about >>small customers at all ! An "unofficial" statement from a Xilinx >>employee was "Spartan-3 is for high-volume customers only" > > > That shouldn't be a surprise, since it's the same thing that happened > with the Spartan 2. It was nearly a year between availability to > high-volume customers, and availability to everyone else. > > >>Maybe someone from Xilinx can comment this. > > > Seems unlikely that you'll get any official comment. They allocate the > limited production where it will do them the most good. I would do the > same in their position. > > If you're not going to buy in high volumes, you shouldn't try to use the > latest bleeding-edge chips. That's true of chips of any sort, not just > FPGAs. To be fair to Xilinx, I missed this: "Pricing and Availability The XC3S50, XC3S200, and XC3S400 Spartan-3 devices with 50,000, 200,000, and 400,000 system gates respectively are available for less than $6.50*. The XC3S1000 Spartan-3 device with 1 million system gates is also available for under $12.00*. The entire Spartan-3 family will be available in volume production in early 2004 from distributors worldwide, or direct from Xilinx at www.xilinx.com/spartan/." It does imply that some devices are available now, however. Perhaps they are simply not available from distributors until early next year. Leon -- Leon Heller, G1HSM Email: aqzf13@dsl.pipex.com My low-cost Philips LPC210x ARM develpment system: http://www.geocities.com/leon_heller/lpc2104.htmlArticle: 64177
Thanks for the quick answers. From what I've seen, the DA filter (with
the default P&R) spreads out across 3/4 of the chip. I need to make
this a parallel-DA filter since my clock rate is limited (I've got -5
grade devices, and taking the synthesizer's advice, clock rate should
not exceed 150 MHz.) At the same rate, MAC FIR filters use just a
small part of the chip. The MAC-FIR core, when used as a decimator,
has a quirk due to which it does not achieve full throughput (this is
documented in the datasheet), so I compensate by using a FIFO and a
DCM to raise the filter's clock rate. It seems to work fine in
simulation, but is there something I should watch out for when I go
forward with the design? As you can tell, I'm quite new to this area
:-)
-Jim
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:<mElEb.392471$Dw6.1244710@attbi_s02>...
> You should definitely use the multipliers if you are using a V2. Why burn
> up the fabric with DA logic if you have unused, fast, embedded multipliers?
> If your output sample rate is 10Msps, then you should only need 256 * 10/200
> multipliers, where 200MHz is the estimated pipeline multiplier speed. You
> will need about the same number of adders and you will accumulate over
> 200/10=20 cycles. You will need to store 20 coeffs for each multiplier,
> which you can do with LUT RAMs or with blockRAMs if you have extra. If the
> coeffs are symmetric, you can halve the number of multipliers required (if
> you are short) by adding symmetry adders in the CLB fabric.
> -Kevin
>
Article: 64178Fred H <secret@nospam.com> wrote in message news:<oprznw5mxaqlpr0e@news.mimer.no>... > Using Xilinx ISE 6.1i, FPGA Editor, it is possible to > edit different aspects of the design implementation > directly in the .ncd-file after finishing P&R. > > Say you have a huge design, that takes forever to run > P&R on, is it then possible to make small changes in > the .ncd-file, using the FPGA Editor, and then either > generate programming files or create a simulation model > of it, without running P&R first? > > The changes I'm talking about, is moving pin-locations, > moving components between slices and last but not least, > editing PULLUP/PULLDOWN on pins. I know I can do this in > the .ucf og .pcf files, but then I will definately need > to rerun P&R, and I want to avoid that. > > I trid to introduce PULLDOWN on a pin in a test design > just now, and after I did that, I generated a new Post > P&R sim model, and ran Modelsim. But nothing happened. > > Then I noticed that the file I was actually editing when > I had double clicked "View/Edit Routed Design (FPGA Editor)" > under the "Place & Route" node in Xilinx Project Navigator > was the map_<filename>.ncd file, and not the <filename>.ncd. > So I trid to open the <filename>.ncd directly from FPGA Editor, > and did the changes there. When I then generated the new > Post P&R sim model, I got this warning: > > WARNING:Anno:13 - The .ncd is out of sync (not logically equivalent) with > the > .ngm; therefore, an .nga will be created from the .ncd. > > I have tried to find out what this actually means, but I'm new > to this, so I haven't figured it out yet. Anyway, when I then > started the post P&R simulation with Modelsim, the PULLDOWN > was in effect. > > When I tried to generate programming files, I could do that wihtout > any warnings. But since I havent actually downloaded my code to an > FPGA, and meassured the voltage on the actual pin, I'm not really > sure weather my modification works or not. > > If anyone has had experience with doing this kind of modifications > without rerunning P&R, I'd like to hear about it. But any comments > are welcome :-) > > Sincerely > -Fred Hi, I am trying to add PULL up for a Pin. How can i do that in FPGA editor? Is there any scripts / how to do with GUI ? MuthuArticle: 64179
Gus Baldauf wrote: > Wilbur Harvey wrote: > >> I am getting a glibc error when tryin to install under Fedora. Does >> anyone know a way around that? > > > Have you set the environment variable "LD_ASSUME_KERNEL=2.4.1"? > > -Gus > Yes, and then it just hangs, taking about 80% of the cpu and does nothing. WilburArticle: 64180
Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote in message news:<qhr7z1bk75.fsf@ruckus.brouhaha.com>... > "Manfred Kraus" <makra7960@tiscali.de> writes: > > Same situation here in Germany. I ordered Spartan-3 FPGAs in > > September. My distributor cannot tell me when I'll get them. It seems > > that Xilinx serves the "big players" first and does not care about > > small customers at all ! this. > > Seems unlikely that you'll get any official comment. They allocate the > limited production where it will do them the most good. I would do the > same in their position. That's not entirely true. At least very small quantities (single trays) gain a lot of design wins without hurting the volume shipments to the big players. The real problem are the arrogant big distributors in europe (and xilinx as it does not understand that these distributors are a problem) I once had a case where Insight plainly lied to me about the availability of samples in munich. Munich told me, that they had none, but the Insight devisions in the Netherlands, Norway, Denmark and UK just told me "Please order in Munich, they have stock". A Xilinx representative in the UK was very helpful in convincing Insight to send me the chips, but it took him a lot of emails and phone calls. I said before that Xilinx really needs a small distributor in Europe beside the big guys Insight and Avnet. Peter Alfke said that there is hope.... Kolja SulimmaArticle: 64181
You should have a look at EasyPath for a HardCopy equivalent. It's a bit restricted in it's application but it exists. John Adair Enterpoint Ltd. Xilinx Xpert Partners This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:MF3Eb.13446$ws.1315229@news02.tsnz.net... > Rahul Khanna wrote: > > Xilinx seems to have launched a new architecture - ASMBL. There is no > > information except a news article. Can we have more info??? Is anyone > > from Xilinx Listening???? > > There was an earlier thread on this. > I did find the PDF on the Xilinx web site that was a little clearer, > as it had (virtual?) die photos. > ( Web info has gone Engineering -> Marketing -> web Publishing, whilst > the PDF has only had Engineering -> Marketing 'content removal':) > Info so far shows some good mechanical ideas for lowering the cost > of creating new die mixtures. > The Real Test will be the Volumes/NRE cost numbers, but they are > flag waving mainly at the ASIC customers, and remember Xilinx do not > have a HardCopy flow like Altera. > One aspect of the Xilinx approach, is it allows Hard IP, AND > keeps _some_ FPGA fabric - again, nice if you are big enough to > 'get the stripes you want spun' :) > -jg >Article: 64182
"Philip Freidin" <philip@fliptronics.com> escribió en el mensaje news:jnv3uv01f53q4reievis7nnnqubqtphb8v@4ax.com... > > I am sorry to say it has nothing to do with which browser you are using, > it is my lack of experience in handling web access abuse. > > Currently I am implementing some fairly draconian access controls on the site > due to my lack of experience in doing it more nicely. > What about setting a user name and a password for those IP you are blocking. I would think this would block all attacks but those directly addressed to your site. Of course, I am no expert so I may be just saying the obvious. By the way, you are blocking my IP also. :-( Best Regards Josep DuranArticle: 64183
Hi all, I'm looking at a design based on a xilinx XCR3256XL cpld. Signals come from different devices (e.g. a CPU), go through the cpld, and end on the system's expansion bus. I need to derive the timings for all the signals on this expansion bus, which depend on the timing of the signals at the CPU and on the prop. delays of the cpld. The datasheet says this device has "predictable and deterministic timing". What does this mean exactly? For example, take the pad to pad delay, which is specified to be 10 ns for the -10 part. Is this 10 ns a maximum value, or can I rely in the delay being 10 ns? e.g. take the following signal from the CPU: CE0# assert delay from rising edge of CLK: min 2 ns, typ 8 ns, max 10 ns. The CLK signal does not go through the cpld, but CE0# does. The timing report indeed says propagation delay for CE0# is 10 ns. Can I assume that CE0# at the expansion bus has min 12 ns, typ 18 ns, max 20 ns relative to the rising edge of CLK? Or are the figures specified by xilinx _maximum_ times only? Thanks.Article: 64184
Patrick MacGregor <patrickmacgregor@comcast.net> wrote in message news:u6CdnY2YoIl05X-iRVn-uw@comcast.com... > Hate to say it, but this is why I use Altera. I can get Cyclones -- today. > And their free tools support the entire family. Aye, but to be fair, how long has Cyclone been out now? Nial (with no real preference between A or X). ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 64185
You are right, I am searching for PCI-X (i.e NOT PCI express). Mark Schellhorn <mark@seawaynetworks.com> wrote in message news:<eqmEb.17753$CK3.1555241@news20.bellglobal.com>... > I'm looking at table 2-62 on p.331 of my 2VP databook that lists PCI33_3, > PCI66_3, and PCIX I/O specs. Maybe you were searching for PCI-X instead of PCIX. > > > Nahum Barnea wrote: > > Hi. > > > > I am designing PCI-X interface on Xilinx virtex2 pro with 100 MHz frequency. > > > > What IOSTANDARD should I use in the .ucf file ? > > > > I see only PCI33_3 and PCI66_3 in Xilinx litrature as "PCI" I/O's. > > > > ThankX > > NAHUMArticle: 64186
Leon Heller <aqzf13@dsl.pipex.com> wrote: : To be fair to Xilinx, I missed this: : "Pricing and Availability : The XC3S50, XC3S200, and XC3S400 Spartan-3 devices with 50,000, 200,000, : and 400,000 system gates respectively are available for less than : $6.50*. The XC3S1000 Spartan-3 device with 1 million system gates is : also available for under $12.00*. The entire Spartan-3 family will be : available in volume production in early 2004 from distributors : worldwide, or direct from Xilinx at www.xilinx.com/spartan/." : It does imply that some devices are available now, however. Perhaps they : are simply not available from distributors until early next year. That's probably marketing, that put out the note above. The most recent datasheet (http://direct.xilinx.com/bvdocs/publications/ds099-1.pdf) dated April 2003 on page 4 Product Ordering and availability still lists all devices in parenthesis, with > 3. Parentheses indicate that a given product is not yet released to > production. Contact sales for availability information. I guess if some parts would already be in general availability the technical people would feel worth the update to that datasheet. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64187
On 18 Dec 2003 18:34:10 -0800, kempaj@yahoo.com (Jesse Kempa) wrote: >John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<brtbfq$2ut$1@bunyip.cc.uq.edu.au>... >> Tom wrote: >> > Is there anybody who has experience at interfacing a WishBone IP core >> > to a CoreConnect bus. Specifically the design of a bridge ? >> >> No, but I would be very interested in such a thing! Opening up the >> whole opencores library to use with microblaze would be a great boost >> for both. >> >> Regards, >> >> John > > >An interesting aside for those using Altera products: The Avalon bus >interface and Wishbone are close enough to each other to make this >very simple. > >A while ago I studied the feasibility of this using Avalon and the >Ethernet MAC core on opencores.org. You can wire up a Wishbone slave >to Avalon in the SOPC Builder tools with a few mouse clicks. No bus >bridge required. Wishbone masters require a bit of RTL to implement >their "acknowledge" signal but other than that everything falls >together automatically. > >Jesse Kempa >Altera Corp. >jkempa at altera dot com Ok thanks for your reply but we are using a virtex pro with powerpc or microblaze. Trouble is as John said, we cannot use the free cores. So it would be nice to have a bridge. regards, TomArticle: 64188
"avalanche effect" <unexpectedvalue@yahoo.com> wrote in message news:1dcb9a53.0312161905.6c373e24@posting.google.com... > Googling web & usenet didn't provide answer or pointers - so here it > goes: > > We have a fully tested design on fat Xilinx FPGA. Must go to ASIC, > 0.18 or better. Relatively simple design, 3 clock domains, 300K gates. > The only interface is USB, so very low pin count. If the foundry > doesn't have USB phy in standard lib, we'll interface external phy. > > The question is - how long does it take - how many months ? We will > farm that out, but I need some realistic idea about time between > giving cash and working FPGA code to this outsourcing entity until we > get first chips in sample quantities. > > I fully understand that each project is different, but feel > uncomfortable with sales' quotes - I'd like to hear real experiences. > > And, BTW, are fabs busy these days or are they in mood for deals ? If you send me Your contact information in a mail, I can provide you with a contact to Atmels ULC offering. Assuming you have a good business case (enough volume), then Atmel can take your complete design + test vectors and design the ASIC. I belive that there will not be any need to go to an external design house for this. Atmel delivers many ASICs with built in USB phy so this will not be a problem. My guess is that it should take 4-6 months. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.Article: 64189
>Aye, but to be fair, how long has Cyclone been out now? But you were able to buy small quantities early... not after a year - IMHO. -- JerryArticle: 64190
Hi, I'm looking for VHDL floating point code to do 32-bit adds and multiplies to work with the ppc405 core. I've found a couple out there but have no idea as to their reliability/performance. Does anyone have any experience with this? Any sources to recommend? Thanks much Bruce --Article: 64191
guille wrote: > Hi all, > > I'm looking at a design based on a xilinx XCR3256XL cpld. Signals come > from different devices (e.g. a CPU), go through the cpld, and end on > the system's expansion bus. I need to derive the timings for all the > signals on this expansion bus, which depend on the timing of the > signals at the CPU and on the prop. delays of the cpld. > > The datasheet says this device has "predictable and deterministic > timing". What does this mean exactly? Umm, hmm, I think that may be marketing-speak for "not subject to variations in routing (wire) delay like those FPGAs". But I shouldn't say to much or I might not be invited to any of their parties ;-) > For example, take the pad to pad > delay, which is specified to be 10 ns for the -10 part. Is this 10 ns > a maximum value, Yup. See below. > or can I rely in the delay being 10 ns? > > e.g. take the following signal from the CPU: > > CE0# assert delay from rising edge of CLK: min 2 ns, typ 8 ns, max 10 > ns. > > The CLK signal does not go through the cpld, but CE0# does. The timing > report indeed says propagation delay for CE0# is 10 ns. Can I assume > that CE0# at the expansion bus has min 12 ns, typ 18 ns, max 20 ns > relative to the rising edge of CLK? Or are the figures specified by > xilinx _maximum_ times only? > > Thanks. Unless otherwise noted the times shown in the timing report or datahseet for our CPLDs would be worst-case values. That means the lowest allowable operating voltage, hottest allowable temperature, and a device built on a Friday before a holiday ;-) . Assuming that you stay within the allowable operating conditions, no device that you get from Xilinx should exhibit worse delay behavior than this, and the vast majority will be faster. Make sure that you take a look at the static timing report produced by iSE when you implement your design. It's generated from the actual implementation of your design, and is more of a final word than the datasheet. Speaking for myself and not for Xilinx, Dennis McCrohanArticle: 64192
If you look in the *_lc*x files that come with the Xilinx PCIX core, you will see they already use the PCIX standard for primitive names, i.e., IBUF_PCIX, etc. If you're planning to write your own PCIX core, don't bother. Just spend the $15k (talk them down from $18k.) That would be the equivelant of two months for two good developers. I know some developers that could do it that fast, but none of those will work for that cheap. "Nahum Barnea" <nahum_barnea@yahoo.com> wrote in message news:fc23bdfc.0312190446.77f4abf5@posting.google.com... > You are right, I am searching for PCI-X (i.e NOT PCI express). That statement really concerned me: PCIX doesn't have anything to do with PCI Express. > > Mark Schellhorn <mark@seawaynetworks.com> wrote in message news:<eqmEb.17753$CK3.1555241@news20.bellglobal.com>... > > I'm looking at table 2-62 on p.331 of my 2VP databook that lists PCI33_3, > > PCI66_3, and PCIX I/O specs. Maybe you were searching for PCI-X instead of PCIX. > > > > > > Nahum Barnea wrote: > > > Hi. > > > > > > I am designing PCI-X interface on Xilinx virtex2 pro with 100 MHz frequency. > > > > > > What IOSTANDARD should I use in the .ucf file ? > > > > > > I see only PCI33_3 and PCI66_3 in Xilinx litrature as "PCI" I/O's. > > > > > > ThankX > > > NAHUMArticle: 64193
Hi, Some additional information that may help: Virtex-E has a PCIX66_3 SelectIO mode, which is useful for PCI-X implementations at 66 MHz. It is not meant for use at 133 MHz. Virtex2 and Virtex2Pro have a PCIX SelectIO mode, which is useful for both 66 MHz PCI-X and 133 MHz PCI-X. Whichever you use, keep in mind all the I/O has to be registered in the IOBs. You will also need to use a DLL/DCM. > If you look in the *_lc*x files that come with the Xilinx > PCIX core, you will see they already use the PCIX standard > for primitive names, i.e., IBUF_PCIX, etc. We have done it this way. I am told that the "way of the future" is to just use IBUFs, etc... and use IO standard constraints in the UCF. Both work. Thanks for the plug for our PCI and PCI-X cores. I also believe if you buy this kind of IP from a reputable vendor (of which there are more than one) at sub-$20K pricing, you are saving yourself a lot of time and money. EricArticle: 64194
Ah yes, without placement, the DA filters, especially with parallel bits don't fare well with the place and route
tools. I've got a design I'm putting the finishing touches on right now that has DA filters implemented in a 2V3000-4
(stepping 0). It has 30 bit coefficients, and in some places up to 40 bits arithmetic. I have no problem getting to
to run at a 160 MHz clock in the -4 part. The areas I have had timing difficulties are in routing to-from the brams
that are used as delay queues, mostly because I was too lazy to place them and the placer does a lousy job placing
brams. Anyway, in this case, using multipliers would have required a bigger part. The multipliers in the stepping 0
devices can't be clocked at 160 MHz, plus due to the data widths I'd need to use four multiplies to complete each
multiplication. In this design, the DA approach was a clear winner.
There is a data ordering quirk with the decimating MAC filter. You have a similar quirk with a DA filter if you are
sending multiple channels thorugh the filter. Nothing a bit of ingenuity won't fix.
Jim George wrote:
> Thanks for the quick answers. From what I've seen, the DA filter (with
> the default P&R) spreads out across 3/4 of the chip. I need to make
> this a parallel-DA filter since my clock rate is limited (I've got -5
> grade devices, and taking the synthesizer's advice, clock rate should
> not exceed 150 MHz.) At the same rate, MAC FIR filters use just a
> small part of the chip. The MAC-FIR core, when used as a decimator,
> has a quirk due to which it does not achieve full throughput (this is
> documented in the datasheet), so I compensate by using a FIFO and a
> DCM to raise the filter's clock rate. It seems to work fine in
> simulation, but is there something I should watch out for when I go
> forward with the design? As you can tell, I'm quite new to this area
> :-)
> -Jim
>
> "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:<mElEb.392471$Dw6.1244710@attbi_s02>...
> > You should definitely use the multipliers if you are using a V2. Why burn
> > up the fabric with DA logic if you have unused, fast, embedded multipliers?
> > If your output sample rate is 10Msps, then you should only need 256 * 10/200
> > multipliers, where 200MHz is the estimated pipeline multiplier speed. You
> > will need about the same number of adders and you will accumulate over
> > 200/10=20 cycles. You will need to store 20 coeffs for each multiplier,
> > which you can do with LUT RAMs or with blockRAMs if you have extra. If the
> > coeffs are symmetric, you can halve the number of multipliers required (if
> > you are short) by adding symmetry adders in the CLB fabric.
> > -Kevin
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 64195Leon Heller wrote: > > Eric Smith wrote: > > > "Manfred Kraus" <makra7960@tiscali.de> writes: > > > >>Same situation here in Germany. I ordered Spartan-3 FPGAs in > >>September. My distributor cannot tell me when I'll get them. It seems > >>that Xilinx serves the "big players" first and does not care about > >>small customers at all ! An "unofficial" statement from a Xilinx > >>employee was "Spartan-3 is for high-volume customers only" > > > > > > That shouldn't be a surprise, since it's the same thing that happened > > with the Spartan 2. It was nearly a year between availability to > > high-volume customers, and availability to everyone else. > > > > > >>Maybe someone from Xilinx can comment this. > > > > > > Seems unlikely that you'll get any official comment. They allocate the > > limited production where it will do them the most good. I would do the > > same in their position. > > > > If you're not going to buy in high volumes, you shouldn't try to use the > > latest bleeding-edge chips. That's true of chips of any sort, not just > > FPGAs. > > To be fair to Xilinx, I missed this: > > "Pricing and Availability > The XC3S50, XC3S200, and XC3S400 Spartan-3 devices with 50,000, 200,000, > and 400,000 system gates respectively are available for less than > $6.50*. The XC3S1000 Spartan-3 device with 1 million system gates is > also available for under $12.00*. The entire Spartan-3 family will be > available in volume production in early 2004 from distributors > worldwide, or direct from Xilinx at www.xilinx.com/spartan/." > > It does imply that some devices are available now, however. Perhaps they > are simply not available from distributors until early next year. It is not so much a matter of them not being available, it is more a question of how you are trying to get them. You need to talk to your distributor and get them to line up a few chips for you. I have not gotten mine yet, but I have been assured that they will be coming in the next month. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 64196
jerry1111 wrote: > > >Aye, but to be fair, how long has Cyclone been out now? > > But you were able to buy small quantities early... not after > a year - IMHO. I think it is more interesting that this thread has been discussed for a full day now and no one from Xilinx has commented. Especially when one poster mentioned rumors of yield issues. I would expect Xilinx to be jumping all over that if it were just a rumor. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 64197
rickman <spamgoeshere4@yahoo.com> writes: > I think it is more interesting that this thread has been discussed for a > full day now and no one from Xilinx has commented. Especially when one > poster mentioned rumors of yield issues. I would expect Xilinx to be > jumping all over that if it were just a rumor. Of course not! Yields are one of the most carefully guarded trade secrets of semiconductor companies. The fact that a semi company doesn't talk about yields, even to dispell a rumor, does not lend any credibility to the rumor.Article: 64198
rickman wrote: > jerry1111 wrote: > >>>Aye, but to be fair, how long has Cyclone been out now? >> >>But you were able to buy small quantities early... not after >>a year - IMHO. > > > I think it is more interesting that this thread has been discussed for a > full day now and no one from Xilinx has commented. Especially when one > poster mentioned rumors of yield issues. I would expect Xilinx to be > jumping all over that if it were just a rumor. > I have had an email from someone at Xilinx; they will be available from distributors in the new year. Leon -- Leon Heller, G1HSM Email: aqzf13@dsl.pipex.com My low-cost Philips LPC210x ARM development system: http://www.geocities.com/leon_heller/lpc2104.htmlArticle: 64199
ranbow wrote: > Can you tell me which one is better,the schematic-Based design or > HDL-based design? I think starting with schematics is a good way to learn fpga hardware and how to do place and route and static timing analysis. The downside is that simulation is very tedious without an HDL. > Can you recommend the type of fpga with a built-in multiplier?And how > much it will cost? http://www.google.com/search?q=fpga+dsp+block+multiply -- Mike Treseler
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