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Messages from 63400

Article: 63400
Subject: Re: CPLD : Generating reset signal
From: arthuryang42spam@yahoo.com (Arthur)
Date: 20 Nov 2003 17:06:42 -0800
Links: << >>  << T >>  << A >>
Lower the external pulldown to something around 20k and that'll do the trick.

Article: 63401
Subject: Re: Xilinx legacy situation
From: Neil Glenn Jacobson <neil.jacobson@xilinx.com>
Date: Thu, 20 Nov 2003 17:27:11 -0800
Links: << >>  << T >>  << A >>
Tim,

iMPACT (all versions, full or WebPACK install) has supported and does 
support download via Parallel Cable III (in fact, I have one on my desk 
and it works just fine) as well as configuration of legacy devices.

Note that new design bitstreams can only be generated with the ISE 
Classics Software.



Tim Forcer wrote:
> We have some well-established teaching laboratory kit, using
> Xilinx XC4013E (optionally XC4020E for project work), with
> download by JTAG and a clone of Xilinx Parallel Cable III
> (DLC5).
> 
> As has been discussed here before, despite some statements on
> Xilinx Website, the latest (full-spec) Xilinx software includes
> an iMPACT downloader which doesn't support Parallel Cable III. 
> Alternatively, latest Webpack 6 includes an iMPACT which
> supports the download, but not any flavour of XC4000 (although
> all the library and similar files seem to be present).
> 
> Options appear to be:
> 
> 1) A kludge whereby we instal only iMPACT from Wepack 6, to get
> the downloading but with no integration into Project Navigator /
> Design Manager (so we lose revision control's updating of where
> to get the .bit file from).  (This is what we're doing at the
> moment - not brilliant, but it does work.)
> 
> 2) Someone spends time messing around to produce a collection of
> batch files which provide equivalent P&R function to Project
> Navigator.
> 
> Suggestions welcome - including suggestions for alternative
> hardware.  We need to retain 5V-compatible I/O, since all our
> kit uses 5V levels for I/O, and much of the work involves
> interfacing with other bits of kit.  We've also spent quite a
> bit of money on the XC4k ICs - total of 25 pin grid array chips,
> which were hideously expensive - and we'd like to get a decent
> return on this investment.
> 
> (In case it is considered relevant: workstations are networked
> PCs with Windows XP Pro, rest of development environment is
> ModelSim and Synplify.  Students work in pairs, 12 pairs at a
> time in a class.)
> 


Article: 63402
Subject: Re: Memory Initialization: mif, coe, hex, etc,
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 21 Nov 2003 02:02:45 -0000
Links: << >>  << T >>  << A >>
>Sure, but the functional simulator in Foundation doesn't read the coe, mif,
>or edf file.  I'm hoping to find the best possible way to allow the
>students to change their program and have those changes show up in both
>simulation and hardware.

Maybe this would be a good introduction to tools-in-real-life?

Can you kludge together something to push the info in those files
into some place/form where the simulator will see it?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 63403
Subject: graphic card accelarator vs. FPGA: which is better for the following task?
From: "walala" <mizhael@yahoo.com>
Date: Thu, 20 Nov 2003 21:49:42 -0500
Links: << >>  << T >>  << A >>
Dear all,

I guess this is a ray-tracing problem... But I need to do this task in as
high as possible speed/throughput. Here is my problem:

Suppose I am given 25 rays and I am given a 3D cube and all parameters of
these rays and cube are given...

I need to compute the length of the intersecting segment of the rays with
this cube as fast as possible. If some rays completely fall outside of the
cube, then it outputs 0, otherwise gives the length.

I heard there are some very good graphic card with accelerator... and I
heard about the bus bandwidth to be as high as 500MHz... I am not sure if
they have good accelaration function for doing my task?

I also think of doing this using an FPGA which is hooked onto a Intel PC
with Linux... I don't know the details, but I guess it uses PCI or other bus
to interact with the CPU and serve as an coprocessor...

I want to know which method is better?

Considering that after solving this throughput problem, the next bottleneck
will be a 1GB memory that I need... I wonder if the graphic card has 1GB
cache/memory inside it? Since a lot time it needs to do triple-buffling, I
guess... it should have a high speed huge memory, right?

I also don't know what is the maximum processing speed of a high-end
graphical card comparing with a high end FPGA implementation?

Can anybody give me some comments/suggestions/advice/hints/pointers on this?

Thanks a lot,

-Walalal



Article: 63404
Subject: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
From: brimdavis@aol.com (Brian Davis)
Date: 20 Nov 2003 19:07:13 -0800
Links: << >>  << T >>  << A >>
Ken wrote: 
> 
> An adder is such a simple thing and the device has specific wires
> to implement it quickly - surely there must be a way to inform the
> tools to use the carry chain in one column only for max speed?
>
 If you don't want to RLOC the primitives, perhaps the next best thing
to try is to put a syn_keep attribute on the input operand signals of
the adder; if it is in fact a logic optimization that is causing an
irregularity which breaks the carry chain placement, that will usually
put a stop to it.

 If one of the operands is a constant, that can often cause this sort of 
problem; you'll need to assign the constant to a signal having a syn_keep
rather than placing the syn_keep on the constant itself. (at least you used
to need to do that, I haven't used Synplify since last year)

 If this is a counter, also note that Synplify has some hardcoded
internal thresholds below which it will implement random logic instead
of carry chain logic, which can cause similar problems for short counters.

Brian

Article: 63405
Subject: Re: Altera Max 7000 cpld's
From: Carl <carl@nothere.com.au>
Date: Fri, 21 Nov 2003 14:21:38 +1100
Links: << >>  << T >>  << A >>
Wing Fong Wong wrote:
> Does anyone know where I can get Altera Max 7000s series cplds in 
> Australia and maybe some prototyping boards as well?
> 
Have you tried Braemac? www.braemac.com.au
At least in Melbourne they've been very helpfull with MAX3000 and 
Cyclone stuff.

	-Carl


Article: 63406
Subject: verification vs validation
From: pradeepg@vlsi1.sastra.edu (pradeep)
Date: 20 Nov 2003 19:55:27 -0800
Links: << >>  << T >>  << A >>
Hi, 

can any one give the difference between verification and validation ?

what is system level validation ?

what is emulation ?

with regards
pradeep.g

Article: 63407
Subject: Re: verification vs validation
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 21 Nov 2003 00:20:38 -0500
Links: << >>  << T >>  << A >>
pradeep wrote:
> 
> Hi,
> 
> can any one give the difference between verification and validation ?
> 
Will I get credit for doing your assignments? 

> what is system level validation ?
> 
What is homework? 

> what is emulation ?

Why can't you read your text book?


I don't normally answer posts that appear to be students asking for help
with homework (or more correctly asking others to do the work for
them).  But this is just too obvious.  

How about you read your book and write a couple of paragraphs on each of
the above questions for us to critique?  Wouldn't that be more useful to
you?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 63408
Subject: Re: Altera Max 7000 cpld's
From: Wing Fong Wong <skywings@dbzmail.com>
Date: Fri, 21 Nov 2003 06:16:41 +0000 (UTC)
Links: << >>  << T >>  << A >>
Carl <carl@nothere.com.au> wrote:
> Have you tried Braemac? www.braemac.com.au
> At least in Melbourne they've been very helpfull with MAX3000 and 
> Cyclone stuff.
> 
>        -Carl
Thanks, I'll go look it up.
-- 
Wing Wong.
Webpage: http://wing.ucc.asn.au


Article: 63409
Subject: Re: Xilinx microblaze : SRAM external mem controller
From: antti@case2000.com (Antti Lukats)
Date: 20 Nov 2003 22:27:21 -0800
Links: << >>  << T >>  << A >>
"Erik Hansen" <nospam-comp-arch-fpga@erik-hansen.de> wrote in message news:<bphv6h$1nj9oh$1@ID-207458.news.uni-berlin.de>...
> Hi Richard,
> xmd> mwr 0x0f100001 0x31 b -> writes _b_ytewise to memrory
> xmd> mrd 0x0f100000              -> read address 0x0f100000

WRONG, if you look at XMD stub you see the stub only support
32 bit read write to memory, so if you do byte read/write then
stub still reads/writes 32 and XMD emulates byte wide access!

antti

Article: 63410
Subject: Re: 400 Mb/s ADC
From: jbp@cmu.edu (Jeff Peterson)
Date: 20 Nov 2003 22:43:16 -0800
Links: << >>  << T >>  << A >>
> If you want to get some real speed, then maybe something like the Atmel
> TS8308500 (500 Mspl/s), TS8388B (1 Gspl/s) or TS83102G0B (Gspl/s) could be
> of interest.
> Going up to Giga Samples per second, would make your problem worse though
> :-)
> 
> http://www.atmel.com/dyn/products/datasheets.asp?family_id=611

I think we will try atmel...Jeff

Article: 63411
Subject: Re: 400 Mb/s ADC
From: jbp@cmu.edu (Jeff Peterson)
Date: 20 Nov 2003 22:46:12 -0800
Links: << >>  << T >>  << A >>
> The fastest slots on a PC Mainboard are the memory expansion slots.
> It's an easy to design hardware interface and if you use a server
> mainboard with multiple memory channels you get a hell lot of
> bandwidth. I remember seeing a cryptoaccelerator on a DIMM somewhere
> and SUN used to place graphics boards in memory slots.
hmmm...interesting idea

Article: 63412
Subject: Re: Xilinx microblaze : SRAM external mem controller
From: Goran Bilski <goran@xilinx.com>
Date: Fri, 21 Nov 2003 07:51:04 +0100
Links: << >>  << T >>  << A >>


True,

You have to use the HW debug logic in MicroBlaze and the opb_mdm.

This will give you true byte-write and a lot of other things.

Göran

Antti Lukats wrote:

>"Erik Hansen" <nospam-comp-arch-fpga@erik-hansen.de> wrote in message news:<bphv6h$1nj9oh$1@ID-207458.news.uni-berlin.de>...
>  
>
>>Hi Richard,
>>xmd> mwr 0x0f100001 0x31 b -> writes _b_ytewise to memrory
>>xmd> mrd 0x0f100000              -> read address 0x0f100000
>>    
>>
>
>WRONG, if you look at XMD stub you see the stub only support
>32 bit read write to memory, so if you do byte read/write then
>stub still reads/writes 32 and XMD emulates byte wide access!
>
>antti
>  
>




Article: 63413
Subject: Re: Does anyone know anything about DC-FPGA?
From: "Jay" <yuhaiwen@hotmail.com>
Date: Fri, 21 Nov 2003 15:12:27 +0800
Links: << >>  << T >>  << A >>
It's not released to public yet.
but I know It has been used and evaluated by many customers and partners of
Synopsys for a long time. (i.e. Xilinx)
It's a tool similar with DC, but targets on FPGA sythesis.
They said it's 15% better than any other products in QoR.
It shares the same flow, resource and environment with DC, which sounds
great for people who use FPGAs to do ASIC prototyping.
Though we at last choosed Synplify pro, I think it's a good tool that we can
expect.
"apple" <apolloxie@hotmail.com>
??????:6d1890bc.0311182142.483421c@posting.google.com...
> Where can i get the information about DC-FPGA?
> I've searched Synopsys website, but got nothing :(
contact their sales directly.



Article: 63414
Subject: Re: State Machines....
From: Goran Bilski <goran@xilinx.com>
Date: Fri, 21 Nov 2003 08:30:03 +0100
Links: << >>  << T >>  << A >>
No, That is another parameter.

If you look under properties in ProjNav for XST.
Under the HDL options you will find
"FSM Encoding Algorithm" where you can set to 
Auto,One-Hot,Compact,Sequential,Gray,Johnson,User,None
Two lines below you have the option
"FSL Style" which you can set to LUT or bram

This is for ISE 6. and when advanced is selected which is selected uner 
Edit -> Preferences under the tab Processes

Göran

Jim Granville wrote:

>>>Jim Granville wrote:
>>>
>>>      
>>>
>>>>It is a good idea, but the SW tool side could need work to help it take
>>>>off.. :)
>>>>        
>>>>
>"Goran Bilski" <goran@xilinx.com> wrote in message
>news:3FBD0BBD.9000306@xilinx.com...
>  
>
>>Hi,
>>
>>The latest version of XST in ISE 6.1 have an option to synthesize a
>>state machine using BRAM as a resource instead of LUTs.
>>It's called FSM_STYLE
>>    
>>
>
>You mean FSM_STYLE lets you choose between (guessing here)
>One-Hot, Binary, Gray Code, (whatever), or BRAM based ?
>
>Another solution to (complex) state engines appeared in the CR2 web seminar,
>for which
>Xilinx use the bland term (IIRC) 'Program Memory Integration' in the
>PicoBlaze.
>
>What this _actually_ does is rather more complex, and powerful.
>
> The Assembler creates a VHD file for simulation, which is run with the
>PicoBlaze
>core, to verify the design. Std soft core operation so far....
> Turns out you can recompile both files, as you NOW have a VHD description
>of the whole system (Core + ASM.VHD)  description, and the tools can
>optimise away
>redundant logic, and create a smaller/faster logic solution, that started
>life looking like
>a 'Tiny_uC and SW in small ROM', but is now whatever the tools optimise to.
>  Not just a soft uC, but a squishy one :)
>
>-jg
>
>
>  
>


Article: 63415
Subject: XC9500 design does not fit into Coolrunner
From: Klaus Falser <kfalser@IHATESPAMdurst.it>
Date: Fri, 21 Nov 2003 08:46:01 +0100
Links: << >>  << T >>  << A >>
Hello,

I have a rather large design for a XC95288XL which consumes 276 macrocells 
of 288 possible.
Since Xilinx seems to prefer Coolrunner devices to the good old XC9500's 
I tried to stuff the design into a Coolrunner II chip to look how it 
would behave.

However, I was not able to make it fit even in a 512 macrocell device.
Timing should not be so tight, it has to run at 8 MHz clock, but the 
timing analyzer gives me 17-18 MHz on the slowest 10 ns device.

Can anybody which know's the XCR2 better than me give me a hit where 
to pay attention?
How can I see from the report where the fitter has a problem?

Thanky you very much
       
-- 
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMdurst.it

Article: 63416
Subject: ERROR:Pack:1107 - ISE 6.1
From: Mastupristi <cialdi_NO_SP@AM_firenze.net>
Date: Fri, 21 Nov 2003 08:51:06 +0100
Links: << >>  << T >>  << A >>
I use Xilinx ISE webpack 6.1 sp 2, and a spartanII/e xc2s50e.

In my project I use the signals clk_in and clk_out.
The frequency of clk_out can be half of clk_in one, or can be equal to
clk_in.
clk_out is the "official" clock that goes to the rest of fpga.

Now I use clk_out = clk_in/2, and I placed clk_in in GCLK pin using
constrain.

I wrote:
clk_out <= clk2 when reset = '0' else '0';

gen_clk: process(clk_in)
begin
  if rising_edge(clk_in) then
    clk2 <= not clk2;
  end if;
end process;

(clk2 is a simple signal) in this way all works.

If I try to make clk_out equal to clk_in I obtain this error:
ERROR:Pack:1107 - Unable to combine the following symbols into a single
IOB   component:
   	PAD symbol "clk_in" (Pad Signal = clk_in)
   	BUF symbol "clk_in_IBUF" (Output Signal = clk_in_IBUF)
   Each of the following constraints specifies an illegal physical site
        for a component of type IOB:
   	Symbol "clk_in" (LOC=B8)
   Please correct the constraints accordingly.

I cannot understand....

How can I avoid this error without moving clk_in pin from GCLK?

thanks

-- 
Mastupristi?

Posted from X-Privat Free NNTP server - www.x-privat.org

Article: 63417
Subject: Re: Memory Initialization: mif, coe, hex, etc,
From: Robert Baumgartner <robert.baumgartner@ops.de>
Date: Fri, 21 Nov 2003 09:18:59 +0100
Links: << >>  << T >>  << A >>
Josh Pfrimmer wrote:

> Hi experts,
>
> I've looked through the archives, and the Xilinx literature, and haven't
> found an answer to this question, so please forgive me if it's obvious
> and/or everyone's sick of answering.  I've spent a couple of days on this.
>
> I'm upgrading a lab here at UVic from an xc4000 based board to a Spartan2.
> So as not to complicate the upgrade needlessly, we'd like to stick with
> Foundation 4.2i tools and design flow.  (We'll upgrade that next semester..
> one thing at a time.) The students are to create a pipelined 8-bit
> processor in either VHDL or Schematic.  They use the Foundation simulator
> to debug.
>
> The first issue I came up against was that they now have to use CoreGen to
> make memories (program, data, stack), where we used to use LogicBlox.
> Specifying memory contents in LogicBlox used a .mem file.  In Coregen, you
> have to use a .coe file.  Easy enough, and when I go all the way through
> implementation, I have no problems at all.
>
> When I want to do a functional simulation, however, the program memory is
> all zeroes.  How best to go about getting the .coe data into the Foundation
> functional simulator?  The VHDL and verilog files reference a .mif file.
> The simulator allows one to "load contents" via a hex file.
>
> I'd prefer a solution that only requires students to edit one file to
> change the program for both the hardware implementation (I've noticed that
> CoreGen puts the correct data in the EDIF file) AND the simulation.  It's a
> pretty challenging lab as it is, without the extra pitfall of having
> mismatching simulation/hardware programs.
>
> Thanks for your time,
>
> JP
>
> --
>                 Josh Pfrimmer, B.Eng.
> _________________________________________
>  University of Victoria, ECE
>  jpfrimmer<AT>ece<DOT>uvic<DOT>ca
> _________________________________________
> ->My views and opinions are not necessarily UVic's

Hi,

In xilinx coregen generate a .coe file with the memory editor (found in the
tool menu) with the correct depth
an width for the memory you want. This will give you a .coe and a .mif file.
Then generate your memory with
coregen. Go to the last page of the configuration (for a dual port block
memory for virtex pro it is page 4);
there you select "load init file" ,  push on the button "load file" and fill
in the name of the .coe file you
generated before. Look in the generated VHDL file, the name of the .mif file
in the VHDL file should match
the file generated by the memory editor. For the Simulation put a .mif file
with the correct content in your
simulation directory. Your Simulator should read the .mif file via textio.


Robert



Article: 63418
Subject: Re: State Machines....
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 21 Nov 2003 08:23:54 -0000
Links: << >>  << T >>  << A >>
>This "block ram as state machine" needs
>a synthesis module generator
>so that it can be inferred from code.
>
>Otherwise, I have to leave the comfortable
>confines of a VHDL clocked process and I
>have two types of source code to maintain.

But one of the reasons for putting a big state machine
in a ROM is so that you can treat it as a software problem.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 63419
Subject: Re: Xilinx legacy situation
From: Tim Forcer <tmf@ecs.soton.ac.uk>
Date: Fri, 21 Nov 2003 08:34:38 +0000
Links: << >>  << T >>  << A >>
Peter Alfke top-posted:
> 
> Tim, you have to get over the idea of still
> getting something from your old chip investment.
> Xilinx FPGAs have become 100 times (!) cheaper,
> have added functionality and better software
> support since the days when you bought the
> XC4013s.

It's not the chip investment that's the *big* hangup, but the
equipment investment.  The chips were chosen deliberately in
pin-grid-array package so we could replace as and when we wanted
- including when/if they got blown up by misuse.  Throw-away ICs
we can live with - even at the price of PGA 4013s.  Throw-away
experimental units is another ball game.

> ( Anybody who tries to hang on to a 10-year old
> computer faces a similar situation, albeit to
> a lesser extent). That's the price of progress.

Hmmm.  Doesn't explain why the majority of PC/104 processors are
486 clones rather than Pentium clones.  Doesn't explain why
8051s still sell by the truck-load.  Sure, we have to stay
current, but we've done some very useful work with 10-year-old
computers!  (Old DOS boxes make excellent targets for
introductory learning about embedded systems, provided you don't
mind the bench space they occupy.)

If it ain't broke, why fix it?  Some concepts can be taught
using kit that's a lot more than ten years old.  We have one
experiment that uses equipment which must be around 25 years
old, and part of the point is to show that important effects,
very relevant to designing the latest and greatest ICs and
systems, can be seen with basic testgear and almost rudimentary
test rigs.

If we can teach _currently relevant_ techniques of FPGA design
with ten-year-old kit (and the FPGA experimenter kits are only 3
years old), why should we have to throw the baby out with the
bathwater?  If the DESIGN software still supports XC4000E, why
has the downloader stopped supporting a download cable which was
still being sold only a couple of years ago?  If the library
files are still there, why can't the software be set up to
access them?  (After all, the guts of the software isn't the
Windows front end with the selection boxes - or have I
misunderstood all those command lines scrolling through, which
appear to show someone using 10-year-old DOS to do the hard work
rather than shiny state-of-the-art Windows?)

> Your biggest stumbling block is the 5-V
> compatibility, which stops you from using
> really modern (and cost-effective and
> sophisticated )

Look, these are STUDENTS.  Second year undergraduates.  Some of
them only got their hands on an oscilloscope for the first time
just over a year ago.  Some only SAW an oscilloscope for the
first time thirteen months ago.  They are designing simple state
machines and the like.  The prime exercise culminates in
controlling a three-storey model lift.  That could be done by a
Xilinx 1000 series device.  For the PURPOSE, we don't need
modern, we don't need sophisticated, and spending money when we
have something already is certainly not cost-effective.  We're
NOT designing for production - where we have project students
and researchers pushing boundaries, of course we use
state-of-the-art.  But at the moment we find 5V 74 series great
for teaching gates and discrete logic systems, so we have a
range of 5V I/O units which those systems can work with.  And,
to benefit both us and the students, we re-use those units. 
Students produce traffic light controllers using 74-series
logic, using a PLD, using a PIC.  They control a lift with an
FPGA and with a PC/104 system.  We're trying to turn out rounded
engineers, who understand there are options when confronted with
a requirement.  Options come with baggage.  Later in the course,
they learn of the baggage which comes with picking a 5V option. 
But up to second year, we're happy for them to swim in a
uniformly 5V digital environment.

> devices. Sooner or later you will curse the
> @#^%$*!  5-V standard.

5V has lasted longer than any other.  All subsequent standards
have been superseded - today's standard will be unusable by the
state-of-the-art ICs in three years.

If we'd gone 3.3V, would we not be cursing THAT?

> Why not do it now!

Because we teach a LOT more than just FPGA.  Believe me, we look
at the voltage issue every year.  So far, we've had insufficient
cause to decide that we'll throw out and re-cast the 21
exercises per student occupying 32 lab sessions over two years
of the course which use 5V circuitry.

-- 
Tim Forcer               tmf@ecs.soton.ac.uk
The University of Southampton, UK

The University is not responsible for my opinions

Article: 63420
Subject: Undocumented units in Virtex (I assume in Spartan-II too)
From: syemets@mail.com (Sergey Yemets)
Date: 21 Nov 2003 00:37:08 -0800
Links: << >>  << T >>  << A >>
Hi.

I have found "CAPTURE SITE" viewing Virtex die in FPGA editor.
(down-left corner of die).
The site has two inputs only (clk,cap).

I think that the "CAPTURE" belongs to JTAG functionality, but I am not
sure.
I can't find any record of the unit (at Xilinx site).

Does somebody know the goal of this unit?
(I've find explanation about similar units  "RPCILOGIC,LPCILOGIC" in
the group only).

Thanks,
Sergey.

Article: 63421
Subject: Re: XC9500 design does not fit into Coolrunner
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Fri, 21 Nov 2003 08:53:35 +0000 (UTC)
Links: << >>  << T >>  << A >>
Klaus Falser <kfalser@ihatespamdurst.it> wrote:
: Hello,

: I have a rather large design for a XC95288XL which consumes 276 macrocells 
: of 288 possible.
: Since Xilinx seems to prefer Coolrunner devices to the good old XC9500's 
: I tried to stuff the design into a Coolrunner II chip to look how it 
: would behave.

Did you play with the fitter options?

: However, I was not able to make it fit even in a 512 macrocell device.
: Timing should not be so tight, it has to run at 8 MHz clock, but the 
: timing analyzer gives me 17-18 MHz on the slowest 10 ns device.

The Macrocell of the XC2 is not as wide as the cell of the XC95X(V), so some
logic may need expansion on two cells.

: Can anybody which know's the XCR2 better than me give me a hit where 
: to pay attention?
: How can I see from the report where the fitter has a problem?

Did you look look at the *.rpt files?

Bye
-- 
Uwe Bonnes  bon@elektron.ikp.physik.tu-darmstadt.de

=======================================================

Free software means: Contribute nothing, expect nothing

=======================================================

Article: 63422
Subject: Virtex2Pro Internal Config. Access Port
From: "Silvano Bettinzana" <bettinzana@diadix.it>
Date: Fri, 21 Nov 2003 09:21:25 GMT
Links: << >>  << T >>  << A >>
Hi,

Is there somebody who has used ICAP (Internal configuration access port)
with internal PPC in Virtex2Pro ?
What are partial reconfiguration advantages versus external port
reconfiguration ? Speed ?
Could this be a step towards real time 'hardware task scheduling' ?

Regards

Silvano Bettinzana

HW Design Manager
COMPASS
Via Borsellino, 40
I-25038 ROVATO (BS)
ITALY
Phone:          +39 030 7249328
Fax:            +39 030 7249329
Mobile Phone:   +39 338 9595415
mailto:bettinzana@diadix.it






Article: 63423
Subject: Re: Xilinx legacy situation
From: "Jim Granville" <no.spam@designtools.co.nz>
Date: Fri, 21 Nov 2003 22:37:33 +1300
Links: << >>  << T >>  << A >>

"Tim Forcer" wrote
<snip many valid points>
> If we can teach _currently relevant_ techniques of FPGA design
> with ten-year-old kit (and the FPGA experimenter kits are only 3
> years old), why should we have to throw the baby out with the
> bathwater?  If the DESIGN software still supports XC4000E, why
> has the downloader stopped supporting a download cable which was
> still being sold only a couple of years ago?  If the library
> files are still there, why can't the software be set up to
> access them?  (After all, the guts of the software isn't the
> Windows front end with the selection boxes - or have I
> misunderstood all those command lines scrolling through, which
> appear to show someone using 10-year-old DOS to do the hard work
> rather than shiny state-of-the-art Windows?)

I think this reply clarified the cable issue ?
<paste>
"Neil Glenn Jacobson" <neil.jacobson@xilinx.com> wrote
> Tim,
>
> iMPACT (all versions, full or WebPACK install) has supported and does
> support download via Parallel Cable III (in fact, I have one on my desk
> and it works just fine) as well as configuration of legacy devices.
>
> Note that new design bitstreams can only be generated with the ISE
> Classics Software.
>

> > devices. Sooner or later you will curse the
> > @#^%$*!  5-V standard.
>
> 5V has lasted longer than any other.  All subsequent standards
> have been superseded - today's standard will be unusable by the
> state-of-the-art ICs in three years.

 True, and 5V will still be around for a long time - Motorola, Lattice,
Atmel
have released 5V IO's on shrink devices.
 There are signs of 5V becomming an Automotive IO standard,
for reasons very similar to Tim's LABs interconnection...

 FPGAs are a bit of a special case - they rush ahead on process, in order
to get the density and speed up, and some details get left behind.

 Still, there are signs of awareness - a Xilinx survey this week asked if
'5V IO was important in your design'.  :)

> > Why not do it now!
>
> Because we teach a LOT more than just FPGA.  Believe me, we look
> at the voltage issue every year.  So far, we've had insufficient
> cause to decide that we'll throw out and re-cast the 21
> exercises per student occupying 32 lab sessions over two years
> of the course which use 5V circuitry.

PowerMOSETS are another good argument for 5V drive ability....

-jg





Article: 63424
Subject: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
From: "Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk>
Date: Fri, 21 Nov 2003 10:12:24 -0000
Links: << >>  << T >>  << A >>
>  If you don't want to RLOC the primitives, perhaps the next best thing
> to try is to put a syn_keep attribute on the input operand signals of
> the adder; if it is in fact a logic optimization that is causing an
> irregularity which breaks the carry chain placement, that will usually
> put a stop to it.
>
>  If one of the operands is a constant, that can often cause this sort of
> problem; you'll need to assign the constant to a signal having a syn_keep
> rather than placing the syn_keep on the constant itself. (at least you
used
> to need to do that, I haven't used Synplify since last year)
>
>  If this is a counter, also note that Synplify has some hardcoded
> internal thresholds below which it will implement random logic instead
> of carry chain logic, which can cause similar problems for short counters.

Brian,

Thanks for the reply.

I have tried putting syn_keeps (and syn_preserves) on the adder in question
and then on all signals in the design - the Synplify logfile indicates no
replication/pruning has taken place but I still see Synplify reporting a
broken chain in the worst path report.

Bit annoying this.

Cheers,

Ken






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