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Messages from 63200

Article: 63200
Subject: Re: SRL16 as synchronizer
From: Hans-Juergen Dorn <hjdorn@freenet.de>
Date: Tue, 18 Nov 2003 03:11:48 +0100
Links: << >>  << T >>  << A >>
On Mon, 17 Nov 2003 23:55:06 GMT, "John_H" <johnhandwork@mail.com>
wrote:

>You might find a comment elsewhere in your timing report that fmax is
>limited by the SRL minimum pulse widths, Twph + Twpl.  The 150E-7 timing I
>had up on my screen (SpeedPrint, v6.1i timing) shows Twph of 2100 ps; Twpl
>isn't specified in the SpeedPrint output but I recall it's the same as Twph
>resulting in an SRL-limited fmax of 238 MHz with no jitter and 50.00% duty
>cycle.
>
>You might be able to get XST to avoid inferring s1 as part of the SRL by
>specifying to XST that it's an IOB register, allowing s2 and Q to be an SRL
>if XST so chooses.
>
>If Q was to be your "stable" value and s1 and s2 were metastability
>registers, why not use s2 as the stable, synchronized value?  I thought only
>two registers were needed for proper metastability protection, the output of
>s1 being a "maybe" that settles to a high or low by the time s2 grabs the
>value.
>
>
Thanks John, I have to admit that the timing analyzer output is still
mostly obscure to me. I'm doing FPGAs more on a hobbyist level 
in my spare time.

BTW. If you use s2 rather heavily, then XST might replicate it.

- Hans


Article: 63201
Subject: Re: ISE5.2 on solaris, can't use promgen
From: "Jay" <yuhaiwen@hotmail.com>
Date: Tue, 18 Nov 2003 10:21:42 +0800
Links: << >>  << T >>  << A >>
It works.
Thanks
"Petter Gustad" <newsmailcomp6@gustad.com>
??????:87islisks9.fsf@zener.home.gustad.com...
> "Alan Fitch" <alan.fitch@doulos.com> writes:
>
> > "Jay" <yuhaiwen@hotmail.com> wrote in message
> > news:bpa4cc$1lsdcn$1@ID-195883.news.uni-berlin.de...
> > > I've installed sp3, but still can't work.
> > >
> > > error info:
> > > ld.so.1: promgen: fatal: libBs_Bitstream.so: open failed: No such
> > file or
> > > directory
> > >
> > > and the file is there:
> > > ls -l /SW/xilinx/bin/sol/libBs_Bitstream.so
> > > -r-xr-xr-x   1 xilinx   sw        149088 Nov 17 16:52
> > > /SW/xilinx/bin/sol/libBs_Bitstream.so
> > >
> > > Is it a bug?
> > >
> > >
> > Check that you have
> >
> >   /SW/xilinx/bin/sol
> >
> > in your LD_LIBRARY_PATH variable,
>
> This can usually be achieved doing
>
> . /SW/xilinx/settings.sh       ; in sh compatible shells like bash, or
> source /SW/xilinx/settings.csh ; in csh compativle shells like tcsh
>
> Petter
>
> --
> A: Because it messes up the order in which people normally read text.
> Q: Why is top-posting such a bad thing?
> A: Top-posting.
> Q: What is the most annoying thing on usenet and in e-mail?



Article: 63202
Subject: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
From: "Jay" <yuhaiwen@hotmail.com>
Date: Tue, 18 Nov 2003 10:44:08 +0800
Links: << >>  << T >>  << A >>
agree.
I started to learn HDL since ISE4.1 no longer integrated Active-HDL but
provide XST.

Dan,
    you can use any 3rd party schematic capture tools, and import the edif
files as Xilinx design entry.

Jay
"Symon" <symon_brewer@hotmail.com> 写入消息新闻
:bpbs4u$1lun84$1@ID-212844.news.uni-berlin.de...
> Hi Dan,
>     Have you considered that this is maybe the opportunity you've been
> waiting for to change to a HDL?!
>         cheers, Symon.
>
> "Dan DeConinck" <pixelsmart@sympatico.ca> wrote in message
> news:Pvdub.4913$ZF1.567826@news20.bellglobal.com...
> > Hello,
> >
> > The newest Xilinx tools will not work on Win98. My Viewdraw schematic
> > capture win not work on XP so I will need to find a new schematic
capture
> > tool. I know that Xilinx has one but it is not powerful or user
friendly.
> >
> > What 3rd party schematic capture tools work with the latest Xilinx tools
?
> >
> > Thanks
> > Dan
> >
> >
> >
>
>



Article: 63203
Subject: Re: Do I need to connect all Vref in a bank together?
From: hmurray@suespammers.org (Hal Murray)
Date: Tue, 18 Nov 2003 02:52:59 -0000
Links: << >>  << T >>  << A >>
>hehe, I am using Vref as video input, trying to use the thing as AD.
>On the other input of the comparator is an r2r ladder.

Have you tried LVDS or other differential input modes?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 63204
Subject: Xilinx Design entry via Schematic Capture - What tool to use ?
From: "Dan DeConinck" <pixelsmart@sympatico.ca>
Date: Mon, 17 Nov 2003 19:15:05 -0800
Links: << >>  << T >>  << A >>
Hello,

The newest Xilinx tools will not work on Win98. My Viewdraw schematic
capture win not work on XP so I will need to find a new schematic capture
tool. I know that Xilinx has one but it is not powerful or user friendly.

What 3rd party schematic capture tools work with the latest Xilinx tools ?

Thanks
Dan




Article: 63205
Subject: Memory Initialization: mif, coe, hex, etc,
From: "Josh Pfrimmer" <yeah_spam_me@thisaddress.com>
Date: Mon, 17 Nov 2003 19:17:10 -0800
Links: << >>  << T >>  << A >>
Hi experts,

I've looked through the archives, and the Xilinx literature, and haven't
found an answer to this question, so please forgive me if it's obvious
and/or everyone's sick of answering.  I've spent a couple of days on this.

I'm upgrading a lab here at UVic from an xc4000 based board to a Spartan2.
So as not to complicate the upgrade needlessly, we'd like to stick with
Foundation 4.2i tools and design flow.  (We'll upgrade that next semester..
one thing at a time.) The students are to create a pipelined 8-bit
processor in either VHDL or Schematic.  They use the Foundation simulator
to debug.

The first issue I came up against was that they now have to use CoreGen to
make memories (program, data, stack), where we used to use LogicBlox.
Specifying memory contents in LogicBlox used a .mem file.  In Coregen, you
have to use a .coe file.  Easy enough, and when I go all the way through
implementation, I have no problems at all.

When I want to do a functional simulation, however, the program memory is
all zeroes.  How best to go about getting the .coe data into the Foundation
functional simulator?  The VHDL and verilog files reference a .mif file.
The simulator allows one to "load contents" via a hex file.

I'd prefer a solution that only requires students to edit one file to
change the program for both the hardware implementation (I've noticed that
CoreGen puts the correct data in the EDIF file) AND the simulation.  It's a
pretty challenging lab as it is, without the extra pitfall of having
mismatching simulation/hardware programs.

Thanks for your time,

JP

-- 
                Josh Pfrimmer, B.Eng.
_________________________________________
 University of Victoria, ECE
 jpfrimmer<AT>ece<DOT>uvic<DOT>ca
_________________________________________
->My views and opinions are not necessarily UVic's



Article: 63206
Subject: Re: Active-HDL 6.1 pricing
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Tue, 18 Nov 2003 14:21:07 +1100
Links: << >>  << T >>  << A >>
On Mon, 17 Nov 2003 19:27:22 -0500, rickman <spamgoeshere4@yahoo.com>
wrote:

>Have you looked at any of the open source tools?  Is that what Icarus
>is?  I am not familiar with them, but I know they exist.  

Yes, I am looking at commercial software because I am currently using
an open source tool (Icarus).

My experience is that "open source" isn't necessarily the same as
"good quality" when applied to EDA tools - both the developer and the
user communities are just too small to achieve quality comparable with
commercial EDA tools (or Linux, for that matter).

I wish that someone could prove me wrong!

Regards,
Allan.

Article: 63207
Subject: xilinx platform flash question
From: "Robert Sefton" <rsefton@abc.net>
Date: Mon, 17 Nov 2003 19:30:29 -0800
Links: << >>  << T >>  << A >>
I need to configure an XC2V6000 from flash. Planning to use six XCF04S
PROMs, but I have a few questions.

1. Anyone having problems buying these PROMs? Avnet had some in stock
last week, but today they had none. What kind of lead times should I
expect?
2. Does the Xilinx Impact software fully support in-system JTAG
programming of a chain of serial PROMs? Is ISE 5.2i sp3 the required
version?
3. Does the software also support direct JTAG downloading to the FPGA if
it sits at the end of the same JTAG chain with the PROMs in it?

I'm a little wary of committing to this path and losing time due to tool
problems or inability to get parts.

Thanks,

Robert



Article: 63208
Subject: Re: How to visit the files in CF cards
From: ramntn@yahoo.com (ram)
Date: 17 Nov 2003 21:02:22 -0800
Links: << >>  << T >>  << A >>
Using impact you have to generate system ACE file and now i learned
that only Windows 95,98,or 2000 would format the flash card right, not
windows xp.
You can go thro the impact manual at the following site to check how
to generate system ACE files.
http://toolbox.xilinx.com/docsan/xilinx5/pdf/docs/pac/pac.pdf
check chapter"using impact to generate files"
Ram_nathan


"#YU WEI#" <yuwei@pmail.ntu.edu.sg> wrote in message news:<Bhw3omFqDHA.496@exchnews1.main.ntu.edu.sg>...
> We have got a Virtex-II Multimedia Board which include CF card slot.
> 
> http://www.xilinx.com/xlnx/xebiz/board detail.jsp?=&category=-21481&i
> Lan
> guageID=1&key=HW-V2000-MLTA
> 
> How to visit the files in CF cards? Can I just copy the files to the CF
> card? Or have to build some described files to let SystemACE recognize
> the file?

Article: 63209
Subject: using multilinx from ISE to download a bit file
From: "Dan DeConinck" <pixelsmart@sympatico.ca>
Date: Mon, 17 Nov 2003 21:52:17 -0800
Links: << >>  << T >>  << A >>
I have ISE 5.2 on winXP and I have a multilinx download cable.

I am trying to download a bit file via the multilinx cable.

With earlier tools ( 3.x ) I would just start the Hardware debuuger and
select File open to import the bit file. I would then select download.

BUT

With ISE there is no hardware debugger that I can see.

I searched the HELP Index under Multilinx , Download , Hardware debugger and
came up empty.

The user interface of ISE looks organized and clean but the methodology is a
mystry to me. Just how do I get the ISE tool to import my bit file and send
it to the multilinx cable ?

Thanks Dan



Article: 63210
Subject: Re: Xilinx Design entry via Schematic Capture - What tool to use
From: JoeG <JoeG@spam.net>
Date: Tue, 18 Nov 2003 07:39:09 GMT
Links: << >>  << T >>  << A >>
Symon wrote:

> Hi Dan,
>     Have you considered that this is maybe the opportunity you've been
> waiting for to change to a HDL?!
>         cheers, Symon.
> 
> "Dan DeConinck" <pixelsmart@sympatico.ca> wrote in message
> news:Pvdub.4913$ZF1.567826@news20.bellglobal.com...
> 
>>Hello,
>>
>>The newest Xilinx tools will not work on Win98. My Viewdraw schematic
>>capture win not work on XP so I will need to find a new schematic capture
>>tool. I know that Xilinx has one but it is not powerful or user friendly.
>>
>>What 3rd party schematic capture tools work with the latest Xilinx tools ?
>>
>>Thanks
>>Dan
>>
>>
>>
> 
> 
> 


Nice try -- but HDL will not help me here --- I have XC4000 devices 
fielded -- hence I'm stuck with the XACT 5.2.1/6.0.1 tools for place and 
route -- Anyways I'm not going to migrate several gate level designs to 
HDL, as it doesn't buy me anything.


Article: 63211
Subject: Re: Xilinx Design entry via Schematic Capture - What tool to use
From: JoeG <JoeG@spam.net>
Date: Tue, 18 Nov 2003 07:40:44 GMT
Links: << >>  << T >>  << A >>
Jay wrote:

> agree.
> I started to learn HDL since ISE4.1 no longer integrated Active-HDL but
> provide XST.
> 
> Dan,
>     you can use any 3rd party schematic capture tools, and import the edif
> files as Xilinx design entry.
> 

Again this is a NO go --- EDIF file does NOT get me there as the XACT 
place & route tools only accepts XNF. I've found that Aldec, MYCAD, and 
ORcad only outputs EDIF not XNF.


Article: 63212
Subject: Re: Acek 1K - Quartus II - timing issues
From: "Manfred Balik" <e8825130@stud4.tuwien.ac.at>
Date: Tue, 18 Nov 2003 09:33:16 +0100
Links: << >>  << T >>  << A >>
It looks like you didn't use the internal Clock-Network.
Use the dedicated Clock Pins 79 or 183 (and maybe the internal PLL) to have
the same delays of clock signal to each gate.
Manfred


"Kumaran" <kumaran@trlabs.ca> schrieb im Newsbeitrag
news:40f2d3e9.0311171247.ab73d04@posting.google.com...
> Hi all,
> I am targeting my design on Acex EP1K100QC208-3 FPGA. I did most of my
> development using Leonardo Spectrum synthesizer(2002) and Max +2. My
> license for leonardo expired, and I decided to use Quartus II(v3.0).
> When I compile using Quartus, Iam getting a negative slack time for
> one of my clock. when I compiled the same FPGA code using LS and Max
> +2, I did not have any timing issues . In the compiler settings, I
> have enabled the "optimize i/o cell register placement for timing"
> option. I also tried different synthesis tool in quartus (FPGA
> express, LS,..) but I could not get the timing right. Can anyone help
> me?
>
> Thanks,
>
> Kumaran



Article: 63213
Subject: microblaze as submodule
From: "Frank" <someone@work.com>
Date: Tue, 18 Nov 2003 09:41:12 +0100
Links: << >>  << T >>  << A >>
Hi,

I'm using a design which contains a microblaze system as submodule. In the
microblaze design there are interrupt used. These interrupts are global
ports in the MHS file. What should I do with these ports in the toplevel
design? The interrupts are generated by OPB devices which exists inside the
microblaze system. So I don't need them in my toplevel design. Actually, the
question is: should the toplevel, which includes the microblaze as a
component, contain all ports specified in the MHS file?

TIA,
Frank



Article: 63214
Subject: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 18 Nov 2003 08:57:15 +0000 (UTC)
Links: << >>  << T >>  << A >>
Dan DeConinck <pixelsmart@sympatico.ca> wrote:
: Hello,

: The newest Xilinx tools will not work on Win98. My Viewdraw schematic
: capture win not work on XP so I will need to find a new schematic capture
: tool. I know that Xilinx has one but it is not powerful or user friendly.

: What 3rd party schematic capture tools work with the latest Xilinx tools ?

Have you tried?

There are reports, that 6.1 again works with win98. Best try yourself.

Bye
-- 
Uwe Bonnes  bon@elektron.ikp.physik.tu-darmstadt.de

=======================================================

Free software means: Contribute nothing, expect nothing

=======================================================

Article: 63215
Subject: Re: microblaze as submodule
From: Goran Bilski <goran@xilinx.com>
Date: Tue, 18 Nov 2003 10:22:41 +0100
Links: << >>  << T >>  << A >>
Hi,

You can specify in the .mhs file which signals you want to bring out to 
the entity of the submodule.
Only bring out signals that you use and need in the top-level.

G鰎an

Frank wrote:

>Hi,
>
>I'm using a design which contains a microblaze system as submodule. In the
>microblaze design there are interrupt used. These interrupts are global
>ports in the MHS file. What should I do with these ports in the toplevel
>design? The interrupts are generated by OPB devices which exists inside the
>microblaze system. So I don't need them in my toplevel design. Actually, the
>question is: should the toplevel, which includes the microblaze as a
>component, contain all ports specified in the MHS file?
>
>TIA,
>Frank
>
>
>  
>


Article: 63216
Subject: Re: Do I need to connect all Vref in a bank together?
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Tue, 18 Nov 2003 09:28:27 -0000
Links: << >>  << T >>  << A >>
"Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message
news:1069103320.807101@evisp-news-01.ops.asmr-01.energis-idc.net...
> hehe, I am using Vref as video input, trying to use the thing as AD.
> On the other input of the comparator is an r2r ladder.

Hi Jan,

All this discussion about how tough it is to do stuff
with Vref just gave me an idea...

How about doing the SA A/D just a little differently...
Instead of putting video on comparator Vref and DAC output
on Vin, why not ADD video+DAC (analogue summation) and
apply it to Vin, and leave Vref at a constant level?
(Yes, I realise there are some AC coupling issues to
worry about.  But you already know all about clamping
on sync tips, so that should not be too hard.)
Obviously the successive approximation will "go
the wrong way" and finally give you an inverted result,
but that's easy to deal with. And your input comparator
is always working about the same Vref so you can apply
lots of bypass caps.  Analogue addition is trivially
achieved by connecting the "tail" of the R2R ladder to
video instead of ground.  Make sure you bypass Vref to
the same ground that's used by the DAC output buffers.

Just a thought.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 63217
Subject: Re: Transforming vector position to binary value
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Tue, 18 Nov 2003 09:42:30 -0000
Links: << >>  << T >>  << A >>
I owe some folk an apology.

"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in
message news:bovsnb$6o5$1$830fa7b3@news.demon.co.uk...

> Don't be silly; if it's in a Xilinx appnote, it's _ipso facto_
> conventional :-)

When I wrote that, my intent was only to poke mild fun at
the fact that Xilinx appnotes are such a pervasive part
of the FPGA design culture that they almost *define* what's
conventional.  But I didn't write it very well, and it was
misunderstood as a slur on the quality of Xilinx material.
That would have been quite absurd and I unreservedly
apologise for any offence.

Xilinx apps people have done us all a great service over
the years by sharing a huge variety of tips and techniques
(some conventional, some highly creative).  I've had many
occasions to be grateful for that.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 63218
Subject: Re: microblaze as submodule
From: "Erik Hansen" <nospam-comp-arch-fpga@erik-hansen.de>
Date: Tue, 18 Nov 2003 11:05:42 +0100
Links: << >>  << T >>  << A >>
Hi,

> These interrupts are
> global ports in the MHS file. What should I do with these ports in the
> toplevel design? The interrupts are generated by OPB devices which
> exists inside the microblaze system. So I don't need them in my
> toplevel design.

You should be aware that the default scope setting for all ports
in XPS is 'external' although most ports are only needed 'internal'.
So when you are generating your mhs using XPS alway remember to
set them 'internal'.
i.e when you are using Projects -> Add/edit Cores to add your
components in the ports tap always remember to double click the
scope colums an set your signals internal. Sometimes it gets very
anoying when you forget to do so, as every other port usings
this signal is set back to external.
The more convinient way, of course, will be writing you
mhs by hand using an text editor. This is a bit of a struggle
in the beginning, but will your spare a lot of trouble with xps

Erik

********************************************
Erik Hansen
SHF Communication Technologies AG
edothansenatshfdotbiz
********************************************




Article: 63219
Subject: Re: using multilinx from ISE to download a bit file
From: Sean Durkin <23@iis.42.de>
Date: Tue, 18 Nov 2003 11:32:08 +0100
Links: << >>  << T >>  << A >>
Dan DeConinck wrote:
> I am trying to download a bit file via the multilinx cable.
 > [... snip ...]
> The user interface of ISE looks organized and clean but the methodology is a
> mystry to me. Just how do I get the ISE tool to import my bit file and send
> it to the multilinx cable ?
You can use iMPACT for that (Start -> Programs -> Xilinx ISE 5 -> 
Accessories -> iMPACT). It usually auto-detects any cables hooked up to 
your PC and all the FPGA and PROM devices connected to it. It then 
prompts you for the bit file(s) to program into each device.

In ISE Project Navigator, it's started when you double click on 
"Configure Devices (iMPACT)" in the "Generate Programming File" process 
on the bottom.

You can also run iMPACT in batch mode, which might be more comfortable. 
See the "iMPACT User Guide" (Xilinx ISE 5 -> Documentation -> Online 
Software Manuals Index -> iMPACT User Guide) for details.

-- 
Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33, 91058 Erlangen, Germany

mailto:23@iis.42.de
([23 , 42] <=> [durkinsn , fraunhofer])


Article: 63220
Subject: None
From: "#YU WEI#" <yuwei@pmail.ntu.edu.sg>
Date: Tue, 18 Nov 2003 19:25:04 +0800
Links: << >>  << T >>  << A >>
Thanks. I read this manual but I didn't find how to visit CF card to get =
the data there. I don't mean to generate a system ACE file which can =
boot up the FPGA. I wonder whether microblaze can get the data in CF =
card after FPGA is configured and how to prepare the data in the CF =
card. Have you met this problem?

Regards,
YUWEI

-----Original Message-----
From: ram [mailto:ramntn@yahoo.com]=20
Posted At: 2003=C4=EA11=D4=C218=C8=D5 13:16
Posted To: comp.arch.fpga
Conversation: How to visit the files in CF cards
Subject: Re: How to visit the files in CF cards

Using impact you have to generate system ACE file and now i learned
that only Windows 95,98,or 2000 would format the flash card right, not
windows xp.
You can go thro the impact manual at the following site to check how
to generate system ACE files.
http://toolbox.xilinx.com/docsan/xilinx5/pdf/docs/pac/pac.pdf
check chapter"using impact to generate files"
Ram_nathan


"#YU WEI#" <yuwei@pmail.ntu.edu.sg> wrote in message =
news:<Bhw3omFqDHA.496@exchnews1.main.ntu.edu.sg>...
> We have got a Virtex-II Multimedia Board which include CF card slot.
>=20
> http://www.xilinx.com/xlnx/xebiz/board =
detail.jsp?=3D&category=3D-21481&i
> Lan
> guageID=3D1&key=3DHW-V2000-MLTA
>=20
> How to visit the files in CF cards? Can I just copy the files to the =
CF
> card? Or have to build some described files to let SystemACE recognize
> the file?


Article: 63221
Subject: %age occupation of interconnect resources
From: Nick <nc300@imperial.ac.uk>
Date: Tue, 18 Nov 2003 12:20:36 +0000
Links: << >>  << T >>  << A >>
I was wondering how much (in percentage terms, roughly) the
interconnect resources occupy in a typical FPGA. 

Is there any paper on the subject?

Thanks



Article: 63222
Subject: Re: microblaze as submodule
From: "Frank" <someone@work.com>
Date: Tue, 18 Nov 2003 14:24:15 +0100
Links: << >>  << T >>  << A >>
I am making the MHS file by hand. Now in the MHS file I've the following:

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_IRQ_IS_LEVEL = 1
 PARAMETER C_IRQ_ACTIVE = 1
 PARAMETER C_BASEADDR = 0xFFFF8400
 PARAMETER C_HIGHADDR = 0xFFFF84FF
 PORT Irq = mblaze_irq
 PORT Intr = pci_irq & pec_irq
 BUS_INTERFACE SOPB = opb_bus
END

so pci_irq and pec_irq are local ports, but in the MSS file I've the
following:

PARAMETER INT_HANDLER = pci_isr, INT_PORT = pci_irq
PARAMETER INT_HANDLER = pec_isr, INT_PORT = pec_irq

when I try to build a netlist, I get the error:

ERROR: Intr (opb_intc) - pec_irq not previously defined!

Check the following for possible causes:

- Nowhere else in the system is pec_irq defined
- pec_irq is not identified as an interrupt signal
- Check MPD of the instance that is the source of pec_irq for
  SIGIS=INTERRUPT, EDGE=RISING/FALLING, or LEVEL=HIGH/LOW tags

Platform build failed
make: *** [implementation/bootldr.ngc] Error 1

How do I assign an interrupt handler to the local port?

Frank

"Erik Hansen" <nospam-comp-arch-fpga@erik-hansen.de> wrote in message
news:bpcqtg$1ncd1u$2@ID-207458.news.uni-berlin.de...
> Hi,
>
> > These interrupts are
> > global ports in the MHS file. What should I do with these ports in the
> > toplevel design? The interrupts are generated by OPB devices which
> > exists inside the microblaze system. So I don't need them in my
> > toplevel design.
>
> You should be aware that the default scope setting for all ports
> in XPS is 'external' although most ports are only needed 'internal'.
> So when you are generating your mhs using XPS alway remember to
> set them 'internal'.
> i.e when you are using Projects -> Add/edit Cores to add your
> components in the ports tap always remember to double click the
> scope colums an set your signals internal. Sometimes it gets very
> anoying when you forget to do so, as every other port usings
> this signal is set back to external.
> The more convinient way, of course, will be writing you
> mhs by hand using an text editor. This is a bit of a struggle
> in the beginning, but will your spare a lot of trouble with xps
>
> Erik
>
> ********************************************
> Erik Hansen
> SHF Communication Technologies AG
> edothansenatshfdotbiz
> ********************************************
>
>
>



Article: 63223
Subject: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Tue, 18 Nov 2003 13:58:02 +0000
Links: << >>  << T >>  << A >>
On Tue, 18 Nov 2003 07:39:09 GMT, JoeG <JoeG@spam.net> wrote:

>Symon wrote:
>
>> Hi Dan,
>>     Have you considered that this is maybe the opportunity you've been
>> waiting for to change to a HDL?!

>Nice try -- but HDL will not help me here --- I have XC4000 devices 
>fielded -- hence I'm stuck with the XACT 5.2.1/6.0.1 tools for place and 
>route -- Anyways I'm not going to migrate several gate level designs to 
>HDL, as it doesn't buy me anything.

Some of the "newer" tools support XC4000 ... up to 3.1 or so, I think
(but I'm not sure), and accept EDIF input. If you can find them...

- Brian

Article: 63224
Subject: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
From: jakespambox@yahoo.com (Jake Janovetz)
Date: 18 Nov 2003 07:12:34 -0800
Links: << >>  << T >>  << A >>
> What 3rd party schematic capture tools work with the latest Xilinx tools ?

Protel DXP does.  Unfortunately, it doesn't work with Win98 (I think).



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