Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMar2019

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 63625

Article: 63625
Subject: Re: 5V I/O with 1.8V Core
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 26 Nov 2003 16:13:58 -0800
Links: << >>  << T >>  << A >>
Agreed, and I am perhaps the strongest advocate of this point of view
inside Xilinx. But Sales and Marketing are always clamoring for highest
speed and lowest price.  "That's what the customers want and need"...

Peter Alfke
===================================
John Williams wrote:
> 
> Hi Peter,
> 
> Peter Alfke wrote:
> > And for most (not all!) FPGA applications, speed is king, and leakage
> > current is whatever it is.
> 
>  > This may change one day...
> 
> I certainly hope so.  There are lots of very interesting things that
> FPGAs could do in handheld consumer multimedia applications, but power
> consumption kills them in that market.  That's what PACT and Quicksilver
> are betting on...
> 
> Regards,
> 
> John

Article: 63626
Subject: Re: 5V I/O with 1.8V Core
From: "Jim Granville" <no.spam@designtools.co.nz>
Date: Thu, 27 Nov 2003 13:45:31 +1300
Links: << >>  << T >>  << A >>

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3FC541C5.D7EB206B@xilinx.com...
> Agreed, and I am perhaps the strongest advocate of this point of view
> inside Xilinx. But Sales and Marketing are always clamoring for highest
> speed and lowest price.  "That's what the customers want and need"...
:)

 Good to hear - To help that advocacy, ask them about "full compliance with
ETSI specifications"
- marketing types love that style of phrase - Volts and uA have them glazing
over ...

This summary from a recent Infineon release (smart card sector) :

"  130nm process SLE88CFX4000P : 80 KBytes of "hidden" ROM, 400 KBytes of
EEPROM/Flash,
16 KBytes of RAM, 32 Bit CPU, crypto co-processor.
 It operates at a voltage range of 1.62 to 5.5 V, in full compliance with
ETSI specifications. "

 Strikes me that getting a 130nm device to operate 1.65-5.5V is not trivial,
but it must
have been important enough for them to make the effort.

 Besides the process/ETSI tag point, this device would make a good secure
FPGA
Bootloader, if  Infineon decided to package for that market.

-jg



Article: 63627
Subject: Xilinx ISE 6.1 external editor
From: Gavin Melville <gavin.melville@acclipse.co.nz>
Date: Thu, 27 Nov 2003 14:24:08 +1300
Links: << >>  << T >>  << A >>
Hi,

Has anyone actually got ISE to use CodeWright as the external editor
-- I have the path correct, but CW32.EXE is called from _pn.exe and it
seems that there is a space on the end of cw32.exe in _pn.exe.
Regardless it doesn't call that exe.

TIA,


--
Regards,
Gavin Melville
gavin.melville@acclipse.co.nz

Article: 63628
Subject: Phy IP for Giga ethernet for Virtex -II Pro
From: anupr@ieee.org (Anup Raghavan)
Date: 26 Nov 2003 17:28:08 -0800
Links: << >>  << T >>  << A >>
Hello, I need to find out the options I have to implement a PHY for
giga-ethernet on a Virtex II pro. I want to be able to use different
types of interfaces like GMII, RGMII, MII, TBI

Can anyone help me out on this?
Thanks
Anup

Article: 63629
Subject: Re: XC9500 design does not fit into Coolrunner
From: "Robert Sefton" <rsefton@abc.net>
Date: Wed, 26 Nov 2003 18:05:52 -0800
Links: << >>  << T >>  << A >>
"Klaus Falser" <kfalser@IHATESPAMdurst.it> wrote in message
news:MPG.1a2d2836d298358b9896a0@151.99.250.3...
> >
> > Did you look look at the *.rpt files?
>
> Sure I did. It is, however, at least a little bit difficult to scan
250 equations
> to look for some anomaly. And I have got no idea how such an anomaly
should look
> like.
>

Klaus -

A couple of things you might try:

1. Compare the XC9500 reports to the CoolRunner reports.
2. Compile parts of the design by themselves, first to XC9500 then to
CoolRunner. See which modules blow up in the CoolRunner.

Robert



Article: 63630
Subject: Re: Xilinx ISE 6.1 external editor
From: "Peng Cong" <pc_dragon@sohu.com>
Date: Thu, 27 Nov 2003 10:13:07 +0800
Links: << >>  << T >>  << A >>
I'm using UlreaEdit, it's fine

"Gavin Melville" <gavin.melville@acclipse.co.nz> 写入消息新闻
:pdkasvgep468oj99sllpa7d2pmvt95arfa@4ax.com...
> Hi,
>
> Has anyone actually got ISE to use CodeWright as the external editor
> -- I have the path correct, but CW32.EXE is called from _pn.exe and it
> seems that there is a space on the end of cw32.exe in _pn.exe.
> Regardless it doesn't call that exe.
>
> TIA,
>
>
> --
> Regards,
> Gavin Melville
> gavin.melville@acclipse.co.nz



Article: 63631
Subject: overshoot problem of EPM7128S
From: "Jian Ju" <jianju.ee@polyu.edu.hk>
Date: Thu, 27 Nov 2003 11:25:49 +0800
Links: << >>  << T >>  << A >>
Hi,

I have a project where one of the output signals is a short pulse with a
width of 100ns and repeat frequency of 1MHz. The main clock in my design is
20MHz. After I download the program to the chip (EPM7128SLC-7) severe
overshoots (over 2V @VCC=5V)can be observed. Does anybody know an answer to
this problem? Thank you.

--
Regards,
Jian



Article: 63632
Subject: PCI LogiCORE with ISE 5.2
From: "Dean Armstrong" <daa1@NOSPAMcs.waikato.ac.nz>
Date: Wed, 26 Nov 2003 19:46:37 -0800
Links: << >>  << T >>  << A >>
Hi All, 
I am trying to synthesise the Xilinx example "ping" PCI LogiCORE using 
Synplify Pro 7.0 and Xilinx ISE 5.2. 

I operate Synplify as detailed in the LogiCORE PCI Implementation Guide, 
and then start the ISE Project Navigator to implement the design. ISE fails 
at the translate stage with the output shown at the bottom of this post. 

I am unclear as to where the error is in this process. The second launcher 
message about PCI_LC_I.ngo seems a bit suspect, but does not seem to be an error. 

I would appreciate any help that anyone could give me on getting past this. 
I'm more than a little bit puzzled after playing with all the options I can 
find to no avail. 

Regards, 
Dean Armstrong. 

Started process "Translate". 

Command Line: ngdbuild -quiet -dd 
e:\working\wireless\vhdl\pci\ping\synthesis/_ngo -uc 
E:/working/wireless/vhdl/pci/xc2s100fg456_32_33.ucf -sd 
E:\working\wireless\vhdl\pci\vhdl\src\xpci -p xc2s100-fg456-6 pcim_top.edf 
pcim_top.ngd 

Launcher: "pcim_top.ngo" is up to date. 
Reading NGO file "e:/working/wireless/vhdl/pci/ping/synthesis/_ngo/pcim_top.ngo" 
... 
Reading component libraries for design expansion... 
Launcher: The source netlist for "PCI_LC_I.ngo" was not found; the current NGO 
file will be used and no new NGO description will be compiled. This probably 
means that the source netlist was moved or deleted. 

abnormal program termination 
ERROR: NGDBUILD failed 
Reason: 

Completed process "Translate". 




Article: 63633
Subject: Re: How many dedicated clock pins EP20K1500EBC652 device?
From: vbetz@altera.com (Vaughn Betz)
Date: 26 Nov 2003 19:54:15 -0800
Links: << >>  << T >>  << A >>
enq_semi@yahoo.com (enq_semi) wrote in message news:<cd4a30b8.0311260745.35013640@posting.google.com>...
> Hi, Vaughn,
> 
> > 
> > Their skew should be much better than that.  Try the experiment above
> > to make sure you are really using the Fast networks.
> > 
> 
> I made sure it should use the Fast networks:
> 
> 1. In assignment manager I have the following settings:
>    -- aclk_in  => Clock Settings = my_clk @ 56MHz
>    -- aclk_in  => Global Signal = Global Clock
>    -- aclk_in  => Auto Global Clock = On

Should really use 
aclk_in => Global Signal = On 

for APEX.

Global clock etc. are really for Stratix where there are multiple
types of globals; from the message below, it looks like they do not
get interpreted as "Global signal = on" for APEX.

> 2. During compile, I saw this message:
>    --Info: Promoted cell aclk_in to global signal automatically

Yup, looks like Quartus automatically promoted it to use global
routing.  If it had recognized your global signal assignment, this
should have been done by your constraints though, and wouldn't require
the automatic global processing.  Just FYI; the end effect is fine.

> I doubted that the timing parameters used by Quartus might not be
> accurate, however, I verified two skews on oscilloscope against the
> timing report by Quartus, the difference is very small (around 0.2 ns
> or so).
> 
> I also tried non-clock and non-fast I/O pin, the skew is much larger.
> So, maybe the 1ns skew with fast I/O pin is considered "useable as
> clock"? (I certainly NOT hope so.)

Hmmm ... I guess the 1 ns skew is correct then.  The Fast networks in
APEX do have higher skew than the dedicated clock networks, so they do
hurt performance a bit.  They still certainly do work as clocks with
no hold violations, since many designs use them that way -- the 1 ns
skew must be between cells that are separated by enough distance that
they have to use enough routing that the data delay is comfortably
above the clock skew.

Vaughn

Article: 63634
Subject: Xilinx FPGA Clock Skew
From: muthu_nano@yahoo.co.in (Muthu)
Date: 26 Nov 2003 20:09:31 -0800
Links: << >>  << T >>  << A >>
Hi,

In FPGA we can't control over the clock skew since it is
being routed via dedicated lines.

When i am looking in to the timing reports, Some times i am getting
the Clock Skew value as 0.102ns.. ie., in Positive

And some times, -0.123 ie., in Negative.

Actually,How the timing report tells the clock skew?

How it is being measured?

Regards,
Muthu

Article: 63635
Subject: Re: Affordable Development Board
From: vbetz@altera.com (Vaughn Betz)
Date: 26 Nov 2003 20:10:53 -0800
Links: << >>  << T >>  << A >>
Hi Nadeem,

The Altera University Program will set you up with a 10K70 based
board, Quartus Web Edition & the download cable etc. for $149 US.  It
includes MaxPlusII as well, but you'll be better off learning Altera's
latest CAD system, Quartus, instead.  See
http://www.altera.com/education/univ/kits/unv-kits.html

You can also get more expensive boards from 
http://www.altera.com/products/devkits/kit-dev_platforms.jsp
The $395 Cyclone C20 and $495 Stratix S10 based boards aren't too
expensive, but have reasonable sized FPGAs on them.

Vaughn

> Jean
> 
> "Nadeem Douba" <ndouba@connectmail.carleton.ca> wrote in message
> news:bpn68h$1nh$1@driftwood.ccs.carleton.ca...
> > Hi everybody,
> >
> > I was wondering if anyone knew where I could get my hands on a cheap fpga
> > development board... I'm a university student at Carleton U. in Ottawa so
>  I
> > can't afford anything to fancy (tuition fees drained my pocket).
>  Anyways...
> > if anyone can direct me to someone or some merchant I would greatly
> > appreciate it.
> >
> > Thanks
> >
> > Nadeem

Article: 63636
Subject: Re: what is the fastest speed that FPGA deals with CPU?
From: muthu_nano@yahoo.co.in (Muthu)
Date: 26 Nov 2003 20:12:58 -0800
Links: << >>  << T >>  << A >>
Hi,

I am working with PCI-X Interface, which is 64bits wide and 133Mhz.

But I have some problem in getting this much frequency in Xilinx FPGA?

Regards,
Muthu


"walala" <mizhael@yahoo.com> wrote in message news:<bq3avb$nt9$1@mozo.cc.purdue.edu>...
> "Kolja Sulimma" <news@sulimma.de> wrote in message
> news:b890a7a.0311261359.2e99abde@posting.google.com...
> > "walala" <mizhael@yahoo.com> wrote in message
>  news:<bq0jie$kv2$1@mozo.cc.purdue.edu>...
> > > Dear all,
> > >
> > > Is PCI the only convinient interfacing unit that talks with CPU by
>  inserting
> > > something into a computer conviniently? What is the speed of that? Is
>  there
> > > any faster method?
> > PCI is the only relatively fast interface that is available on almost
> > any computer for internal extensions and has good operating system
> > support for hardware drivers. The usual 32-Bit, 33MHz PCI can provide
> > 133MB/s in theory of which about 90MByte/s are usable without to much
> > effort for writes, considerably less for reads. There are also 66MHz
> > and/or 64-Bit variants available on more expensive mainboards.
> >
> > But there are lots of alternatives.
> > There are faster "PCI-like" interfaces like AGP, PCI-X, PCI-Express
> > (only possible with some FPGAs).
> > You can also connect your hardware via ATA or SCSI busses. That's
> > about the speed of PCI. For data aquisition tasks you can make your
> > hardware look like a tape drive so that you do not need to write a
> > driver and readout software. Just use the tar command for that.
> >
> > Probably the fastest interface inside a PC is a memory slot. But
> > getting OS support for your device in this case is not straight
> > forward. But there are a couple of GByte/s available there.
> >
> > And then you can use all the external interfaces: FireWire, USB,
> > Ethernet, ...
> >
> > Kolja Sulimma
> 
> Hi, Kolja,
> 
> Thanks a lot for your help!
> 
> Can you compare in a little more detail of those internal or external
> interfaces?
> 
> For example, USB vs. PCI? Or PCI-X vs. FireWire?
> 
> I guess USB is not as fast as PCI, right?
> 
> Thanks a lot,
> 
> -Walala

Article: 63637
Subject: Re: Input pins without Vcco supply-- Virtex-II
From: "Jay" <yuhaiwen@hotmail.com>
Date: Thu, 27 Nov 2003 12:14:24 +0800
Links: << >>  << T >>  << A >>
Austin,

Thanks your answer. It sounds good!
That means we can use IO pins as power supply instead of Vcco.

"Austin Lesea" <austin@xilinx.com>
??????:bq2hma$ha33@cliff.xsj.xilinx.com...
> Jay,
>
> By using the banks that are unpowered as inputs, you are in effect
> powering up the bankl by reverse biasing the protection structures
> (diodes) that are part of the pmos output transistor stack (basically,
> there is no separate diode, it is the junction of the pmos transistor
> itself).
>
> That said, the bank requires ~ 2mA to power on (as long as it doesn't
> have to drive anything) so a bunch of inputs toggling effectively powers
> up the bank....
>
> Doesn't hurt anything at all.  Can't say that we meet all specifications
> for timing, etc. but you are certainly able to function.
>
> In fact, the clock inputs are no different than any others, so you are
> powering up the bank from those alone.
>
> If you really want to power up the bank for test reasons, I would
> program an output to be a "1" with the PCI IO standard (one of the
> strongest) and themn connect that pin to 3.3V.  That is good for ~ 60 mA
> of IO current without concern.  Need more outputs?  Parallel up a bunch
> of IOs as "1" to 3.3V.
>
>
> Austin
>
> Jay wrote:
>
> > Hi all,
> > The factory have made some mistakes when they had our V-II pcb board
> > manufactured and assembled. and we found only the Vccint, Vccaux and
Vcco4
> > is available for the FPGAs.
> > To save time, we still want to do some debugging on this board before we
can
> > get our new board.
> > Thanks god that with these 3 Vcc supplies we can download our design
through
> > JTAG, and later I found input signals of other banks without Vcco still
can
> > be used.(at least the GCLK, I've not tried other pins yet).
> > so my question is: can anyone confirm that I really can use the input
pins
> > without Vcco. and how about its Electrical Characteristics, ?V tolerant
etc.
> >
> >
>



Article: 63638
Subject: Re: Reverse engineering an EDIF file?
From: muthu_nano@yahoo.co.in (Muthu)
Date: 26 Nov 2003 20:19:37 -0800
Links: << >>  << T >>  << A >>
Hi,

I think you have got enough ideas for this issue.

I want to learn, how can i set time limit for a core. As you said, how
can i make my .edf to work fine for limited period of time?

Can you help me on this?

Regards,
Muthu

Rastislav Struharik <rasti@eunet.yu> wrote in message news:<6o20rv4dvcb461rkatu5tuodam5sma06u4@4ax.com>...
> Hello,
> 
> I would like to know does anyone knows, is it possible to reverse
> engineer an edif netlist file? I am currently developing an FPGA core.
> I would like to supply an evaluation version of the core, that would
> have all the functionality of the final core, but would operate only
> for a limited period of time. My fear is that there is a way to modify
> the evaluation version edif netlist (find and remove modules that set
> a time limit to the operation of the evaluation version), and thus
> obtain completely functional core. Can something like this be done, or
> am I being paranoid?
> Every help and clarification on this subject is most welcome.
> 
> Thanks in advance,
> Rastislav Struharik

Article: 63639
Subject: Re: Infer DDR registers from RTL?
From: praveen@cg-coreel.com (praveen)
Date: 26 Nov 2003 20:43:03 -0800
Links: << >>  << T >>  << A >>
anil, 
can i know which is your target device.
as per my knowledge dual edge triggered flip flop is supported only in
Cool Runner - II.

"Anil Khanna" <anil_khanna@mentor.com> wrote in message news:<3fa97de8$1@solnews.wv.mentorg.com>...
> Hi all,
> 
> Does anyone know the right steps to make ISE infer DDR registers from a RTL
> code? I am following the template that ISE suggests in their answer record
> #15776. Apart from this, I also make sure to set the IOB option during MAP.
> I still cannot see the dual-data rate flops being used in the map report.
> 
> However, when I open FPGA editor, I can see that my two flops were mapped to
> registers that are placed in the same IOB. How do I know for a fact that the
> IFDDRSE (or a corresponding) primitive is actually being used?
> 
> Thanks
> 
> Anil

Article: 63640
Subject: Re: Slightly unmatched UART frequencies
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Thu, 27 Nov 2003 05:44:51 GMT
Links: << >>  << T >>  << A >>
Hi all,



I've posted some code to do a UART last week on the fpga4fun site...

http://www.fpga4fun.com/SerialInterface.html



For the receiver, the bits are sampled in the middle - with the sampling
point configurable.

Also, the receiver starts checking for a "start" as soon as the "stop"
mid-point bit is detected, so that should be consistent with the
recommendations posted earlier.

Jean



"valentin tihomirov" <valentinNOMORESPAM@abelectron.com> wrote in message
news:bpum8f$1srj32$1@ID-212430.news.uni-berlin.de...
> UART is used to transfer a byte in serial form bit-by-bit. I know that 10%
> deriviations in frequencies of transmitter and receiver are permissible. I
> was learnt that UARTs synchronyze at the falling edge (1to0) of start bit;
> hence, there should allow for transfer of a stream of bytes of arbitrary
> length.
>
> I have developed a simple UART. It's receiver and transimtter run at 9600
> bps with 16x oversampling. Both receiver and transmitter have 1-byte
buffer.
> To test the design I've created an echo device; it merely mirrors all the
> bytes sent to it back to the sender. It works fine with one of COM ports
on
> my PC. Another COM port has its crystal running at a bit faster
fundamental
> frequency. This causes a problem when it sends a long stream of bytes to
my
> UART. In fact, sender and recepient cannot synchronize at falling edge of
> start bit because one of them is slower and is processing a previous byte
> wrile sender proceeds to next byte transmitting start bit. Despite of the
> fact, my receiver still works fine beacuse it is ready to receive next
byte
> right after a first half of stop bit is received. Just to clarify,
receiver
> acquares values from serial input at the middle of each data bit slice; it
> reports BYTE_READY in the middle of stop bit and from this moment is ready
> to accept next byte, i.e. ready fror synchronization. Therefore, if data
is
> coming slightly faster and falling edge of start bit is located within
stop
> bit (according to my UART's clock) receiver is still capable not to
overlook
> the data.
> On the other hand, transmitter should transmit all 10 bits (start + 8 data
+
> stop) @ 9600 bps. Consider for instance an UART forwarder or an echo
device.
> If data is coming faster than I forward it I get a buffer overrun
> ultimately. That is, receiver is ready with a byte in its buffer to be
> copied into transmitter to forward but slow transmitter is still shifting
> data out and its buffer is blocked.
> I have a "fast" solution for my UART echo device; if transmitter has
> transmitted > half of stop bit and sences that there is a next byte
received
> it stops sending current stop bit and starts transmitting a start bit for
> next byte. Untimely ceasing transmission is not good solution because
> transmitter may be connected to a good matched or slightly slower running
> UART. Design may be not a forwarder thus data provider may differ from
9600
> bps receiver. In this case, starting early transmission of next byte while
> remote peer is still receiving stop bit causes stop bit error.
>
> What is interesting in this situation is the fact I can build a good echo
> device from any industrial manufactured UART (I've used standalone 16c750
> and ones built into i8051). They never have a buffer overrun issue despite
> sending port is slightly faster than receiving (like sending data from my
> fast COM port to slow one). Note, no flow control is used, buffers are
> always 1-byte long. Which trick do they use? Again, 10% frequency
> dereviations between sender and receiver are considered permittable and no
> flow control is not required since sender and receiver both run at formal
> 9600bps.
>
> I feel this should be a well-known problem (solution) and just wonder why
I
> did not encounter this consideration before.
>
> Thanks.
>
>
>



Article: 63641
Subject: DDFS technique problem in generating a few clocks
From: praveen@cg-coreel.com (praveen)
Date: 26 Nov 2003 22:49:09 -0800
Links: << >>  << T >>  << A >>
hi peter,

I went through one of the application note(xl31_32.pdf) of xilinx on
DDFS.
he gives the eq Fout=Fclk * N/2 power k.Is there any effective method
of selecting the value of N and k or is it trial and error.

Thanks in advance.

rgds,
praveen

For ex if my Fclk= 98 MHZ and  Fout =21.24 MhzPeter Alfke <peter@xilinx.com> wrote in message news:<3FA16B91.6436E4E4@xilinx.com>...
> Here is a simple suggestion:
> Your output frequency divided by your accumulator clock frequency is
> 0.0074327256  as displayed on my cheap calculator.
> Just convert this decimal value into a binary fraction, and that gives
> you the inputs to your accumulator. You can make the accumulator more
> than 20 bits long to increase the average frequency accuracy, but you
> will still get a jitter of one ~73 MHz clock period, which is roughly
> 0.7% of your output period.
> If you absolutely need less jitter, there are tricks (like multiple
> accumulators), but they get complicated and/or expensive.
> 
> Good luck.
> Peter Alfke
> ===========================
> 
> Atif wrote:
> > 
> > Hello all,
> > I am generating the clock of frequency 548KHz from an input clock of
> > 73.728MHz. I am using the Direct digital frequency synthesis DDFS
> > technique from
> > www.xilinx.com/xcell/xl31/xl31_32.pdf
> > But I am getting the wrong output as;
> > *************************************************
> > Running...
> >                  929 929.134     t=0.000000
> > 929.134period=929.134000
> > 929.134t=929.134000
> > freq=1076271.022264 HZ
> >                 2747 2746.71     t=929.134000
> > 2746.71period=1817.576000
> > 2746.71t=2746.710000
> > freq=550183.321083 HZ
> >                 4578 4577.85     t=2746.710000
> > 4577.85period=1831.140000
> > 4577.85t=4577.850000
> > freq=546107.889075 HZ
> > Exiting VeriLogger Pro at simulation time 10000000
> > 0 Errors, 0 Warnings
> > Compile time = 0.00000, Load time = 0.04700, Execution time = 0.04700
> > 
> > Normal exit
> > ***********************************************************************
> > Here is the code of my program:
> > ***********************************************************************
> > // Thanks to Jonathan Bromley for his valuable suggestions for the
> > code.
> > `timescale 1ns/1ps
> > module fulladd28(out,clock,reset);
> >    parameter a=28'd1995207;
> >    parameter w = 28; // bit width of phase accumulator
> >    output out;
> >    input clock, reset;
> >    reg [w-1:0] sum;
> >    always @(posedge clock or posedge reset)
> >          if(reset)
> >                sum <= 0;
> >            else
> >               sum <= sum+a;
> >    assign out = sum[w-1];
> > endmodule       //end of module fulladd28
> > module stimulus;
> >    wire OUT;
> >    reg CLOCK, RESET;
> >    fulladd28 myfulladd28(OUT, CLOCK, RESET);
> >    always@(posedge OUT)
> >       begin
> >          :freqmeter
> >          real t, period;
> >          period=$realtime - t;
> >          $display($time, " ", $realtime, "\t t=%f ",t);
> >          $display($realtime, "period=%f ",period);
> >          t=$realtime;
> >          $display($realtime, "t=%f ",t);
> >          $display("freq=%f HZ", 1000000000/period);
> >       end
> >    initial
> >       begin
> >          RESET=1'b1;
> >          #10 RESET=1'b0;
> >       end
> >    initial
> >       begin
> >          CLOCK=1'b0;
> >          forever #6.782 CLOCK=~CLOCK;
> >       end
> >    initial
> >       begin
> >          #10000 $finish;
> >       end
> > endmodule //end of module stimulus
> > ***********************************************************************
> > 
> > Can anyone please guide me why is this deviation from the desired
> > frequency and how to remove this? Is there any other accurate method
> > of generating the desired frequency from the input one?
> > I want the accuracy of 20ppm. The device to be used is
> > Xc2s50-5PQ208-I.
> > 
> > Thanks and Regards
> > Atif Nadeem
> > Research Associate

Article: 63642
Subject: Re: DDFS technique problem in generating a few clocks
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Thu, 27 Nov 2003 18:17:39 +1100
Links: << >>  << T >>  << A >>
On 26 Nov 2003 22:49:09 -0800, praveen@cg-coreel.com (praveen) wrote:

>hi peter,
>
>I went through one of the application note(xl31_32.pdf) of xilinx on
>DDFS.
>he gives the eq Fout=Fclk * N/2 power k.Is there any effective method
>of selecting the value of N and k or is it trial and error.
>
>Thanks in advance.
>
>rgds,
>praveen

You can determine k from the required frequency accuracy, as the
output frequency is quantized in steps of Fclk / 2^k

E.g.  Fclk is 73.728 MHz, k of 20 bits gives a step size of 70.3125Hz.

N determines the output frequency, as above.

Using some primary school algebra, we can work out an expression for
the ideal value of N as:

Nideal = (Fout / Fclk) * 2^k

now round Nideal to an integer to give N.

E.g.  Fclk is 73.728 MHz, Fout is 548kHz


k	N	Error

18	1948	-228.1ppm
19	3897	+28.5ppm
20	7794	+28.5ppm
21	15588	+28.5ppm
22	31175	-3.6ppm
23	62350	-3.6ppm
24	124700	-3.6ppm
25	249401	+0.4ppm
26	498802	+0.4ppm
27	997604	+0.4ppm
28	1995207	-0.06ppm
...

Regards,
Allan.

Article: 63643
Subject: Re: overshoot problem of EPM7128S
From: "Krzysztof Szczepanski" <kszczepa@poczta.wp.pl>
Date: Thu, 27 Nov 2003 08:38:24 +0100
Links: << >>  << T >>  << A >>

Uzytkownik "Jian Ju" <jianju.ee@polyu.edu.hk> napisal w wiadomosci
news:1069903547.946685@hkpu01...
> Hi,
>
> I have a project where one of the output signals is a short pulse with a
> width of 100ns and repeat frequency of 1MHz. The main clock in my design
is
> 20MHz. After I download the program to the chip (EPM7128SLC-7) severe
> overshoots (over 2V @VCC=5V)can be observed. Does anybody know an answer
to
> this problem?

A serial inductance at the power path can do the overshoots or a switching
power supply generates pulses of voltage at times where large current
changes are observed (shortcut to ground or VCC at output pin).

Regards,
krzysiek




Article: 63644
Subject: Re: Slightly unmatched UART frequencies
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 27 Nov 2003 08:16:52 GMT
Links: << >>  << T >>  << A >>
Jean Nicolle wrote:

> I've posted some code to do a UART last week on the fpga4fun site...

> http://www.fpga4fun.com/SerialInterface.html

> For the receiver, the bits are sampled in the middle - with the sampling
> point configurable.

> Also, the receiver starts checking for a "start" as soon as the "stop"
> mid-point bit is detected, so that should be consistent with the
> recommendations posted earlier.

I finally found from another post that the OP was trying to build a loop 
back device that would send back everything it received.  Since it is 
possible to receive a character in (about) 9.5 bit times, but it takes 
10 to send it, (8N1), an unbuffered device could quickly lose data.

It seems that this is not one of the cases the protocol was designed to 
handle.    As far as I know, the popular full duplex with remote echo 
would not have been considered when the protocols were defined.

Also, as far as I know both the popular XON/XOFF and RTS/CTS flow 
control are relatively recent inventions.  RTS/CTS is from the real half 
duplex days, where only one side could transmit at a time.

Part of the asynchronous protocol is that both ends have their own clock.

For T1 and related protocols, one end synchronizes its clock to the 
other, so that there is no speed matching problem.

For ethernet, the receiver synchronizes to the transmitter from clock 
information in the data stream.

It should be possible to build a device with a UART and PLL to 
synchronize the transmit clock to the incoming data rate.  There should 
probably be some buffer to last until the PLL locks.

-- glen


Article: 63645
Subject: Re: area constraints
From: nospampleeeeze@yahoo.com (A.y)
Date: 27 Nov 2003 00:46:40 -0800
Links: << >>  << T >>  << A >>
thanks all for clearing my doubt.. 
in fact my design is consuming 99% slices (69% FFs and 67%LUT ) (is
this figure/ratio normal ?)
.. in xc2v3k it's having 5-6 heirarchy levels .. and i am in dilemma
how to go about
floorplanning this design .. i don't know if i shud make rpms of each
module from the bottom ?
make everything rpm or keep some modules as rpm and make area groups
for higher levels ?
experimenting all things cud take a long time .. that's why a want to
have some advice
from the expert .. 
in one line what is the general procedure to extract the best
performance(important)
as well as runtime from the tool in case of high density designs ?

regards
ay

Article: 63646
Subject: Re: what is the fastest speed that FPGA deals with CPU?
From: news@sulimma.de (Kolja Sulimma)
Date: 27 Nov 2003 01:11:47 -0800
Links: << >>  << T >>  << A >>
> Can you compare in a little more detail of those internal or external
> interfaces?
> 
> For example, USB vs. PCI? Or PCI-X vs. FireWire?
> 
> I guess USB is not as fast as PCI, right?

This is a little bit OT for this group, but anyway:
All this depends on your application, the interfaces have various
strengths and weeknesses in areas like latency, streaming read/write,
single reads/writes and so  on. Also, utilisation of the bandwidth
tends to become worse for the faster interfaces.
But very roughly 
USB2.0, FireWire four times as fast as 100Mb Ethernet
PCI, U160-SCSI, Fibre Channel, Gb-Ethernet are twice as fast as
USB2.0/FireWire
PCI32-66MHz, PCI64-33MHz, U320-SCSI, 2Gb Fibre Channelare twice as
fast as PCI32-33MHz
PCI64-66MHz, PCI-X-66MHz, 1xInfiniBand, 1xPCI-Express  are twice as
fast as PCI32-66MHz.
PCI-X-1.0-133MHz is twice as fast as PCI-X-66MHz
PCI-X-2.0-266MHz, 10Gb Fibre Channel, 10 Gb Ethernet, 4xInfiniBand,
4xPCI-Express are twice as fast as PCI-X-133MHz
PCI-X-2.0-533MHz is twice as fast as PCI-X-266MHz
PCI-X-3.0-1066MHz, 40 Gb Ethernet will be twice as fast as
PCI-X-533MHz

Somewhere in the upper range there are AMDs HyperTransport and
Motorolas RapidIO

Kolja Sulimma

Article: 63647
Subject: Re: XC9500 design does not fit into Coolrunner
From: Iwo Mergler <Iwo_dot_Mergler@soton_dot_sc_dot_philips_dot_com>
Date: Thu, 27 Nov 2003 11:42:01 +0000
Links: << >>  << T >>  << A >>
Klaus Falser wrote:
> Hello,
> 
> I have a rather large design for a XC95288XL which consumes 276 macrocells 
> of 288 possible.
> Since Xilinx seems to prefer Coolrunner devices to the good old XC9500's 
> I tried to stuff the design into a Coolrunner II chip to look how it 
> would behave.
> 
> However, I was not able to make it fit even in a 512 macrocell device.
> Timing should not be so tight, it has to run at 8 MHz clock, but the 
> timing analyzer gives me 17-18 MHz on the slowest 10 ns device.
> 
> Can anybody which know's the XCR2 better than me give me a hit where 
> to pay attention?
> How can I see from the report where the fitter has a problem?
> 
> Thanky you very much
>        

Have you constrained the design (pin assignments, etc)? What
is the fitter complaining about?

There are some hard limits, like less OE lines than there are
outputs to a block. If, for instance, you are trying to create
a large GPIO device with more than 4 I/Os per block (8 are
possible) it won't work.

Kind regards,

Iwo


Article: 63648
Subject: Re: external sdram and gdb tool
From: Tom <t_t_1232000@yahoo.com>
Date: Thu, 27 Nov 2003 13:40:22 +0100
Links: << >>  << T >>  << A >>
Hi Ryan, 

I tried to connect with ppcconnect to the board, and then i downloaded
the program. Then I started the processor and the program worked.

ppcconnect
dow ppc405_0/code/executable.elf
con

Correct me if I am wrong, but is this what the bootloader should do ?
Could you be more specific about the bootloader?

Thanks, 

Tom


On Wed, 26 Nov 2003 10:01:29 -0700, Ryan Laity
<ryan_dot_laity@x-i-l-i-n-x_pleasenospam_dot_com> wrote:

>Hi Tom,
>
>How are you populating the SDRAM with your .elf file when not using the 
>debugger? Perhaps you're doing this properly, but you didn't mention it 
>here so I have to ask.  When downloading the .bit file via iMPACT, the 
>only .elf data that you can possibly have is that in the Block RAM.  If 
>you're not moving the .elf into SDRAM then that's the problem; you will 
>need a bootloader of some sort to move the data from a static location 
>(Flash, etc.) into SDRAM.
>
>If you are already loading the .elf into SDRAM, then use the XMD tool to 
>check the validity of the .elf file in memory.  What I typically do is 
>run an object dump (either mb-objdump or powerpc-eabi-objdump) on the 
>.elf file (I typically use the -S option) and pipe that out to a text 
>file.  Next, connect to the device via XMD (ppcconnect or mbconnect) and 
>do mwr's from the base address of your SDRAM.  If you do something like 
>mwr 0xF0000000 20, it will dump the 20 addresses after 0xF0000000 
>(obviously change this to match your SDRAM base address) and you can 
>check them against the .elf file.  The boot section of the .elf is at 
>the bottom of the file so look there to start.  This will check that 
>your bootloader is doing its job properly and that your system is able 
>to read from the static location (Flash, etc.) properly (we already know 
>that it can write to SDRAM properly because it works with the debugger).
>
>I hope this information helps.  If not, please post a follow up or open 
>a case with Support.
>
>
>Ryan Laity
>Xilinx Applications
>
>
>Tom wrote:
>
>> Hi, 
>> 
>> I have some project where I store my entire program in the external
>> sdram (by redirecting every section in the linker script to the
>> sdram). When I download the program to the board, it doesn't work.
>> When I run the program in the debugger tool, it works. Does anybody
>> know an answer to this problem ?
>> 
>> regards, 
>> 
>> Tom


Article: 63649
Subject: Re: external sdram and gdb tool
From: Tom <t_t_1232000@yahoo.com>
Date: Thu, 27 Nov 2003 14:36:49 +0100
Links: << >>  << T >>  << A >>
Of course I downloaded the program first with XPS, and then I
downloaded it a second time with xmd.

I also checked the boot section: 

f1000ca0 <_boot0>:
f1000ca0:	3c 00 f1 00 	lis	r0,-3840
f1000ca4:	60 00 00 68 	ori	r0,r0,104
f1000ca8:	7c 08 03 a6 	mtlr	r0
f1000cac:	4e 80 00 20 	blr
Disassembly of section .boot:

f1000cb0 <_boot>:
f1000cb0:	4b ff ff f0 	b	f1000ca0 <__stack> 


Tom


On Thu, 27 Nov 2003 13:40:22 +0100, Tom <t_t_1232000@yahoo.com> wrote:

>Hi Ryan, 
>
>I tried to connect with ppcconnect to the board, and then i downloaded
>the program. Then I started the processor and the program worked.
>
>ppcconnect
>dow ppc405_0/code/executable.elf
>con
>
>Correct me if I am wrong, but is this what the bootloader should do ?
>Could you be more specific about the bootloader?
>
>Thanks, 
>
>Tom
>
>
>On Wed, 26 Nov 2003 10:01:29 -0700, Ryan Laity
><ryan_dot_laity@x-i-l-i-n-x_pleasenospam_dot_com> wrote:
>
>>Hi Tom,
>>
>>How are you populating the SDRAM with your .elf file when not using the 
>>debugger? Perhaps you're doing this properly, but you didn't mention it 
>>here so I have to ask.  When downloading the .bit file via iMPACT, the 
>>only .elf data that you can possibly have is that in the Block RAM.  If 
>>you're not moving the .elf into SDRAM then that's the problem; you will 
>>need a bootloader of some sort to move the data from a static location 
>>(Flash, etc.) into SDRAM.
>>
>>If you are already loading the .elf into SDRAM, then use the XMD tool to 
>>check the validity of the .elf file in memory.  What I typically do is 
>>run an object dump (either mb-objdump or powerpc-eabi-objdump) on the 
>>.elf file (I typically use the -S option) and pipe that out to a text 
>>file.  Next, connect to the device via XMD (ppcconnect or mbconnect) and 
>>do mwr's from the base address of your SDRAM.  If you do something like 
>>mwr 0xF0000000 20, it will dump the 20 addresses after 0xF0000000 
>>(obviously change this to match your SDRAM base address) and you can 
>>check them against the .elf file.  The boot section of the .elf is at 
>>the bottom of the file so look there to start.  This will check that 
>>your bootloader is doing its job properly and that your system is able 
>>to read from the static location (Flash, etc.) properly (we already know 
>>that it can write to SDRAM properly because it works with the debugger).
>>
>>I hope this information helps.  If not, please post a follow up or open 
>>a case with Support.
>>
>>
>>Ryan Laity
>>Xilinx Applications
>>
>>
>>Tom wrote:
>>
>>> Hi, 
>>> 
>>> I have some project where I store my entire program in the external
>>> sdram (by redirecting every section in the linker script to the
>>> sdram). When I download the program to the board, it doesn't work.
>>> When I run the program in the debugger tool, it works. Does anybody
>>> know an answer to this problem ?
>>> 
>>> regards, 
>>> 
>>> Tom




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMar2019

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search