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kempaj@yahoo.com (Jesse Kempa) writes: Hi Jesse, Thank you for your reply. > Send me an email and I'll send you my design -- it is just that, the That would be great. You'll find my e-mail address at: http://gustad.com/pics/email.gif > master) being 16-bits wide is solved by something called "dynamic bus > sizing". This is a feature of the Avalon bus which has been present in I'm familiar with dynamic bus sizing from other arcitechrues, but I was not aware of that it was implemented in NIOS/Avalon. I'll have to spend some time debugging my simulation... Again, thank you for your extensive reply. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 63976
Hi, I agree with the fact that crossing clock domains with special care is still possible even with higher clock frequencies. However, I believe some designs involving the Virtex II Pro cross clock boundaries (300 MHz to 100 MHz and the opposite) without concern about skew. Does that mean that the skew is negligible compared to propagation delay by construction of the Virtex II Pro ? Would it be the same for Virtex II ? JF Hasson "Ray Andraka" <ray@andraka.com> a écrit dans le message de news: 3FD73863.BE23FD47@andraka.com... > The input_jitter constraint does not factor in jitter caused skew between clock > nets. It only decreases the available cycle time in your period constraint to > account for cycle to cycle variations (jitter) in the clock for that net. I > don't know if the VirtexII suffers to the same degree or not (and I haven't > chanced it) from DLL output spreading due to input jitter. > > Safe crossing between related clock domains in not overly difficult, and is > still possible to do with the faster clock speeds. The only work around other > than deliberate safe crossing design is to guarantee the delay between two > flip-flops on different but related clocks is greater than the maximum possible > clock skew between those flip-flops, which is to say you have to depend on LUTs > and routing to delay the data signal. If speed is critical, then adding the > delays can hurt you more than doing a proper safe crossing. > > John_H wrote: > > > The new version of Xilinx tools (6.1i and on) appear to be doing a more > > complete job on this analysis. The biggest problem earlier was the effect > > of input jitter on the DCM that couldn't be accounted for. Uneven loading > > on the clock nets was also an issue. Now the tools allow an INPUT_JITTER > > constraint to go along with your specified period and duty cycle. Also with > > the automated elimination of hold-time violations, it looks like the tools > > are filling in for the corner cases of design as long as we, the designers, > > give the tool the right info. > > > > I'm now happier making the transition between same-edge clock domains > > without special treatment though I know where to look first if my design > > starts to misbehave. > > > > "jean-francois hasson" <jfhasson@club-internet.fr> wrote in message > > news:3fd377da$0$6982$7a628cd7@news.club-internet.fr... > > > Hi, > > > > > > I remember reading a few lines on this newsgroup about the fact that a DLL > > > in a Virtex might not be able to handle a negligible skew between two > > > outputs (clk0 and clk2X for instance) in some situations like a heavy > > > loading difference between the two clock trees with maybe an important > > (but > > > in the datasheet spec ?) jitter on the input clock. Ever since I read this > > I > > > did not consider I could change from one clock domain to the other without > > > special care. Has anyone something new concerning these potential cases ? > > If > > > there is still a possibility does it apply only to Virtex or also to > > Virtex > > > II ? The reason I ask is that the designs coming up are running faster and > > > faster making it more difficult to consider changing clock domains with > > some > > > extra precaution. > > > Thanks, > > > > > > JF > > > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 63977
Joel,
It is possible, but not advisable. The finer the pin, the lower the
total heat time is. Also the probability of solder balls and shorts is
greater. Certain vendors sell development boards with mounted FPGA's pinned
out to berg connectors and some to MIC connectors. It's safer this way and
less agravation, also it addresses noise and power decoupling issues.
Article: 63978Plug or die testing is done as part of the fab process. Go to your favorite book site and look up VLSI processes. Here's a start: http://www.amazon.com/exec/obidos/search-handle-url/index=books&field-keywords=Integrated%20circuits/ref=br_sub_/103-2193650-9589411 "Nick" <nc300@imperial.ac.uk> wrote in message news:c9sdtv8c41j4oj7shuc6o8ai4gm0li7ae2@4ax.com... > Hi, > > can anyone point out a book, paper or webpage where manufacturing > tests are described? > > By manufacturing tests I mean before packaging, when the manufacturer > determines whther a chip is defective or not > > Thanks > >Article: 63979
Marc Randolph wrote: > I am not saying I'm against revolutions when they are really called for. > I'm just saying that the word has been associated with A LOT of > failure and that whenever I hear it coming from the mouth of a marketing > droid, I hold onto my wallet. Fear of revolution? Let's stay away from politics, and look at technology: Programmable logic was a revolutionary idea (Signetics, MMI, Xilinx) FM radio, LCD display, the PC/Mac, transistors, the printed circuit board, the idea of a stored-program computer, telephony, radio, etc are all revolutionary and successful ideas in electronics. The 4-stroke gasoline (Otto) and Diesel, and jet engines, powered flight (Wright), movable type (Gutenberg) were all revolutionary inventions that caught on extremely fast. Vaccination and recent progress in medicine must be called revolutionary. (Nice not to worry about polio anymore). DNA testing in law enforcement... Let's keep at least some of the enthusiasm for scientific progress that permeated my youth, long ago. Let's hear it for revolution again! Down with pessimism and sarcasm ! Peter AlfkeArticle: 63980
Soldering by hand works. Investment in micro-width solder and solder-wick are only part of the journey. I can do this kind of work easily under a stereo microscope but I imagine a hobbyist may not have one handy and they tend to be more than $100-$250. Perhaps jewelers' magnifiers (the glasses with the lenses on swing-in arms) could suffice but personally, I don't want to get my face too close to boiling rosin. Tacking down opposite corner pins for an alignment check around all four sides is a good start, allowing a slight skew to be corrected before going too far down a wrong path. With those corners in place, the trick is to get good solder flow without wicking to the adjacent pad. It's tough but can be fun. "Georgi Beloev" <gbH8SPAM@beloev.net> wrote in message news:vteoqe7hkto707@corp.supernews.com... > Hey Joel, > > It is possible to solder TQFP/PQFP packages using a gold soldering iron and > bit of patience. Be sure do doulbe-check visually and electrically the board > before power-up. > > There are also other methods. For example, take a look at this page (I have > not tried this method myself... yet): > > http://www.seattlerobotics.org/encoder/200006/oven_art.htm > > Regards, > -- Georgi > > > > "Joel Smith" <joels@mobyfoo.org> wrote in message > news:1071075419.16811.0@eunomia.uk.clara.net... > > Hello, > > > > Is it possible for a hobbyist to solder FPGAs with high pin counts to > > PCBs? How would I go about doing it? What equipment would I need? > > > > I want to starting working with FPGAs and rather than buying a development > > board I wanted to build my own board gradually from scratch. Is this a > > silly idea? > > > > I've talked to some electrical repair people I know and they say its > > impossible to solder chips with 200 pins or so without expensive kit. Is > > this true? I could afford to spend maybe $100-$250 on some kit. > > > > I've read some stuff, on the web, that seems to suggest that it is > possible for a > > hobbyist to solder FPGAs. What advice can you guys give? > > > > Thanks very much, > > > > Joel. > >Article: 63981
"Peter Alfke" wrote > Jim, > this was the first pre-announcement of something new from Xilinx. Don't > complain that it is vague, it is meant to be. It's supposed to create > interest, curiosity, perhaps even impatient excitement. Maybe - I'm still trying to cut through the fluff, to make my own mind up. > > "Austin Lesea" wrote > > > Jim, > > > If we can architect a device to allow for any collection of "stripes" > > > and have the mask, and the software ready immediately, isn't that worth > > > shouting about? > > > > Can you clarify 'the mask' ? > > Does this mean this will become like a block-hard-copy (but still FPGA), > > where a large enough customer (/market?) can 'select the mix of stripes' > > and a new die results ? One poor aspect of the info so far, is it does not delineate SOFT and HARD features clearly at all. So, I am trying to see what is new, or clever, and may be over-interpreting some info.... Putting the discussion of 'revolution' to one side, can we focus on what really is new, or clever ? My reading of the fluff so far, is that there is some freedom to stripe-select at FAB time, and so Xilinx can roll new die variants relatively easily to target new market segments - correct, or not ? Now, if that really is a whole new mask set, then that will have significant NRE costs, esp at 90nm, and so restrict the market reach, but I could imagine a smarter-flow where the stripes are 'printed a stripe at a time', and this would slash NRE to an admin/package/test flow aspect. Q: Which of these applies to 'the mask' ? -jgArticle: 63982
The easiest part to solder is a BGA. You line it up on the pads and to keep it from sliding during reflow you must glue some sort of "corral" around it; I've used SMT resistors for this. Then you just heat it up with one of those big red hot air guns that look like oversized hair dryers that would fry a hole in your scalp (I think these are around $100.) I've done this with success. You may have to put solder or paste on the pads if there is none on the PCB already. -Kevin "Joel Smith" <joels@mobyfoo.org> wrote in message news:1071075419.16811.0@eunomia.uk.clara.net... > Hello, > > Is it possible for a hobbyist to solder FPGAs with high pin counts to > PCBs? How would I go about doing it? What equipment would I need? > > I want to starting working with FPGAs and rather than buying a development > board I wanted to build my own board gradually from scratch. Is this a > silly idea? > > I've talked to some electrical repair people I know and they say its > impossible to solder chips with 200 pins or so without expensive kit. Is > this true? I could afford to spend maybe $100-$250 on some kit. > > I've read some stuff, on the web, that seems to suggest that it is possible for a > hobbyist to solder FPGAs. What advice can you guys give? > > Thanks very much, > > Joel.Article: 63983
Jim, ---snip--- >... there is some freedom to > stripe-select at > FAB time, and so Xilinx can roll new die variants relatively easily to > target > new market segments - correct, or not ? Correct. The rest has to wait for the next press release. AustinArticle: 63984
Jim, it's best to stop reading too much into the press release. We should never even have mentioned stripes and soft and hard, it just sends smart guys like you off in strange directions. Let's keep it at: Xilinx will soon announce a new and exciting, fast and flexible architecture. Stay tuned, you will like it. You can decide later whether it is evolutionary or revolutionary. Trust me, it's both... End of story, for the time being. Peter Alfke ====================== Jim Granville wrote: > > "Peter Alfke" wrote > > Jim, > > this was the first pre-announcement of something new from Xilinx. Don't > > complain that it is vague, it is meant to be. It's supposed to create > > interest, curiosity, perhaps even impatient excitement. > > Maybe - I'm still trying to cut through the fluff, to make my own mind up. > > > > "Austin Lesea" wrote > > > > Jim, > > > > If we can architect a device to allow for any collection of "stripes" > > > > and have the mask, and the software ready immediately, isn't that > worth > > > > shouting about? > > > > > > Can you clarify 'the mask' ? > > > Does this mean this will become like a block-hard-copy (but still FPGA), > > > where a large enough customer (/market?) can 'select the mix of stripes' > > > and a new die results ? > > One poor aspect of the info so far, is it does not delineate SOFT and HARD > features clearly at all. > So, I am trying to see what is new, or clever, and may be over-interpreting > some info.... > > Putting the discussion of 'revolution' to one side, can we focus on > what really is new, or clever ? > > My reading of the fluff so far, is that there is some freedom to > stripe-select at > FAB time, and so Xilinx can roll new die variants relatively easily to > target > new market segments - correct, or not ? > > Now, if that really is a whole new mask set, then that will have > significant > NRE costs, esp at 90nm, and so restrict the market reach, but I could > imagine > a smarter-flow where the stripes are 'printed a stripe at a time', and this > would > slash NRE to an admin/package/test flow aspect. > Q: Which of these applies to 'the mask' ? > > -jgArticle: 63985
If you really want to solder a fine pitch IC - Get a Metcal soldering iron (or borrow one) "Amos B. Moses" <nospam@nospam.com> wrote in message news:qOKBb.35636$ue2.6262@newssvr32.news.prodigy.com... > Joel, > It is possible, but not advisable. The finer the pin, the lower the > total heat time is. Also the probability of solder balls and shorts is > greater. Certain vendors sell development boards with mounted FPGA's pinned > out to berg connectors and some to MIC connectors. It's safer this way and > less agravation, also it addresses noise and power decoupling issues. > > >Article: 63986
Hey, I'd be happy if they get their current hardware and software to operate fully. :) Peter Alfke wrote: > > Jim, it's best to stop reading too much into the press release. We > should never even have mentioned stripes and soft and hard, it just > sends smart guys like you off in strange directions. > > Let's keep it at: > Xilinx will soon announce a new and exciting, fast and flexible > architecture. Stay tuned, you will like it. > You can decide later whether it is evolutionary or revolutionary. > Trust me, it's both... > End of story, for the time being. > > Peter Alfke > ====================== > Jim Granville wrote: > > > > "Peter Alfke" wrote > > > Jim, > > > this was the first pre-announcement of something new from Xilinx. Don't > > > complain that it is vague, it is meant to be. It's supposed to create > > > interest, curiosity, perhaps even impatient excitement. > > > > Maybe - I'm still trying to cut through the fluff, to make my own mind up. > > > > > > "Austin Lesea" wrote > > > > > Jim, > > > > > If we can architect a device to allow for any collection of "stripes" > > > > > and have the mask, and the software ready immediately, isn't that > > worth > > > > > shouting about? > > > > > > > > Can you clarify 'the mask' ? > > > > Does this mean this will become like a block-hard-copy (but still FPGA), > > > > where a large enough customer (/market?) can 'select the mix of stripes' > > > > and a new die results ? > > > > One poor aspect of the info so far, is it does not delineate SOFT and HARD > > features clearly at all. > > So, I am trying to see what is new, or clever, and may be over-interpreting > > some info.... > > > > Putting the discussion of 'revolution' to one side, can we focus on > > what really is new, or clever ? > > > > My reading of the fluff so far, is that there is some freedom to > > stripe-select at > > FAB time, and so Xilinx can roll new die variants relatively easily to > > target > > new market segments - correct, or not ? > > > > Now, if that really is a whole new mask set, then that will have > > significant > > NRE costs, esp at 90nm, and so restrict the market reach, but I could > > imagine > > a smarter-flow where the stripes are 'printed a stripe at a time', and this > > would > > slash NRE to an admin/package/test flow aspect. > > Q: Which of these applies to 'the mask' ? > > > > -jg -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 63987
Yeah, in the specification it is 3 clocks for each transfer. however now if i want to put burst data on it, but i will change the state machines in the APB slave, meaning i am not following the APB protocol any more... Does that work? Mike Lewis <someone@microsoft.com> wrote in message news:OqWdnQf-lYnM-UqiRVn-gQ@magma.ca... > The AMBA APB bus does not support bursting. > All accesses are of a fixed length (3 clocks). Typically > an application that uses an APB bus also has > an APB bridge that connects the APB bus to > an AHB bus. You can busrt on the AHB bus if you like .... > the bridge will convert that to fixed length cycles > on the APB bus and insert wait states in the AHB burst. > > "Invincible" <asdf@asdf.com> wrote in message > news:br5iph$v0e$1@reader01.singnet.com.sg... > > Hi, there: > > > > I am reading AMBA specification. > > Does the Read/Write waveform for the APB indicate the bus speed is 1/3 of > > the pclk frequency? > > Now if I need to write a continuously in every clock cycle, may I keep the > > PWRITE, PSELx and > > PENABLE high for many cycles while keep changing address and data every > > clock cycle? > > OR, am I obliged to use AHB's burst moode? > > > > Thanks. > > > > > > > > > >Article: 63988
I found that soldering SMDs (including TQFPs and PQFPs) is easy, as long as you have flux handy. Tweezers and a magnifier can also be useful. Jean more advices here: http://www.fpga4fun.com/forum/viewtopic.php?t=6 "Joel Smith" <joels@mobyfoo.org> wrote in message news:1071075419.16811.0@eunomia.uk.clara.net... > Hello, > > Is it possible for a hobbyist to solder FPGAs with high pin counts to > PCBs? How would I go about doing it? What equipment would I need? > > I want to starting working with FPGAs and rather than buying a development > board I wanted to build my own board gradually from scratch. Is this a > silly idea? > > I've talked to some electrical repair people I know and they say its > impossible to solder chips with 200 pins or so without expensive kit. Is > this true? I could afford to spend maybe $100-$250 on some kit. > > I've read some stuff, on the web, that seems to suggest that it is possible for a > hobbyist to solder FPGAs. What advice can you guys give? > > Thanks very much, > > Joel.Article: 63989
Hi, many thanks for ur suggestionz, it works !=20 -----Original Message----- From: Colm Clancy [mailto:colmc@xilinx.com] Posted At: Wednesday, December 10, 2003 2:16 AM Posted To: fpga Conversation: Too many signals [Xilinx Foundation 4.1i] Subject: Re: Too many signals [Xilinx Foundation 4.1i] If I remember right this was a known issue way back where the number of = signals on a sheet could not exceed 1024. The workaround was (as = lnguyen) said to split the design over multiple sheets Basuki Endah Priyanto wrote: > Hi all, > I'd like to highlight a problem encountered while using the Xilinx = foundation series 4.1i. I am unable to connect all the input ports to = the respective output ports due the following comments shown: > Too many signals: Checking for sourceless, loadless nets and multiple = drivers aborted. > I suspect that there is a limit to the number of bus terminal labels = that we can give on a schematic. > The bus terminal labels are given to the inputs and outputs ports so = that they need not to be physically connected with wires. These termianl = labels are essential as it is impossible to physically connect the ports = together with wires under the constraint of the space given in the = schematic. > > Any idea how to solve the problem ??? > > Thanks. > > BuzzArticle: 63990
Hi,Scott, I'm planning a new project related to yours, though I need both DVI input and output, may I know the source of FPGA development board that you are using ? where you bought this board from ? thanks, JulianArticle: 63991
Hi all, I have a 4-FPGA design with nearly identical VHDL source code, so in order to speed development, I started using the command-line tools instead of the Xilinx IDE (which basically also runs the cmd line tools from the shell). I've encountered strange behavior since: 1. MPPR and PAR with the same cost table generate different results on my PC (w2k, sp3, running 5.2i sp3). This is not such a big issue, as I wrote my own batch to do an MPPR by calling PAR with different cost tables values. 2. PAR run from the ISE and PAR from the command line generate different results, with identical options and input files (I actually used the .cmd_log file to write my own batch file). More specifically, ISE returns result A, cmd line returns B. Strangely enough, I ran the cmdline tools on another PC, with identical settings, and this returned result A as well. I browsed through the Xilinx answer database for clues, and I found no. 17134, describing a similar problem. A workaround is presented, but when I implement it (it involves settings the PL_NODIROPT env. variable to 1), I get yet another result, C. Has anyone encountered this problem before and was able to solve it? Thanks in advance, Jo Pletinckx ___________________________________________________________________________ ir. Jo Pletinckx Ghent University Department of Information technology / INTEC-design Sint-Pietersnieuwstraat 41 B-9000 GENT Belgium, Europe ___________________________________________________________________________Article: 63992
"Joel Smith" <joels@mobyfoo.org> wrote in message news:1071075419.16811.0@eunomia.uk.clara.net... > Hello, > > Is it possible for a hobbyist to solder FPGAs with high pin counts to > PCBs? How would I go about doing it? What equipment would I need? > > I want to starting working with FPGAs and rather than buying a development > board I wanted to build my own board gradually from scratch. Is this a > silly idea? > > I've talked to some electrical repair people I know and they say its > impossible to solder chips with 200 pins or so without expensive kit. Is > this true? I could afford to spend maybe $100-$250 on some kit. > > I've read some stuff, on the web, that seems to suggest that it is possible for a > hobbyist to solder FPGAs. What advice can you guys give? > The method I used to do for PQ208s and such was to make my PCBs with lead&tin coating. Now, all what I needed to do was to glue the PQ208 part in its place, and use hot air on the pins. Less than 2 minutes for a perfect job.Article: 63993
John_H <johnhandwork@mail.com> wrote in message news:1GLBb.9$Ej2.1783@news-west.eli.net... > I can do this kind of work easily under a > stereo microscope but I imagine a hobbyist may not have one handy and they > tend to be more than $100-$250. If you keep an eye on auctions you might be able to pick one up for this sort of money. An example is http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&item=2580122938&category=361 Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 63994
Hi all, I'm working on a verification of a network on chip switch. FCII produces "latch inferred" warnings, and later we get "gated clock" warnings from Xilinx tools. When implemented in VirtexE, the switch (of course) has completely bogus output. It was easy to identify a culprit: almost all the conditional assignments are incompletely specified. Anyway, I'm having problems describing to the design team why their coding style is incomplete, especially because they claim that it works perfectly in a back-annotated simulation. Could you please arm me with some examples of race_conditions/bugs that can emerge from those "latch inferred" warnings ? Also, should I advise them to try simulating VHDL generated after routing in order to get more insight ? Thx. Best regards, -- Domagoj Babic domagoj (et) engineer.comArticle: 63995
Hi,
I am a novice to hardware programming...
I have a query..I need to know which PCI versions any motherboard can support...
E.g I wish to find which versions of PCI my i810 chipset motherboard
(or rather any motherboard) can support
Is there any method to accomplish this?
Thanks and regards,
Article: 63996Hi (Mohan and rest ;), When I have downloaded a bootloader in bram at a microblaze system, I download by use of the microblaze my application to external SDRAM and after that the Xilinx Micro Kernel (also to external SDRAM). To start my application and the kernel I have to jump to the start address of my kernel (the kernel will automatically run the application). What I want to do is the following: When running the application, I want to be able to return to the bootloader in order to download a new application. But just jumping to the start address of the bootloader is (in my opinion) not enough. The kernel still keeps running, I guess. How can I make this possible?? Is there a way to stop the kernel? Or another way to replace the application with a new one (by using the bootloader). Or is described behaviour not possible when using the kernel?! FrankArticle: 63997
Well if your not following the protocol any more .. you're making your own protocol so anything will work as long as you design it right. :) You would also have to change the protocol of the AHB to APB bridge or whatever master device you have driving the APB slaves. Mike "One Day & A Knight" <kelvin8157@hotmail.com> wrote in message news:3fd75ab9$1@news.starhub.net.sg... > Yeah, in the specification it is 3 clocks for each transfer. > > however now if i want to put burst data on it, but i will change the state > machines in the APB slave, > meaning i am not following the APB protocol any more... > > Does that work? > > > > Mike Lewis <someone@microsoft.com> wrote in message > news:OqWdnQf-lYnM-UqiRVn-gQ@magma.ca... > > The AMBA APB bus does not support bursting. > > All accesses are of a fixed length (3 clocks). Typically > > an application that uses an APB bus also has > > an APB bridge that connects the APB bus to > > an AHB bus. You can busrt on the AHB bus if you like .... > > the bridge will convert that to fixed length cycles > > on the APB bus and insert wait states in the AHB burst. > > > > "Invincible" <asdf@asdf.com> wrote in message > > news:br5iph$v0e$1@reader01.singnet.com.sg... > > > Hi, there: > > > > > > I am reading AMBA specification. > > > Does the Read/Write waveform for the APB indicate the bus speed is 1/3 > of > > > the pclk frequency? > > > Now if I need to write a continuously in every clock cycle, may I keep > the > > > PWRITE, PSELx and > > > PENABLE high for many cycles while keep changing address and data every > > > clock cycle? > > > OR, am I obliged to use AHB's burst moode? > > > > > > Thanks. > > > > > > > > > > > > > > > > > >Article: 63998
Get them to simulate at the gate level and see if they get the same results. I'm guessing they won't ... that should be enough amo to shoot em down. Mike "Domagoj Babic" <domagoj@engineer.com> wrote in message news:br9lgj$73g$1@nntp.itservices.ubc.ca... > Hi all, > > I'm working on a verification of a network on chip switch. FCII produces > "latch inferred" warnings, and later we get "gated clock" warnings from > Xilinx tools. When implemented in VirtexE, the switch (of course) has > completely bogus output. > > It was easy to identify a culprit: almost all the conditional assignments > are incompletely specified. > > Anyway, I'm having problems describing to the design team why their coding > style is incomplete, especially because they claim that it works perfectly > in a back-annotated simulation. > > Could you please arm me with some examples of race_conditions/bugs that can > emerge from those "latch inferred" warnings ? > > Also, should I advise them to try simulating VHDL generated after routing in > order to get more insight ? > > Thx. > > Best regards, > > -- > > Domagoj Babic > domagoj (et) engineer.com > > >Article: 63999
Thank you! And how can i realize a 32-bit wide FIFO? At the moment I use the Xilinx-FIFO-designs for Spartan-II. They use block ram - but the biggest module i can get is 16bit-wide. Is it possible to use 2 instances of ramb4_s16_s16 and drive each instance with the same clock, enable signals and so on? Thank you, Simone "Mike Lewis" <someone@microsoft.com> schrieb im Newsbeitrag news:4P-dnWSWl-I__kqi4p2dnA@magma.ca... : If you make the FIFO 32 bits wide on both ports. : Then alternate between writing to the lower : and upper half of the 32 bit datapath on the : "16 bit" side of the fifo you have effectively : converted from 16 to 32 bits when travelling through the : FIFO.
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