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Messages from 67325

Article: 67325
Subject: Very strange Xilinx timing report.
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Wed, 10 Mar 2004 19:09:30 +0800
Links: << >>  << T >>  << A >>
Hi, there:

I am synthesizing a design with 12 & 4MHz and 36MHz clock from two different
DCMs, but
I made them synchronize to same input 40MHz clock. However, I got this type
of odd
timing errors. How may I correct such problem?

Best Regards,
Kelvin





Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------
----
  Constraint                                | Requested  | Actual     |
Logic
                                            |            |            |
Levels
----------------------------------------------------------------------------
----
  TS_exahb_clk_1m_sdr = PERIOD TIMEGRP "exa | 1000.000ns | 5.550ns    | 2
  hb_clk_1m_sdr" 1000 nS HIGH 50.000000  %  |            |            |
----------------------------------------------------------------------------
----
  TS_exahb_clk_12m_sdr = PERIOD TIMEGRP "ex | 83.333ns   | 16.065ns   | 16
  ahb_clk_12m_sdr" TS_exahb_clk_1m_sdr /  1 |            |            |
  2.000000 HIGH 50.000 %                    |            |            |
----------------------------------------------------------------------------
----
  TS_clk_40m_w = PERIOD TIMEGRP "clk_40m_w" | N/A        | N/A        | N/A
    25 nS   HIGH 50.000000 %                |            |            |
----------------------------------------------------------------------------
----
  TS_clk_36m_rx = PERIOD TIMEGRP "clk_36m_r | 27.777ns   | 3.410ns    | 3
  x" TS_clk_40m_w / 0.900000 HIGH 50.000  % |            |            |
----------------------------------------------------------------------------
----
* TS_clk_4m_rx = PERIOD TIMEGRP "clk_4m_rx" | 250.000ns  | 164750.000ns | 3
   TS_clk_40m_w * 10.000000 HIGH 50.000  %  |            |            |
----------------------------------------------------------------------------
----
  TS_clk_12m_rx = PERIOD TIMEGRP "clk_12m_r | 83.333ns   | 18.399ns   | 28
  x" TS_clk_40m_w / 0.300000 HIGH 50.000  % |            |            |
----------------------------------------------------------------------------
----




Article: 67326
Subject: Re: novice for FPGA
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Wed, 10 Mar 2004 19:32:15 +0800
Links: << >>  << T >>  << A >>
Tong:

If you have learnt Verilog or VHDL then a LUT is not difficult to build. I
can provide you
some sample functional source codes of LUTs in Verilog...

However I don't know how they build switch box either, I suspect it is made
up of some
transmission gates cascaded together?

For example, the following is a LUT1, but you need to use standard gates to
build it...



// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/s/LUT1.v,v
1.4.30.1 2001/11/19 17:06:31 patrickp Exp $
/*

FUNCTION : 2-inputs LUT

*/

`timescale  100 ps / 10 ps

`celldefine

module LUT1 (O, I0);

    parameter INIT = 2'h0;

    input I0;

    output O;

    wire out;

    lut1_mux2 (out, INIT[1], INIT[0], I0);

    buf b1 (O, out);

    specify
 (I0 *> O) = (1, 1);
    endspecify

endmodule

`endcelldefine

primitive lut1_mux2 (O, d1, d0, s0);

  output O;
  input d1, d0;
  input s0;

  table

    // d1  d0  s0 : O;

       ?   1   0  : 1;
       ?   0   0  : 0;
       1   ?   1  : 1;
       0   ?   1  : 0;
       0   0   x  : 0;
       1   1   x  : 1;

  endtable

endprimitive




Tong <nospam@cuhk.edu.hk> wrote in message
news:c2mmt6$1h7c$1@justice.itsc.cuhk.edu.hk...
> hi Kelvin,
>
> Yup, I come from The Chinese University of Hong Kong.
> I don't think my professor is fooling me. May be I should state clearly
what
> I have to do.
>
> The poject do not require us to make a real chip. We just use magic to
draw
> the layout and use irsim to simulate. And, it is a group poject.
>
> Could you shed a light on my project?
>
>
> Regards,
> Tong
>
>
> "Kelvin @ SG" <kelvin8157@hotmail.com> ΌΆΌg©σΆl₯σ·s»D
> :404e7739@news.starhub.net.sg...
> > it seems your professor is fooling you...i guess designing a decent FPGA
> > chip will require a big team of
> > engineers and top of the line Cadence & Mentor softwares...be prepared
to
> > pay hundreds of thousands US$
> > for the licenses alone...besides, it seems u r from a Chinese
> university...
> >
> >
> >
> > Tong <nospam@cuhk.edu.hk> wrote in message
> > news:c2km7a$ko9$1@justice.itsc.cuhk.edu.hk...
> > > hi all,
> > >
> > > I am a undergraduate studying VLSI and Magic manul layout. My
professor
> > have
> > > asked us to design an FPGA chip using Magic.
> > > I am confused in how to build the switch box and look up table. Could
> > anyone
> > > kindly recommend some website or books that gives detail explanation
on
> > > these stuff.
> > >
> > > Thanks a lot.
> > >
> > > Regards,
> > > Tong
> > >
> > >
> >
> >
>
>



Article: 67327
Subject: Re: Very strange Xilinx timing report.
From: "John Adair" <newsreply@loseinspace.co.uk>
Date: Wed, 10 Mar 2004 11:34:19 -0000
Links: << >>  << T >>  << A >>
Suggest you run Timing Analyser and get a full list of paths in error. Will
give the starting registers and end registers that are in error.

John Adair
Enterpoint Ltd.
http://www.enterpoint.co.uk

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.

"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message
news:404ef78c@news.starhub.net.sg...
> Hi, there:
>
> I am synthesizing a design with 12 & 4MHz and 36MHz clock from two
different
> DCMs, but
> I made them synchronize to same input 40MHz clock. However, I got this
type
> of odd
> timing errors. How may I correct such problem?
>
> Best Regards,
> Kelvin
>
>
>
>
>
> Asterisk (*) preceding a constraint indicates it was not met.
>    This may be due to a setup or hold violation.
>
> --------------------------------------------------------------------------
--
> ----
>   Constraint                                | Requested  | Actual     |
> Logic
>                                             |            |            |
> Levels
> --------------------------------------------------------------------------
--
> ----
>   TS_exahb_clk_1m_sdr = PERIOD TIMEGRP "exa | 1000.000ns | 5.550ns    | 2
>   hb_clk_1m_sdr" 1000 nS HIGH 50.000000  %  |            |            |
> --------------------------------------------------------------------------
--
> ----
>   TS_exahb_clk_12m_sdr = PERIOD TIMEGRP "ex | 83.333ns   | 16.065ns   | 16
>   ahb_clk_12m_sdr" TS_exahb_clk_1m_sdr /  1 |            |            |
>   2.000000 HIGH 50.000 %                    |            |            |
> --------------------------------------------------------------------------
--
> ----
>   TS_clk_40m_w = PERIOD TIMEGRP "clk_40m_w" | N/A        | N/A        |
N/A
>     25 nS   HIGH 50.000000 %                |            |            |
> --------------------------------------------------------------------------
--
> ----
>   TS_clk_36m_rx = PERIOD TIMEGRP "clk_36m_r | 27.777ns   | 3.410ns    | 3
>   x" TS_clk_40m_w / 0.900000 HIGH 50.000  % |            |            |
> --------------------------------------------------------------------------
--
> ----
> * TS_clk_4m_rx = PERIOD TIMEGRP "clk_4m_rx" | 250.000ns  | 164750.000ns |
3
>    TS_clk_40m_w * 10.000000 HIGH 50.000  %  |            |            |
> --------------------------------------------------------------------------
--
> ----
>   TS_clk_12m_rx = PERIOD TIMEGRP "clk_12m_r | 83.333ns   | 18.399ns   | 28
>   x" TS_clk_40m_w / 0.300000 HIGH 50.000  % |            |            |
> --------------------------------------------------------------------------
--
> ----
>
>
>



Article: 67328
Subject: Re: Very strange Xilinx timing report.
From: "Francisco Rodriguez" <prodrig@disca.upv.es>
Date: Wed, 10 Mar 2004 12:51:55 +0100
Links: << >>  << T >>  << A >>

"Kelvin @ SG" <kelvin8157@hotmail.com> escribiσ en el mensaje
news:404ef78c@news.starhub.net.sg...
> Hi, there:
>
> I am synthesizing a design with 12 & 4MHz and 36MHz clock from two
different
> DCMs, but
> I made them synchronize to same input 40MHz clock. However, I got this
type
> of odd
> timing errors. How may I correct such problem?
>
> Best Regards,
> Kelvin
>
>
>
>
>
> Asterisk (*) preceding a constraint indicates it was not met.
>    This may be due to a setup or hold violation.
>
> --------------------------------------------------------------------------
--
> ----
>   Constraint                                | Requested  | Actual     |
> Logic
>                                             |            |            |
> Levels
> --------------------------------------------------------------------------
--
> ----
>   TS_exahb_clk_1m_sdr = PERIOD TIMEGRP "exa | 1000.000ns | 5.550ns    | 2
>   hb_clk_1m_sdr" 1000 nS HIGH 50.000000  %  |            |            |
> --------------------------------------------------------------------------
--
> ----
>   TS_exahb_clk_12m_sdr = PERIOD TIMEGRP "ex | 83.333ns   | 16.065ns   | 16
>   ahb_clk_12m_sdr" TS_exahb_clk_1m_sdr /  1 |            |            |
>   2.000000 HIGH 50.000 %                    |            |            |
> --------------------------------------------------------------------------
--
> ----
>   TS_clk_40m_w = PERIOD TIMEGRP "clk_40m_w" | N/A        | N/A        |
N/A
>     25 nS   HIGH 50.000000 %                |            |            |
> --------------------------------------------------------------------------
--
> ----
>   TS_clk_36m_rx = PERIOD TIMEGRP "clk_36m_r | 27.777ns   | 3.410ns    | 3
>   x" TS_clk_40m_w / 0.900000 HIGH 50.000  % |            |            |
> --------------------------------------------------------------------------
--
> ----
> * TS_clk_4m_rx = PERIOD TIMEGRP "clk_4m_rx" | 250.000ns  | 164750.000ns |
3
>    TS_clk_40m_w * 10.000000 HIGH 50.000  %  |            |            |
> --------------------------------------------------------------------------
--
> ----
>   TS_clk_12m_rx = PERIOD TIMEGRP "clk_12m_r | 83.333ns   | 18.399ns   | 28
>   x" TS_clk_40m_w / 0.300000 HIGH 50.000  % |            |            |
> --------------------------------------------------------------------------
--
> ----
>
>
>
Hi Kelvin

I've encountered the same timing report problems with a simpler design.
I'm working with a single DCM and have two clock domains, clkin and the
clkfx output.

Failing paths in the timing analyzer are crossing clock domains with source
and destination
clock edges separated a few ps apart. These are the ones generating odd
timing values.
These only show up with certain M/D factors used to generate the clkfx
output frequency,
like 10/3.
It seems that the tool get fooled as it can not determine the worst case for
clock edges alignment.


A TIG constraint between the clocks solved the problem.
As you've put synchronizers to sync all data, excluding those paths from the
analysis should be not an issue.

Hope this helps you

Francisco Rodriguez
================================================================
Francisco Rodriguez Ballester (prodrig@disca.upv.es)
Postal address: Dept. DISCA, EUI - Univ. Politecnica de Valencia
                c/Camino de Vera s/n, E-46022, VALENCIA (SPAIN)
tlf: +(34) 96 387 70 07 ext. 75759   -   fax: +(34) 96 387 75 79
================================================================





Article: 67329
Subject: fpga
From: sirohi_rajiv@rediffmail.com (sirohi_rajiv@rediffmail.com)
Date: 10 Mar 2004 04:02:23 -0800
Links: << >>  << T >>  << A >>
hello all.
i am working with xilinx ise webpack 6.2.
i want to know that how i can upload my program on "xilinx xc4010e" kit.
i am in great trouble so please help me.
thanking you.
rajiv

Article: 67330
Subject: Re: Very strange Xilinx timing report.
From: Stephan Neuhold <stephan.neuhold@xilinx.com>
Date: Wed, 10 Mar 2004 12:08:13 +0000
Links: << >>  << T >>  << A >>
Hi Kelvin,

This is a problem with the Timing analyzer when encountering subpicosecond
values. Derived timing constraints or the like may end up having subpicosecond
values due to multiplication and division in the DCM, etc.

You can either choose a input clock period value that will not go into the
subpicosend range due to these multiplications or division but rather stay in
the ps range. Alternatively you can also choose different values for the
multiplication and division factor so that you do not end up having
subpicosecond values but this is usually more difficult to achieve.

--Stephan



"Kelvin @ SG" wrote:

> Hi, there:
>
> I am synthesizing a design with 12 & 4MHz and 36MHz clock from two different
> DCMs, but
> I made them synchronize to same input 40MHz clock. However, I got this type
> of odd
> timing errors. How may I correct such problem?
>
> Best Regards,
> Kelvin
>
> Asterisk (*) preceding a constraint indicates it was not met.
>    This may be due to a setup or hold violation.
>
> ----------------------------------------------------------------------------
> ----
>   Constraint                                | Requested  | Actual     |
> Logic
>                                             |            |            |
> Levels
> ----------------------------------------------------------------------------
> ----
>   TS_exahb_clk_1m_sdr = PERIOD TIMEGRP "exa | 1000.000ns | 5.550ns    | 2
>   hb_clk_1m_sdr" 1000 nS HIGH 50.000000  %  |            |            |
> ----------------------------------------------------------------------------
> ----
>   TS_exahb_clk_12m_sdr = PERIOD TIMEGRP "ex | 83.333ns   | 16.065ns   | 16
>   ahb_clk_12m_sdr" TS_exahb_clk_1m_sdr /  1 |            |            |
>   2.000000 HIGH 50.000 %                    |            |            |
> ----------------------------------------------------------------------------
> ----
>   TS_clk_40m_w = PERIOD TIMEGRP "clk_40m_w" | N/A        | N/A        | N/A
>     25 nS   HIGH 50.000000 %                |            |            |
> ----------------------------------------------------------------------------
> ----
>   TS_clk_36m_rx = PERIOD TIMEGRP "clk_36m_r | 27.777ns   | 3.410ns    | 3
>   x" TS_clk_40m_w / 0.900000 HIGH 50.000  % |            |            |
> ----------------------------------------------------------------------------
> ----
> * TS_clk_4m_rx = PERIOD TIMEGRP "clk_4m_rx" | 250.000ns  | 164750.000ns | 3
>    TS_clk_40m_w * 10.000000 HIGH 50.000  %  |            |            |
> ----------------------------------------------------------------------------
> ----
>   TS_clk_12m_rx = PERIOD TIMEGRP "clk_12m_r | 83.333ns   | 18.399ns   | 28
>   x" TS_clk_40m_w / 0.300000 HIGH 50.000  % |            |            |
> ----------------------------------------------------------------------------
> ----


Article: 67331
Subject: Keeping unused ports of an entity
From: guenter.wolpert@orsys.de (G?nter Wolpert)
Date: 10 Mar 2004 04:20:59 -0800
Links: << >>  << T >>  << A >>
hello,

The problem I'm struggling with is a common thing, that has already been
discussed in this group, however, I don't like the suggested solution.
Here's the problem:
I have an FPGA design that is intended as a starting point for VHDL designs.
Design environment is Xilinx ISE.
Starting point means ALL ports are unused. Someone will then take some ports
and use them.
The suggested solution is to connect all ports to an AND gate and connect the
output to a spare port. I don't like this, since I have no spare output (each
port could potentially be used in future).
Further, the ports are a mixture of in/out/inout.

So my current solution is
- drive unused outputs to 'Z'
- connect unsued in/inout ports to signal named UNUSED_IO using a Xilinx buffer
  primitive.
- later on when a signal is used in some design, the corresponding lines are
  removed, or better, commented out.

This allows to check for a 100% IOB usage and prevents accidental placing
of ports to unused or incorrect pins.
The generated warnings appear as one block and are easy distinguished from
'real' warnings, since they relate to dedicated unused signals:
WARNING:Xst:646 - Signal <UNUSED_IO00> is assigned but never used.

However, I would appreciate if I could even supress the warnings.
further, I'm not sure if a change of development tools will cause new problems.

Does anyone know a better solution?

regards
Guenter

Article: 67332
Subject: A hardware question?
From: charlesg77@yahoo.com (chuk)
Date: 10 Mar 2004 04:30:56 -0800
Links: << >>  << T >>  << A >>
A hardware question?

I am planning to use a Virtex 300 FPGA QFP package for a current
project running with a clock of 100MHz.  My question is with regard to
the PCD design.  Due to budget restriction I would like to restrict my
design to a 2 layer PCB.  As a result, due to space restriction I have
placed the power tracks under the FPGA on the component side and plan
to place most of the larger decoupling caps on the bottom layer where
I have my ground plane.  I am concerned that placing power tracks
under the fpga may cause coupling problems as well as excessive
chopping up of the bottom layer ground plane.  The implementation is
jitter critical I must add.  Does anyone have experience on this
respect?  Should I just bite the bullet and pay for a four layer
implementation?
Thanks 
Chuk

Article: 67333
Subject: CFP: 7th Mil/Aerospace Applications of Programmable Logic Devices (MAPLD) Int'l Conference
From: "Richard B. Katz" <richard.b.katz@nospamplease.nasa.gov>
Date: 10 Mar 2004 12:45:07 GMT
Links: << >>  << T >>  << A >>



                           Call for Papers


            7th Mil/Aerospace Applications of Programmable 
            Logic Devices International Conference (MAPLD)

         Ronald Reagan Building and International Trade Center
                           Washington, D.C.
                        September 8-10, 2004

                Hosted by the NASA Office of Logic Design


   The 7th annual MAPLD International Conference's extensive program
   will include presentations, seminars, workshops, and exhibits
   on programmable logic devices and technologies, digital engineering,
   and related fields for military and aerospace applications.
   Devices, technologies, logic design, flight applications, fault
   tolerance, usage, reliability, radiation susceptibility, and
   encryption applications of programmable devices, processors,
   and adaptive computing systems in military and aerospace systems
   are among the subjects for the conference.

   Abstracts are due April 26, 2004.  Late submissions will be
   considered for poster and workshop sessions only.

   We are planning an exciting event with presentations by
   Government, industry, and academia, including talks by 
   distinguished Invited Speakers.   This conference is open to
   US and foreign participation and is not classified.  For related
   information, please see the NASA Office of Logic Design Web Site
   (http://klabs.org). 


   This year, there will be special emphasis on the following themes: 

      • "War Stories" and Lessons Learned
      • Programmable Logic and Obsolescence Issues 
      • Implementing high performance, high reliability processor cores.
      • Logic design evaluation, design guidelines, and recommendations. 
      • Verification methods for radiation hardness and fault tolerance. 
      • Applications such as MIL-STD interfaces, UAV's, and controllers.
      • Automated Checkers for low reliability design constructs. 
      • PLD tools/methods that we need but vendors don't supply.


   CONFERENCE HOME PAGE - http://klabs.org/mapld04 - contains 
   an abundance of information on both technical and programmatic
   aspects of the conference.


   SEMINARS - Two full-day seminars will be presented:

      • VHDL Synthesis for High-Reliability Systems
      • Aerospace Mishaps and Lessons Learned


   PANEL SESSION: 

      • "Why Is Space Exploration So Hard?  The Roles of Man and Machine"


   WORKSHOPS & "BIRDS OF A FEATHER" SPECIAL SESSIONS

      • Mitigation Methods for Reprogrammable Logic in
           The Space Radiation Environment
      • Reconfigurable Computing
      • PLD Failures, Analyses, and the Impact on Systems
      • Digital Engineering and Computer Design - A Retrospective and
           Lessons Learned for Today's Engineers 
           * Includes a disassembly and discussion of a Block II
             Apollo Guidance Computer by the engineers who designed it.
      • "An Application Engineer's View" - Back for 2004! 
      • "NESC and Software" - a joint session of MAPLD and the NASA
           Engineering and Saftey Center


   TECHNICAL SESSIONS:

      • Applications: Military and Aerospace
      • Systems and Design Tools
      • Radiation and Mitigation Techniques
      • Processors: General Purpose and Arithmetic
      • Reconfigurable Computing, Evolvable Hardware, and Security
      • Poster Session


   INDUSTRIAL and GOVERNMENT EXHIBITS AND SPONSORS
   (early reservations, more to come):

      NASA Office of Logic Design         Mentor Graphics Corporation
      Xilinx Corporation                  Synthworks
      Tensilica                           Actel Corporation
      Annapolis Microsystems              Space Micro, Inc.
      SEAKR Engineering                   Aldec
      IEEE Aerospace and Electronics      Systems Society
      Hier Design                         Global Velocity
      Lattice Semiconductor               Quicksilver Technology
      Celoxica                            BAE Systems
      Nallatech                           The Andraka Consulting Group 
      Aeroflex                            Synopsys
      Peregrine Semiconductor             Starbridgesystems
      Condor Engineering                  AccelChip
      NASA Engineering and Safety Center  Synplicity


   For more information, please visit http://klabs.org/mapld04
   or contact:

      Richard Katz - Conference Chair   NASA Goddard Space Flight Center
      mapld2004@klabs.org               Tel: (301) 286-9705

Article: 67334
Subject: Re: licence for Xilinx 2.1i
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Wed, 10 Mar 2004 07:56:21 -0500
Links: << >>  << T >>  << A >>
On Tue, 09 Mar 2004 23:18:38 -0800, manmohan singh wrote:

> Dear Sir,
> 
> As suggested by you I have downloaded the webpack from the Xilinx
> website but how to set the options for the device XC4010E and
> FPGA3142. Forgive me for my ignorance. kindly help me.
> 
> regards and thanks
> 
> "B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:<pan.2004.03.07.15.46.31.684698@polybus.com>...
>> On Sun, 07 Mar 2004 06:38:15 -0800, manmohan singh wrote:
>> 
>> > Hi All,
>> > Greetings,
>> > 
>> > I am a student. I found Xilinx 2.1i version software but I think
>> > Licence is expired. Can anybody give me the information from where I
>> > can get the licence (preferably free because as student I don't have
>> > much funds)
>> > 
>> > regards and thnaks
>> 
>> You don't want to use 2.1 for anything it's an antique. Xilinx offers
>> webpack which is a free version of their tools. Webpack is a subset but
>> it's probably sufficient for your needs. If you want to use the full set
>> of tools you should have your EE department contact the local Xilinx sales
>> office, I suspect that they would be happy to provide a free or
>> discounted version of their tools to you University.

The 4000 series is opsolete, the current tools no longer support it. The
oldest parts that are supported in the current generation of tools is the
Spartan but I would recommend that you not use anything older than a
Spartan 2e.


Article: 67335
Subject: Re: fpga
From: =?iso-8859-1?q?Dennis_Kr=F8ger?= <losdlosdlosd@hotmail.com>
Date: Wed, 10 Mar 2004 14:36:36 +0100
Links: << >>  << T >>  << A >>
On Wed, 10 Mar 2004 04:02:23 -0800, sirohi_rajiv@rediffmail.com wrote:

> hello all.
> i am working with xilinx ise webpack 6.2.
> i want to know that how i can upload my program on "xilinx xc4010e" kit.
> i am in great trouble so please help me.
> thanking you.
> rajiv

You say that it is a XC4010E kit... If it's a development board from some
manufacturer you should find specs for the board... But most (AFAIK) use
JTAG to program the chip... Then you should buy a JTAG cable, or make one
yourself (here's a quick schematic
http://jtag-arm9.sourceforge.net/circuit.txt), and use iMPACT to program
it...

Hope this helps!

Dennis

Article: 67336
Subject: Re: A hardware question?
From: Marc Randolph <mrand@my-deja.com>
Date: Wed, 10 Mar 2004 07:40:49 -0600
Links: << >>  << T >>  << A >>
chuk wrote:
> A hardware question?
> 
> I am planning to use a Virtex 300 FPGA QFP package for a current
> project running with a clock of 100MHz.  My question is with regard to
> the PCD design.  Due to budget restriction I would like to restrict my
> design to a 2 layer PCB.  As a result, due to space restriction I have
> placed the power tracks under the FPGA on the component side and plan
> to place most of the larger decoupling caps on the bottom layer where
> I have my ground plane.  I am concerned that placing power tracks
> under the fpga may cause coupling problems as well as excessive
> chopping up of the bottom layer ground plane.  The implementation is
> jitter critical I must add.  Does anyone have experience on this
> respect?  Should I just bite the bullet and pay for a four layer
> implementation?

Howdy Chuk,

    In my mind, this is a question of tradeoff's.  You say that you have 
a budget restriction.  Do you also have a time restriction?  If not, you 
can build a two layer, see if it has acceptable margin, and then either 
adjust on the layout, or switch gears and go with the four layer.

Or you can do what many do where time is the most critical thing: do the 
"safer" four layer version first.  Then after the time crunch is over, 
respin it and try to get cost out of it.  You'll probably discover other 
areas of the design you can cost reduce as well.

Lastly, if you're under such a tight of a budget restriction that 2 vs. 
4 layers makes a big difference, have you checked out using a Spartan 
IIE or Cyclone?

Good luck,

    Marc

Article: 67337
Subject: Re: HOW to Increase jitter in ALTERA PLL ?
From: Jakab Tanko <jtanko@ics-ltd.com>
Date: Wed, 10 Mar 2004 08:43:11 -0500
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> That's hitting below the belt!
> 
> I think the motivation here is for randomness.  I'd use a digital random number
> generator though, and just seed it with some random event.  You might do  consider
> using a ring oscillator implemented in the fabric (which will be sensitive to
> temperature, process and supply voltage) along with your externally applied clock
> to get a random seed.
> 
> 
> 
> Jakab Tanko wrote:
> 
> 
>>john wrote:
>>
>>>Hi,
>>>
>>>Is somebody know how to increase the jitter in a PLL integrated in a FPGA ??
>>>
>>>Thanks in advance...
>>
>>For thr Altera PLL just power it up, that will do the trick :-)
>>---
>>jakab
> 
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
> 
> 
Sorry, didn't mean it that way, it was meant to be a little
on the funny side more than anything else;
---
jakab


Article: 67338
Subject: Re: Can `protect-ed Verilog codes be synthesized with Xilinx XST?
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Wed, 10 Mar 2004 22:10:20 +0800
Links: << >>  << T >>  << A >>
well, i found it is for Verilog-XL...I met problems because I saved the file
in DOS format
but tried to simulate in Unix and VXL flagged error...

Thank you all for your suggestion.

Best Regards,
Kelvin




"Andy Peters" <Bassman59a@yahoo.com> wrote in message
news:9a2c3a75.0403091054.69837fe2@posting.google.com...
> "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message
news:<404d756d@news.starhub.net.sg>...
> > well, maybe that is why i couldnt simulate the Samsung SmartMedia model
with
> > Modelsim...
> > How do I find out which is the right simulator?
>
> Call Samsung?
>
> --a



Article: 67339
Subject: Re: novice for FPGA
From: johnjakson@yahoo.com (john jakson)
Date: 10 Mar 2004 06:13:01 -0800
Links: << >>  << T >>  << A >>
"Tong" <nospam@cuhk.edu.hk> wrote in message news:<c2km7a$ko9$1@justice.itsc.cuhk.edu.hk>...
> hi all,
> 
> I am a undergraduate studying VLSI and Magic manul layout. My professor have
> asked us to design an FPGA chip using Magic.
> I am confused in how to build the switch box and look up table. Could anyone
> kindly recommend some website or books that gives detail explanation on
> these stuff.
> 
> Thanks a lot.
> 
> Regards,
> Tong

Well you could either start by building a family of small srams and or
shift registers with a 16 way mux. With the mux inputs you can now
bring in 4 logic signals to get an output. The routing architecture is
clearly the difficult part isn't it. Like building a telephone network
that allows most users to be online at same time.

I think its a fair enough project to get some insight into the
complexity of these things, makes you think. Or you could just visit
some websites and think about what it would take to do circuit design
for CLBs you might find drawings of. These days the routing boxes
don't seem to get described like the old 4000 parts, wonder why.
(Don't answer that)

At the very least you can learn about sram design.

johnjakson_usa_com

Article: 67340
Subject: Re: LVDS
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Thu, 11 Mar 2004 01:34:14 +1100
Links: << >>  << T >>  << A >>
On Wed, 10 Mar 2004 10:10:19 +0100, Thomas Kurth
<thomas.nospam@gmx.net> wrote:

>Hi Allan,
>
>In comp.arch.fpga, Allan Herriman said...
>> I suggest you look at Ethernet PHYs.  They are cheap, readily
>> available, simple to interface to your FPGA, and will work reliably at
>> 100Mb/s over 100m of cat5.  They also take care of scrambling and
>> coding such that you effectively have a 100Mb/s clear channel
>> end-to-end.
>> 
>> E.g. LXT972A
>> http://www.intel.com/design/network/products/ethernet/linecard_ept.htm
>
>Thanks for the hint. We have to transmit very low amounts of data (17 
>Bit adress, 16 Bit Data). Our idea was to create our own protocol, which 
>has just a little overhead to secure the data. I have not yet understood 
>what the scrambler/descrambler does. It does not produce the whole 
>ethernet protocol, does it? 

No.  Framing, etc. is the job of the MAC.  The PHY just has the line
drivers, equalisers, symbol timing recovery, etc.  The PHY also
contains a 4B/5B coder, which converts groups of 4 bits at 100Mb/s
into groups of 5 bits at 125Mb/s and vice versa.  The groups of 5 bits
are DC balanced (which allows transmission though transformers without
too much baseline wander) and guarantee a minimum transition density,
which makes clock recovery possible.

(Note that your LVDS solution will also need to have some sort of line
coding to allow clock recovery to work.)

>Isn't it possible to use just the cat5 cable 
>and the Ethernet coils? Can I connect the coil directly to the FPGA? 

Um, no.  Actually you can, provided that you have a short transmission
line.  You are interested in long lines, however.

>How much is the PHY you proposed? 

Not much, as they are made in huge quantities.  You have to balance
that against the cost of implementing the equivalent functional blocks
inside an FPGA.  The dedicated PHY ASIC will have better performance
than your FPGA solution though.

If you really do need 1km reach, I recommend an optical solution.

>What else do I need to have it working? 
>Sorry for these maybe silly questions, but I never designed an Ethernet 
>connection before. Thanks for your help.

I suggest you start reading the datasheets for some PHYs to get an
idea of how to use them.

Regards,
Allan.

Article: 67341
Subject: Re: Using ALTPLL
From: "Christos" <chris_saturnNOSPAM@hotmail.com>
Date: Wed, 10 Mar 2004 15:36:30 +0100
Links: << >>  << T >>  << A >>

> You can take the 50 mhz clock into a 2 bit counter and take the output
> of the MSB for 12.5 MHz. This can drive a global clock tree within the
> device to minimize skew between all registers driven by the 12.5 MHz.
> The only drawback is that you will have some skew between the 50 mhz
> and 12.5 mhz domains, so you need to be careful with data transfers
> across the domains.
>
> Or you could take a 25 MHz PLL output and divide by 2 with a TFF. A
> variety of options here.
>
> Sincerely,
> Greg Steinke
> gregs@altera.com
> Altera Corporation


Hi all,

Since I am not an expert user I have a couple of questions on the above.

<This can drive a global clock tree.. > how do you configure this?
With the Assignment Editor?

If in the top-level schematic ( I use mostly schematics were some of its
blocks are in VHDL) you ask from the Assignment Editor to set for example
the CLK pin as a global clock then everything connected with this pin below
in the hierarchy will be by this global tree lines? or do I have to go one
by one the steps below to configure with the assignment editor the clock
input as global line?

It sounds logical only the first but had to ask.

Thanks for your time.



Article: 67342
Subject: Re: fpga
From: "John Adair" <newsreply@loseinspace.co.uk>
Date: Wed, 10 Mar 2004 14:47:12 -0000
Links: << >>  << T >>  << A >>
If it is a 4010E part based board then you are going to have to go back many
editions of software to get support. I don't think that any of the Webpack
software versions will support this kit.
-- 
John Adair
Enterpoint Ltd.
http://www.enterpoint.co.uk

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.


<sirohi_rajiv@rediffmail.com> wrote in message
news:c8cb1645.0403100402.41ec53ab@posting.google.com...
> hello all.
> i am working with xilinx ise webpack 6.2.
> i want to know that how i can upload my program on "xilinx xc4010e" kit.
> i am in great trouble so please help me.
> thanking you.
> rajiv



Article: 67343
Subject: Re: licence for Xilinx 2.1i
From: pildistaja@hotmail.com (Raivo Nael)
Date: 10 Mar 2004 06:54:02 -0800
Links: << >>  << T >>  << A >>
sona_singh@yahoo.com (manmohan singh) wrote in message news:<ce2407dc.0403092318.70c56ea5@posting.google.com>...
> Dear Sir,
> 
> As suggested by you I have downloaded the webpack from the Xilinx
> website but how to set the options for the device XC4010E and
> FPGA3142. Forgive me for my ignorance. kindly help me.
> 
> regards and thanks
> 
> "B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:<pan.2004.03.07.15.46.31.684698@polybus.com>...
> > On Sun, 07 Mar 2004 06:38:15 -0800, manmohan singh wrote:
> > 
> > > Hi All,
> > > Greetings,
> > > 
> > > I am a student. I found Xilinx 2.1i version software but I think
> > > Licence is expired. Can anybody give me the information from where I
> > > can get the licence (preferably free because as student I don't have
> > > much funds)
> > > 
> > > regards and thnaks
> > 
> > You don't want to use 2.1 for anything it's an antique. Xilinx offers
> > webpack which is a free version of their tools. Webpack is a subset but
> > it's probably sufficient for your needs. If you want to use the full set
> > of tools you should have your EE department contact the local Xilinx sales
> > office, I suspect that they would be happy to provide a free or
> > discounted version of their tools to you University.

You encountered the problem that about once in month emerges here and
there is no solution. Xilinx does not want you do use their older
devices and so you probably will not get any help here. Only solution
is to find some hacker who knows about old Xilinx stuff or you have to
use only newest soft and newest chips.

Using new chips is not bad (this is only solution if you wish to
design something for production). But if you simply wish to do some
funny thing for yourself then you see that newer chips are much more
expensive to get in any reasonable quantities and these BGAs and very
thin flat packs are pain to use if you wish to make your board at
home.

nevertheless good luck

Raivo

Article: 67344
Subject: Re: Very strange Xilinx timing report.
From: "John Adair" <newsreply@loseinspace.co.uk>
Date: Wed, 10 Mar 2004 14:57:46 -0000
Links: << >>  << T >>  << A >>
Depending on how much you have to change you could consider using a 36MHz
clock with clock enables to mimic 12MHz and 4MHz. You won't have issues
between these effective frequencies then. If the 40MHz has some registers on
it directly you could consider crossing the clock boundaries using negative
edge for source reg and positive edge for rising. Makes the gap a reasonable
number of  nano-seconds as opposed to pico-seconds. The timing tools should
be able to cope with buffer delays etc when generating the 36 MHz.
-- 
John Adair
Enterpoint Ltd.
http://www.enterpoint.co.uk

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.

"Stephan Neuhold" <stephan.neuhold@xilinx.com> wrote in message
news:404F052D.55C42D83@xilinx.com...
> Hi Kelvin,
>
> This is a problem with the Timing analyzer when encountering subpicosecond
> values. Derived timing constraints or the like may end up having
subpicosecond
> values due to multiplication and division in the DCM, etc.
>
> You can either choose a input clock period value that will not go into the
> subpicosend range due to these multiplications or division but rather stay
in
> the ps range. Alternatively you can also choose different values for the
> multiplication and division factor so that you do not end up having
> subpicosecond values but this is usually more difficult to achieve.
>
> --Stephan
>
>
>
> "Kelvin @ SG" wrote:
>
> > Hi, there:
> >
> > I am synthesizing a design with 12 & 4MHz and 36MHz clock from two
different
> > DCMs, but
> > I made them synchronize to same input 40MHz clock. However, I got this
type
> > of odd
> > timing errors. How may I correct such problem?
> >
> > Best Regards,
> > Kelvin
> >
> > Asterisk (*) preceding a constraint indicates it was not met.
> >    This may be due to a setup or hold violation.
> >
>
> --------------------------------------------------------------------------
--
> > ----
> >   Constraint                                | Requested  | Actual     |
> > Logic
> >                                             |            |            |
> > Levels
>
> --------------------------------------------------------------------------
--
> > ----
> >   TS_exahb_clk_1m_sdr = PERIOD TIMEGRP "exa | 1000.000ns | 5.550ns    |
2
> >   hb_clk_1m_sdr" 1000 nS HIGH 50.000000  %  |            |            |
>
> --------------------------------------------------------------------------
--
> > ----
> >   TS_exahb_clk_12m_sdr = PERIOD TIMEGRP "ex | 83.333ns   | 16.065ns   |
16
> >   ahb_clk_12m_sdr" TS_exahb_clk_1m_sdr /  1 |            |            |
> >   2.000000 HIGH 50.000 %                    |            |            |
>
> --------------------------------------------------------------------------
--
> > ----
> >   TS_clk_40m_w = PERIOD TIMEGRP "clk_40m_w" | N/A        | N/A        |
N/A
> >     25 nS   HIGH 50.000000 %                |            |            |
>
> --------------------------------------------------------------------------
--
> > ----
> >   TS_clk_36m_rx = PERIOD TIMEGRP "clk_36m_r | 27.777ns   | 3.410ns    |
3
> >   x" TS_clk_40m_w / 0.900000 HIGH 50.000  % |            |            |
>
> --------------------------------------------------------------------------
--
> > ----
> > * TS_clk_4m_rx = PERIOD TIMEGRP "clk_4m_rx" | 250.000ns  | 164750.000ns
| 3
> >    TS_clk_40m_w * 10.000000 HIGH 50.000  %  |            |            |
>
> --------------------------------------------------------------------------
--
> > ----
> >   TS_clk_12m_rx = PERIOD TIMEGRP "clk_12m_r | 83.333ns   | 18.399ns   |
28
> >   x" TS_clk_40m_w / 0.300000 HIGH 50.000  % |            |            |
>
> --------------------------------------------------------------------------
--
> > ----
>



Article: 67345
Subject: Re: LVDS
From: Marc Randolph <mrand@my-deja.com>
Date: Wed, 10 Mar 2004 09:16:10 -0600
Links: << >>  << T >>  << A >>
Thomas Kurth wrote:

> Hi Klaus,
> 
> In comp.arch.fpga, Klaus Falser said...
> 
>>We are using LVDS together with a low capacitance cable of 10 m 
>>at 50 MHz clock, and my impression is that it is on it's limit. It is sensitive 
>>to disturbances and signal quality depends strongly on quality of the cable.
>>
>>If you really want to do it, do not forget to feed the GND signal too through 
>>the cable, since the common mode range of the differential receivers is not 
>>large enough for dealing with differences between the ground levels of 
>>transmitter and receiver.
>>
>>I seem to remember that somewhere on the National Semiconductor web pages there is 
>>a graph about data rates and covered distances.
>>
>>Convince your boss to use an optical link, you will have only advantages! They are not 
>>so complicated as it seems.
> 
> 
> Thanks for your help. I have already found the graph before and so I am 
> a little confused about your experience. On 
> http://www.maxim-ic.com/appnotes.cfm/appnote_number/1856/ln/en there is 
> table3 and figure7 which show the relation between cable lengths and 
> transmission rates. I found a reliable transmission over 60 ft (20 m) at 
> data rates of about 528 MBit. So your 10 m @ 50 MBit seem to be very 
> low... Factor 10 should be possible?
> 
> Concerning the optical solution. What do we need for such a thing and 
> what will it cost? Do you have any experience on this topic?

Howdy Thomas,

Before you can ask what it will cost, you have to know what your real 
requirement is.  Is it 10 meters or 1000 meters?  Is optical even an 
option (from a mechanical and product management standpoint)?  How much 
are you willing to pay?

There are lots of hungry optical transceiver companies out there 
(Opnext, OCP, Stratos, Finisar, JDSU, Molex, just to name a few of 
many).  After you nail down your needs, contact them.

Just so you know, we do STS-48 (2.5 Gbps SONET) over cable, at lengths 
exceeding 15 meters.  So, it's possible.

    Marc

Article: 67346
Subject: Re: Quartus II version 4 (Web Edition) DOES NOT WORK AT ALL !?
From: "Subroto Datta" <sdatta@altera.com>
Date: Wed, 10 Mar 2004 15:20:16 GMT
Links: << >>  << T >>  << A >>
Hi Antti,

   Just to make sure that everything is on the Altera web site is OK,  I did
the following:

1. Downloaded the Quartus II 4.0 Web Edition ( used the
quartuii_40_web_edition_single.exe download, all 144.7 MB of it),  installed
it on my PC,
2. Got myself a license from the Altera Licesning Center,
3. Compiled a one wire design, (input followed by lcell followed by output),
for the APEX20KE, Cyclone, Stratix, and MaxII families, both with Auto
Device Selection and Specifying a fixed Device (from the list shown in the
Assign Device Box).
4. Compiled the fir_filter Tutorial design

All without any problems.

Based on your description of the internal error, I believe your installation
was incomplete, and that some of your device databases may not been
installed. This may happen if you ran out of disk space during the
installation, or your downloaded image was corrupt. It is probably the
former. Give the installation a try again, and send me the results.


- Subroto Datta
Altera Corp.




"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0403100111.5b08404c@posting.google.com...
> Hi
>
> has anyone have had any luck with Quartus II ver 4?
>
> Internal Error: Sub-system: FYGR, File: fygr_global_utility.cpp, Line:
5797
> number_of_res == 0 || number_of_res == 1
> (Fitter pre-processing)
> Quartus II Version 4.0 Build 190 1/28/2004 SJ Web Edition
>
> the desing is one input routed to one output.
> all other projects fail as well including the
> tutorials from QII V4
>
> Altera: what is that? Measuring customers?
> How much bullshit can they take?
> If you cant make a software to work, DO NOT RELEASE IT!
> Hire people that can make it work, and TEST IT!
>
> v3 is now uninstalled and v4 completly fails!!!
> and I am really really really tired to submit service requests!
>
> Antti Lukats
>
> P.S.
> For Altera: for a short period of time I might be available
> for hiring, as my current contract ends 31.03.2004, I will
> be still busy in April preparing a OTG core ASIC tapeout,
> but after that I would be available. However the situation
> may change any day.
>
> P.P.S. the OTG core is AHB bus connected but instead of using
> Altera and NIOS (and NIOS avalon 2 AHB wrapper) we are
> using Microblaze with OPB to AHB wrappers. Those neverending
> problems with Altera tools have been one reason why we did
> not make the FPGA verification on NIOS board what also was
> available.
> I could change that (people abonding use of Altera products),
> if I get the chance!



Article: 67347
Subject: Re: very strange error
From: Jim Lewis <Jim@SynthWorks.com>
Date: Wed, 10 Mar 2004 07:31:56 -0800
Links: << >>  << T >>  << A >>
Bruno,
I can make a couple of guesses.  If this does not help,
you may need to post the code.  In the design HdpStrSafePX,

-- Array definition has no elements:
signal Str2 : std_logic_vector(0 downto 1) ;

--  Constant has no value
constant Str2 : string (10 downto 0) ;

Again, these are just guesses, to get it right
most of us need to see the code.

Cheers,
Jim
-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


Bruno Vermeersch wrote:

> Hi everybody,
> 
> I'm rather new to the whole VHDL business but I'm surrounded by good 
> helpfull people. Yesterday I wrote a short block which has caused us al 
> headaches. The error I get after "Syntax check" is:
> 
> Started process "Check Syntax".
> 
> =========================================================================
> 
> # HDL Compilation * 
> =========================================================================
> Compiling vhdl file c:/bruno/tb/test.vhd in Library work.
> ERROR:HDLParsers:3214 - HdpStrSafeCatPX: Str2 is NULL
> ERROR: XST failed
> Process "Check Syntax" did not complete.
> 
> anybody who can help us out?
> 
> thx in advance
> 
> Bruno


Article: 67348
Subject: xilinx jtag problems
From: topfuel1015@comcast.net (warren)
Date: 10 Mar 2004 07:40:03 -0800
Links: << >>  << T >>  << A >>
I have been going nuts with a Spartan 2 and 18v04 during configuration
with a JTAG cable (III) and impact 6.1.

1. The mode pins are set for boundary scan.
2.  If I run the cable with a 5v reference:
   a. Chain initialization will succeed 99% of the time.
   b. EPROM programming/verify will succeed 95% of the time.
   c. FPGA programming/verify will fail verify 100% of the time and
the FPGA is left with what appears to be wrong IOB configuration;
starts drawing a great deal of power.
   d. If I run IDCODE looping, it will fail before my defined 1000
loops are completed.
3. If I run the cable with 3.3v reference (which it should be anyway),
I cannot get through the Chain initialization ever. I get
up to 10 unknown devices reported.

I have pulled out a previously designed board and reprogrammed it
without any problems, to verify the software/drivers/cables.

I have checked for noise on the power and JTAG lines, didn't find
anything alarming.

If anyone has any suggestions, your input would be GREATLY
appreciated.


Thanks!

(reposted to get a new thread)

Article: 67349
Subject: Re: xilinx configuration problem
From: topfuel1015@comcast.net (warren)
Date: 10 Mar 2004 07:42:49 -0800
Links: << >>  << T >>  << A >>
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<404ea276@news.starhub.net.sg>...
> Do spartan-2 and JTAG support readback and verify?
> 
> Kelvin
> 
> 
I never had a problem on other boards I have developed.
> 
> 
> warren <topfuel1015@comcast.net> wrote in message
> news:86732d3d.0403092000.656c2ac3@posting.google.com...
> > I have been going nuts with a Spartan 2 and 18v04 during configuration
> > with a JTAG cable (III) and impact 6.1.
> >
> > 1. The mode pins are set for boundary scan.
> > 2.  If I run the cable with a 5v reference:
> >    a. Chain initialization will succeed 99% of the time.
> >    b. EPROM programming/verify will succeed 95% of the time.
> >    c. FPGA programming/verify will fail verify 100% of the time and
> > the FPGA is left with what appears to be wrong IOB configuration;
> > starts drawing a great deal of power.
> >    d. If I run IDCODE looping, it will fail before my defined 1000
> > loops are completed.
> > 3. If I run the cable with 3.3v reference (which it should be anyway),
> > I cannot get through the Chain initialization ever. I get
> > up to 10 unknown devices reported.
> >
> > I have pulled out a previously designed board and reprogrammed it
> > without any problems, to verify the software/drivers/cables.
> >
> > I have checked for noise on the power and JTAG lines, didn't find
> > anything alarming.
> >
> > If anyone has any suggestions, your input would be GREATLY
> > appreciated.
> >
> >
> > Thanks!



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2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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