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Messages from 65425

Article: 65425
Subject: Re: Flip-Chip Package Substrate Solder Issue
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 28 Jan 2004 12:04:44 -0800
Links: << >>  << T >>  << A >>
Emile,

Just so you have the facts, we have 100 2V6000's from the affected lot, 
that are at 12 upsets in 44,496 device hours of operation.  It takes 
from 6 to 40 flips to cause a functional fail (on average over many 
customer designs).  Assuming 10 flips on average, that makes the mean 
time to fail 4.2 years (approx).  Could be half that on average, to more 
than four times that, on average.

Austin

Emile wrote:
> My Xilinx distributor shipped an affected lot to us and we are now in
> a line-down situation.  We've been told that lead-time is 10 weeks. 
> I'm looking for 50 XC2V6000-4BF957C from an unaffected lot.  Thanks.


Article: 65426
Subject: Hot2 configuration
From: fabio.matos@terra.com.br (Fabio de Matos Gon?alves)
Date: 28 Jan 2004 12:40:25 -0800
Links: << >>  << T >>  << A >>
Hi,

I have been in troubles when configuring Xilinx FPGA's. It seems to
end up not properly configuring the boards in some scenarios.

My system is a linux 2.2.x and 2.4.x, and i use HOT2 boards, by VCC -
featuring Spartan 2 and XCS40 XLA with PCI interfaces - in 8 machines
of a cluster. Configuration happens by PCI access. After they are off
for a while, on first boot, almost none of the machines can succeed
configuring the boards. When i hard reboot the ones that didn't, some
of it can succeed configuring. If i need all machines working, this
process goes on for quite a long time. What happens is that all memory
positions contain 0xff, as far as i look.

Quoting Steve Casselman on earlier messages ( back in 1999 ) , there
is a mechanism that brings these boards to a known state when
configuration errors are detected.

This behaviour seems to happen only in some motherboard models. On
others, i have never seen it happening - although never tried it hard
enough.

This problem asks far more observation than i can manage. Because
failures take a long time to happen ( altough too often to be
tolerable ), only after a few months of errors I could really start
understanding what was going on.

Any related problems should help. 

Anyway, what is happening to vcc.com site?

Article: 65427
Subject: Re: Flip-Chip Package Substrate Solder Issue
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Thu, 29 Jan 2004 05:38:23 GMT
Links: << >>  << T >>  << A >>
"Austin Lesea" wrote:

> mean time to fail 4.2 years (approx).

So, if the product in question is not operating 24/7 (powered on/off on a
daily basis or when it gets used) the failure in question is as good as
non-existent?


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 65428
Subject: Re: building macros for Virtex-II with FPGA editor...
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Thu, 29 Jan 2004 13:53:48 +0800
Links: << >>  << T >>  << A >>
Bret
may I know the "documented hard macro flow"? Is it an application note or
what?
Does the RPMs allow going parameteric? I guess a Bus Macro with a variable
bus width is better than the current 4-bit bus...

Otherwise I may merge a lot of bus macros to make 32-bit or 64-bit Bus
Macros...
It's really troublesome to instantiate many Bus Macros...


Kelvin





Bret Wade <bret.wade@xilinx.com> wrote in message
news:465bd4b1.0401281033.6e9d867e@posting.google.com...
> simon <ssteineg@ee.ethz.ch> wrote in message
news:<40177bdc$1@pfaff2.ethz.ch>...
> > Hello Bret,
> > I just read some xilinx documents about RPMs and Directed routing. I'm
> > not quite sure if these are useful in my case. I'm working on a
> > dynamically partial reconfigurable design and I want to model
> > communication lines across reconfigurable modules as hard macros. I
> > assume that this will prevent (or rather minimize) discontinuation of
> > the signal flow when the module is reconfigured.
> >
> > Regards,
> > Simon
>
> Hello Simon,
>
> I don't see why Directed Routing constraints couldn't replace the
> functionality of the Bus Macro in the partial reconfig flow, but since
> the penalty for not doing exactly the right thing is higher there, I
> recommend staying with the documented hard macro flow. If you do try
> the Directed Routing method, pay attention to the section in the .par
> file that tells you if all the DIRT constraints were successfull.
>
> Regards,
> Bret



Article: 65429
Subject: Re: Altera Active Serial
From: antti@case2000.com (Antti Lukats)
Date: 28 Jan 2004 23:43:35 -0800
Links: << >>  << T >>  << A >>
Ben Popoola <b.popoola@ntlworld.com> wrote in message news:<wBoQb.11$WQ3.10@newsfep1-gui.server.ntli.net>...
> Khim Bittle wrote:
> > hi folks ... when using the Cyclones with the EPCS4 flash
> > configuration chip and active serial mode ... I'd like to use the
> > extra memory space to store a memory image ... so all I need to do is
> > read or write it in a big block .. so yes i have done this with Nios
> > but this is too much overhead in a small cyclone device simply to copy
> > an image from the flash to an external ram  .. anyone know how to read
> > the flash without using nios ?  kb
> > 
> Hi Khim,
> 	As I understand things, the Altera flash memory devices are based upon 
> standard serial flash devices  (ST microelectronics ?). Hence you would 
> program these devices as you would any normal serial memory device. You 
> only have yo be careful that you do not overwrite your configuration data.

EPCS1 == M25P10
EPCS4 == M25P40

standard serial flash from www.st.com
altera is only ordering them them with custom lables printed :)

the problem accessing the config memory from non-nios applications is that
quartus doesnt allow assignments to pins DATA0 and DCLK so it is not 
possible to access the config flash memory.

there must be some internal trick that altera software uses but this
seems to be "Altera undocumented"

Antti Lukats
xilin.openchip.org

Article: 65430
Subject: jBits RouteClock
From: simon <ssteineg@ee.ethz.ch>
Date: Thu, 29 Jan 2004 09:55:16 +0100
Links: << >>  << T >>  << A >>
Hello,
Is there anyone who has successfully applied com.xilinx.util.RouteClock?

I applied RouteClock to a full bitstream as you suggested. But
unfortunately this seemed to have some side-effect, which led to
malfunctioning of the bitstream. I programmed a tool which
re-translated the bitstreams to the commands described in xilinx's
virtex-II user guide and encountered some differences. I hope you can
help me find the reason for the malfunctioning:

1.
before:
...
3000C001  MASK            Masking Register for CTL
00000008                  MASK Register value
30008001  CMD             Write to Command Register
00000009  SWITCH          Switch CCLK Frequency
30002001  FAR             Frame Address Register
00000000                  Frame Address
30008001  CMD             Write to Command Register
00000001  WCFG            Write Config Data
30004000  FDRI followed by Type 2 Packet Header
5004926E  TYPE2           Word Count = 299630
00000000                  Data Word 1
00000000                  Data Word 2
...

after RouteClock: CTL register write moved down to the end of the
bitstream, CMD SWITCH vanished, the FDRI command seems to have changed
to "04804000" - what's the meaning of that command?:
...
3000C001  MASK            Masking Register for CTL
00000008                  MASK Register value
3000A001  CTL             Control Register
00000008                  Control Register value
30002001  FAR             Frame Address Register
00000000                  Frame Address
30008001  CMD             Write to Command Register
00000001  WCFG            Write Config Data
04804000
5004926E
00120480
00000000
00000000
...

2.
before:
(config data)...
00000000                  Data Word 299629
00000000                  Data Word 299630
0000DEFC
30008001  CMD             Write to Command Register
0000000A  GRESTORE        Pulse GRESTORE Signal
30008001  CMD             Write to Command Register
00000003  DGHIGH          De-asserts GHIGH
20000000
20000000
...

after RouteClock: CMD GRESTORE moved to the end, some FAR FDRI (data) 
commands are added - I guess there lies the clock net routing information:
(config data)...
00000000
00000000
0000DEFC
30008001  CMD             Write to Command Register
00000003  DGHIGH          De-asserts GHIGH
20000000
20000000

3.
before:
...
20000000
20000000
30008001  CMD             Write to Command Register
00000005  START           Begin STARTUP Sequence
3000A001  CTL             Control Register
00000008                  Control Register value
30000001  CRC             CRC Register
0000DEFC                  CRC Register value
30008001  CMD             Write to Command Register
0000000D  DESYNCH         Forces Realignment to 32 bits
20000000
20000000
20000000
20000000
(end of bitstream)

after RouteClock: GRESTORE is now located here, while the CTL command
setting the "persist" flag is at the beginning of the bitstream...
...
00000000                  Data Word 497
00000000                  Data Word 498
0000DEFC
30008001  CMD             Write to Command Register
0000000A  GRESTORE        Pulse GRESTORE Signal
30008001  CMD             Write to Command Register
00000005  START           Begin STARTUP Sequence
30000001  CRC             CRC Register
0000DEFC                  CRC Register value
30008001  CMD             Write to Command Register
0000000D  DESYNCH         Forces Realignment to 32 bits
20000000
20000000
20000000
20000000
(end of bitstream)

Well, i hope i didn't provide too much unnecessary information. If
someone needs more information to be able to help please post a reply.

Thanks in advance for your support
Simon


Article: 65431
Subject: Re: Asking about FPGA-SPARTAN error in synthizer
From: "John Adair" <newsreply@loseinspace.co.uk>
Date: Thu, 29 Jan 2004 10:48:25 -0000
Links: << >>  << T >>  << A >>
I have seen similar things generated by synthesisers When this has been the
problem the net is driven by the output of a lut. The lut has a constant
value output and has no inputs. To find if this is the problem use FPGA
EDITOR to look at the design, select the net from the list window and use
the attrib button to bring up the pop-up window. Then select the pins tab
and you will see the output and inputs of the net.

If this is your problem check to see if you are synthesising for the correct
part. This sort of structure is sometimes valid in families without built-in
pull elements. Otherwise try and change your logic, or synth options, to get
a different synthesis that might not have the problem.

John Adair
Enterpoint Ltd.

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.


"H.Azmi" <haythamazmi@hotmail.com> wrote in message
news:34c5542c.0401280550.78f8ee0e@posting.google.com...
> what can cause this error :
> ERROR: a gnd net is driven by primitive gate(s) --  NET: GND0
> ???



Article: 65432
Subject: Re: Good/Affordable Stater kits
From: "StoneCold" <ihatespam@nospam.net>
Date: Thu, 29 Jan 2004 17:13:08 +0530
Links: << >>  << T >>  << A >>
Hi,

Does anyone have any idea regarding clock multiplication using all-digital
PLLs?
I am designing one system where I need to multiply clock frequencies on a
FPGA, but I would like to use all-digital components.
(without any analog components, preferably).
I trid a lot to get some good reference on the internet, but have failed
miserably. No one seems to have done it, but no one even said that it cannot
be done.
If anyone has relevant experience in this domain,  please suggest and
advise.

-Deepak
----------------------------------------------------------------------------
------------
Life is like a see-saw , with success and failure being
the two ends. Both of them come in succession, neither
of them is continuous.
----------------------------------------------------------------------------
--------------------

"Vaughn Betz" <vbetz@altera.com> wrote in message
news:48761f7f.0401202112.526e08bc@posting.google.com...
> x86asm <isaac_8e@hotmail.com> wrote in message
news:<45YOb.12249$7JB1.3852@news04.bloor.is.net.cable.rogers.com>...
> > Hi guys, I was wondering if there were any good starter kits you know of
> > and where I am able to purchase them, I want to dip into VHDL a bit and
> > try out my creations on a FPGA, nothing too fancy as I'm no engineer,
> > just a hobbyist :) I saw one on Xilinx's online store for ~$50 US is
> > that a good choice?
>
> See http://www.altera.com/products/devkits/kit-dev_platforms.jsp for a
> listing of Altera's development boards.  The $99 7K board and $195
> Cyclone board are good choices for someone on a budget.  The Cyclone
> board has a better (bigger & faster) FPGA on it, but for hobby
> projects you likely want to focus at least as much on the board I/O
> capabilities as you do on the FPGA on the board.  So it's good to look
> at the list of what's on the board and see if it meets your I/O needs.
>
> As other posters have pointed out, there's no shortage of dev kits at
> pretty low prices out there.
>
> The cheapest solution of all to get some experience is just to
> download a CAD suite and start synthesizing & simulating without a
> development kit.
> You can get the web edition of Quartus for free from
>
http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmai
n.html.
>
> Regards,
>
> Vaughn
> Altera



Article: 65433
Subject: FPGA basics
From: "Arcadius A." <ahouans@sh.cvut.cz_NOSPAM>
Date: Thu, 29 Jan 2004 13:00:56 +0100
Links: << >>  << T >>  << A >>
Hello!
Please, I'm looking for documents/URLs explaining the basics of FPGA, 
and how FPGA work.
I've done a google search, but I couldn't find any thing simple enough 
for me to get the idea.

All I need is the base architecture, the logic components used, and how 
the whole works.

Thanks.

Arcadius.

Article: 65434
Subject: pci-x core/ XC2VP/ pin capacitance
From: Matthias =?iso-8859-1?Q?M=FCller?= <spam*mur@iis.fhg.de>
Date: Thu, 29 Jan 2004 13:20:44 +0100
Links: << >>  << T >>  << A >>
Hallo,
I will implement a PCI-X core in a XC2VP7, the pin capacitance of which
is 10 pF. The PCI-X specification requires a pin capacitance of 8 pF.
Does anyone know if there will be serious problems for operation  with
133MHz?
Thank you for answers,
Matthias


Article: 65435
Subject: what is back annotation
From: raghurash@rediffmail.com (Raghavendra)
Date: 29 Jan 2004 04:52:16 -0800
Links: << >>  << T >>  << A >>
Hi All,
   Please anyone explain in detail about back annotation.
Thanks in advance+regards,
Raghavendra

Article: 65436
Subject: Power extimation?
From: raghurash@rediffmail.com (Raghavendra)
Date: 29 Jan 2004 04:53:44 -0800
Links: << >>  << T >>  << A >>
Hi All,
How to manually estimate dynamic power consumption of the design in the FPGA?
Thanks in advance,
Raghavendra.S

Article: 65437
Subject: Re: OT: Flash memory problem on Spirit?
From: rk <stellare@NOSPAMPLEASE.erols.com>
Date: 29 Jan 2004 13:01:45 GMT
Links: << >>  << T >>  << A >>
In general, it turns out that the storage element in flash is reasonably 
robust to radiation.  The sensitive parts are often in the control areas or 
temporary registers, where a single heavy ion can cause a lockup of internal 
state machines or an "upset" in say an address or data holding register.  In 
some cases the lockups require a full power cycle to clear.

Bob wrote:

> This appears to be the latest thinking, from NASA.
> 
> Flash seems like it would be fairly susceptible to radiation.
> 
> Does anyone know if any other inter-planetary craft have utilized this
> technology?

-- 
rk, Just an OldEngineer
"For a successful technology, reality must take precedence over public 
relations, for nature cannot be fooled."
-- R. Feynman, Appendix F.

Article: 65438
Subject: Is FPGA fully static?
From: pildistaja@hotmail.com (Raivo Nael)
Date: 29 Jan 2004 05:46:05 -0800
Links: << >>  << T >>  << A >>
If i wish for debuging purposes lower clock frequency that i supply
for FPGA from external source can i always do it?

For example if i have borad that is intended to run with 40MHz
external clock source and for debuging purposes i will supply 40 Hz
clock, does circuit behave exactly as on higher speed expect that all
happens 1 000 000 x slower or is this situation more complicated?

regards,
Raivo

Article: 65439
Subject: Re: FPGA basics
From: "David Brown" <david@no.westcontrol.spam.com>
Date: Thu, 29 Jan 2004 14:53:54 +0100
Links: << >>  << T >>  << A >>

"Arcadius A." <ahouans@sh.cvut.cz_NOSPAM> wrote in message
news:bvaslp$u6s$1@ns.felk.cvut.cz...
> Hello!
> Please, I'm looking for documents/URLs explaining the basics of FPGA,
> and how FPGA work.
> I've done a google search, but I couldn't find any thing simple enough
> for me to get the idea.
>
> All I need is the base architecture, the logic components used, and how
> the whole works.
>
> Thanks.
>
> Arcadius.

You can't have tried googling very much if you've come up with nothing - try
searching for "fpga" and clicking on some of the links (including the
sponsered ones).  Try also:

http://www.optimagic.com/faq.html



Article: 65440
(removed)


Article: 65441
Subject: V2Pro & PCI Problem?
From: "Ron Huizen" <rhuizen@bittware.com>
Date: Thu, 29 Jan 2004 08:54:33 -0500
Links: << >>  << T >>  << A >>
One of our guys just returned from a Xilinx training class where a
supposedly informed source stated that the V2Pro somehow breaks PCI support,
i.e. you can't implement a proper PCI interface in them.

Anyone heard anything about this?

------
Ron Huizen
BittWare



Article: 65442
Subject: Re: Is FPGA fully static?
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Thu, 29 Jan 2004 08:56:29 -0500
Links: << >>  << T >>  << A >>
On Thu, 29 Jan 2004 05:46:05 -0800, Raivo Nael wrote:

> If i wish for debuging purposes lower clock frequency that i supply
> for FPGA from external source can i always do it?
> 
> For example if i have borad that is intended to run with 40MHz
> external clock source and for debuging purposes i will supply 40 Hz
> clock, does circuit behave exactly as on higher speed expect that all
> happens 1 000 000 x slower or is this situation more complicated?
> 
> regards,
> Raivo

The DCMs in Xilinx parts have a minimum frequency requirement, it's in the
neighborhood of 25MHz. If you want to use a slow clock you can't use the
DCMs, you will have to use the input clock directly.



Article: 65443
Subject: Re: Flip-Chip Package Substrate Solder Issue
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 29 Jan 2004 08:00:26 -0800
Links: << >>  << T >>  << A >>
Martin,

Excellent point.  If the unit is reconfigured (doesn't even have to be 
powered off) it does not change the probability, but it will prevent 
upsets from acumulating bit flips (lessening probability of functional 
fail), as well as lessening the time of the outage, or the probability 
that an outage is even noticed.

Austin



Martin Euredjian wrote:
> "Austin Lesea" wrote:
> 
> 
>>mean time to fail 4.2 years (approx).
> 
> 
> So, if the product in question is not operating 24/7 (powered on/off on a
> daily basis or when it gets used) the failure in question is as good as
> non-existent?
> 
> 


Article: 65444
Subject: Re: FPGA basics
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Thu, 29 Jan 2004 11:32:36 -0500
Links: << >>  << T >>  << A >>
On Thu, 29 Jan 2004 13:00:56 +0100, Arcadius A. wrote:

> Hello!
> Please, I'm looking for documents/URLs explaining the basics of FPGA, 
> and how FPGA work.
> I've done a google search, but I couldn't find any thing simple enough 
> for me to get the idea.
> 
> All I need is the base architecture, the logic components used, and how 
> the whole works.
> 
> Thanks.
> 
> Arcadius.

Goto the Xilinx an Altera sites and download the datasheets for a couple
of FPGA families. 

Article: 65445
Subject: Re: what is back annotation
From: "fabbl" <yttt@nukes.com>
Date: Thu, 29 Jan 2004 16:36:15 GMT
Links: << >>  << T >>  << A >>
During a non-deterministic process step information is generated. This
information is usually the result of implementation in some step of the FPGA
(usually timing, sometimes labels or logic).  This added information may be
used in a previously created step (ie simulation) . The information is
"back-annotated" and this information makes the simulation (in this case)
more accurate.

"Raghavendra" <raghurash@rediffmail.com> wrote in message
news:1776d39.0401290452.3ff67936@posting.google.com...
> Hi All,
>    Please anyone explain in detail about back annotation.
> Thanks in advance+regards,
> Raghavendra



Article: 65446
Subject: Re: Power extimation?
From: "fabbl" <yttt@nukes.com>
Date: Thu, 29 Jan 2004 16:41:54 GMT
Links: << >>  << T >>  << A >>
Xilinx has a power estimator utility for their parts. Some other vendors may
have suggestions as well. try contacting their FAE's. By default their are
no "one-size-fits-all" models, only estimations, worse/best case etc.

"Raghavendra" <raghurash@rediffmail.com> wrote in message
news:1776d39.0401290453.3bd7cbe9@posting.google.com...
> Hi All,
> How to manually estimate dynamic power consumption of the design in the
FPGA?
> Thanks in advance,
> Raghavendra.S



Article: 65447
Subject: Showing design in vpr
From: BrakePiston <brakepiston@REMOVEyahoo.co.uk>
Date: Thu, 29 Jan 2004 16:42:14 +0000
Links: << >>  << T >>  << A >>
Hi there, a question about VPR:

If I have the output of the placement and the routing, how can I see
them on screen without having to recompute it all?

Thanks!!



Article: 65448
Subject: Re: building macros for Virtex-II with FPGA editor...
From: Ray Andraka <ray@andraka.com>
Date: Thu, 29 Jan 2004 12:01:46 -0500
Links: << >>  << T >>  << A >>
Not sure if this helps, as I'mnot entirely clear on what you are attempting to
do:  You might try the more conventional RPM approach where you put RLOCs on
the instances (Tbufs in your case?) to place but not route the primitives.
Given a good placement, the router will usually find a solution that meets
timing.  Prior to ISE 4, given a good placement, the router did a great job.
versions 4 and 5 had some laziness in the router that led to less than optimal
routes.  I have not fully evaluated the results in version 6, but it does seem
to be doing considerably better.  In any event, doing placement only lets you
do the macro layout using the conventional, well documented tools flow.  RLOCs
can either be entered in the ucf either manually or using the floorplanner, or
they can be embedded in your source code.  I prefer to embed them in the
source because it lets you build the macros, including placement,
hierarchically.  The ucf treats the design as flat, so you don't get the
reuse.   If you use VHDL, the ability to use the index variable in a
for..generate statement in the constant declarations lets you easily do step
and repeat type layouts.  Verilog doesn't have a mechanism to include the
generate index in the rloc strings.

>

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 65449
Subject: Re: Is FPGA fully static?
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 29 Jan 2004 09:07:18 -0800
Links: << >>  << T >>  << A >>
If you do NOT use the DCM, you can go as low as you want.
The DCM has a min input frequency of 25 MHz,( except for the FS mode
where the min output frequency is 25 MHz, and the input frequency can
then be significantly lower).

Peter Alfke, Xilinx
---------------------------
Raivo Nael wrote:
> 
> If i wish for debuging purposes lower clock frequency that i supply
> for FPGA from external source can i always do it?
> 
> For example if i have borad that is intended to run with 40MHz
> external clock source and for debuging purposes i will supply 40 Hz
> clock, does circuit behave exactly as on higher speed expect that all
> happens 1 000 000 x slower or is this situation more complicated?
> 
> regards,
> Raivo



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1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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