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Messages from 83075

Article: 83075
Subject: Re: What is the cause of a "can not see clock" problem in logic analyser?
From: Jerry Avins <jya@ieee.org>
Date: Fri, 22 Apr 2005 13:55:20 -0400
Links: << >>  << T >>  << A >>
Acceed See wrote:
> "Acceed See" <invalicd@hotmail.com> wrote in message
> news:4264e0ae$1@news.starhub.net.sg...
> 
>>My LA is agilent 16702. When I use the 400MHz internal clock to sample
>>the clock pin and the data pin with probes, I can see them nicely on the
> 
> LA,
> 
>>and positive edge of the clock is right in the middle of the data. When I
>>change
>>to sampling data with my external clock pin, LA told me the clock is too
>>weak
>>and can not see a clock in the top-right banner. Of course, I don't see
> 
> any
> 
>>data.
>>
>>What is the cause of that? How can I correct this?
>>
> 
> 
> 
> Any quick fix for those "It worked in simulation, but not in FPGA"
> nightmares?
> My design is 200K ASIC gates burned in an FPGA, it's so tiring to debug
> that.

What is the clock source? Is id overloaded or short on settling time?

Jerry
-- 
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ

Article: 83076
Subject: Re: VHDL or Verilog
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 22 Apr 2005 10:57:20 -0700
Links: << >>  << T >>  << A >>
"Erik Walthinsen" <omega@pdxcolo.net> wrote in message
news:d49r8402gi0@enews1.newsguy.com...
> Ray Andraka wrote:
> > Muslim or Christian.  Normally you have the choice of which you want to
> > follow.....
>
> I find my self speechless, shocked that this thread hasn't deteriorated
> into a lengthy battle of people talking past each other, calling names
> and so on.
>
> What's wrong with this group?  Am I on the wrong Usenet???
>
> <g>
http://www.googlefight.com/ resolves all these arguments!



Article: 83077
Subject: Re: ispTRACY-Lattice vs. SignalTap-Altera
From: "Peter Sommerfeld" <psommerfeld@gmail.com>
Date: 22 Apr 2005 11:25:57 -0700
Links: << >>  << T >>  << A >>
I know you can add other clocks to the list of nodes in SignalTap, and
that compiles fine. Do their traces not appear in the Data screen? For
some reason I thought I had done that in the past. Or maybe it was just
data in a different domain than the sampling clock.

-- Pete


Article: 83078
Subject: Re: How do I convert binary data from Agilent logic analyzer 16702 into plain text?
From: "Avrum" <avrum@REMOVEsympatico.ca>
Date: Fri, 22 Apr 2005 14:53:49 -0400
Links: << >>  << T >>  << A >>
If I remember, the way to do this is to "print" the results. Instead of
selecting a printer, save it to a file instead. This will "print" a text
file containing the data. I think the resulting file is more or less human
and machine readable - the data is all in proper columns, however, I think
it puts page headers every 70 or so lines - if you want to process the file
(say, with awk or perl), then you will have to make sure the program can
recognize the header lines as well as the blank lines.

Also, there may be a problem with the carriage return/line feed sequences in
the file - the 16702 uses PC style CR/LF sequences - if you are working in
UNIX, then you will have to have a sed (or vi) script remove the extra
control character.

Avrum

"Acceed See" <invalicd@hotmail.com> wrote in message
news:4264c256$1@news.starhub.net.sg...
> I gather some file from this machine, but I was only able to save it in
> binary format. What I need is in plain text so that I can correlate with
> my simulator. Anyone can give a pointer?
>
>
>
>



Article: 83079
Subject: Re: What is the cause of a "can not see clock" problem in logic analyser?
From: "Avrum" <avrum@REMOVEsympatico.ca>
Date: Fri, 22 Apr 2005 15:02:30 -0400
Links: << >>  << T >>  << A >>
I can think of a couple of reasons...

First, the "clock" signal on a 16500/16700 logic analyzer needs to be on
specific pins - there is one pin per pod that is the clock pin for that pod.
Also, the naming is not all that easy to determine - the name of the clock
depends on which pod you are using (i.e. the "J" clock is the clock pin on
pod D1). The mapping of clocks to pins is determined by which pods you have
in what slots of the logic analyzer, so changes from LA to LA; go through
the setup menus to make sure you have the right clock.

Second, the LA can deal with digital signals of different voltages; this
allows it to monitor signals from different I/O standards. Each pin (or pod,
I can't remember) must have the proper signal threshold programmed. This
should be set to the proper value for the I/O standard you are using. The
defaults may not necessarily be correct for the I/O standard you are using.
For example, if you are using SSTL2, then the threshold MUST be set to
1.25V. If it is set to a different value, the LA will not "see" the
transitions from the "0" to "1" on the clock.

Avrum


"Acceed See" <invalicd@hotmail.com> wrote in message
news:4264e0ae$1@news.starhub.net.sg...
> My LA is agilent 16702. When I use the 400MHz internal clock to sample
> the clock pin and the data pin with probes, I can see them nicely on the
LA,
> and positive edge of the clock is right in the middle of the data. When I
> change
> to sampling data with my external clock pin, LA told me the clock is too
> weak
> and can not see a clock in the top-right banner. Of course, I don't see
any
> data.
>
> What is the cause of that? How can I correct this?
>
>
>



Article: 83080
Subject: Re: ATA FPGA IP Core
From: chris.hallahan@nuvation.com
Date: 22 Apr 2005 12:54:28 -0700
Links: << >>  << T >>  << A >>
Nuvation has ATA-4 and ATA-5 cores for Xilinx and Altera targets.
www.nuvation.com


Article: 83081
Subject: Virtex 4 Power consumption
From: "jason.stubbs" <jason.stubbs@gmail.com>
Date: 22 Apr 2005 13:39:29 -0700
Links: << >>  << T >>  << A >>
Can anyone give me an estimate of the max current a V4fx60 FPGA will
draw for VCCINT @ 1.2v, & VCCAUX and VCCO @ 2.5v?

I am designing a board with 9 of them and need a rough idea of power
required.

Any help would be appreciated.

Jason


Article: 83082
Subject: Re: Virtex 4 Power consumption
From: "Amora" <amrahmadain@gmail.com>
Date: 22 Apr 2005 13:52:06 -0700
Links: << >>  << T >>  << A >>
Using the Xilinx XPower tool, you can get an estimate of the worst case
power consumption. If you just crank in 1.2v for VCCINT and 2.5v for
VCCO, then by a simple division, you could get the max current drawn by
a V4FX60 FPGA for a specific design. Different designs will draw
different amounts of current. 

Amr


Article: 83083
Subject: Xilinx multiplier out of slices
From: "Peter Sommerfeld" <psommerfeld@gmail.com>
Date: 22 Apr 2005 14:16:31 -0700
Links: << >>  << T >>  << A >>
Hi,

I'm new to the Xilinx tools. How do I tell Xilinx ISE 7.1 to synthesise
the following statement:

y <= a * b;

to NOT use dedicated multipliers?

Thanks a bunch, Pete


Article: 83084
Subject: Re: Xilinx Impact in Linux 2.6.x
From: Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.>
Date: Fri, 22 Apr 2005 14:51:16 -0700
Links: << >>  << T >>  << A >>
Have you tried this:

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18612

Trond Egil Gran wrote:
> Have anyone got Impact working in Fedora Core 3? Or any similar Linux?
> 
> I have tried this:
> 
> http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm
> 
> but I probably get 1000 compile errors.
> 
> Is there any other possibilities for programming xilinx FPGA's?
> I have read about NAXJP but can't find any places to download it,
> I have tried http://www.nahitech.com/nahitafu/naxjp/naxjp-j.html#down
> but can't find any links to click on to download it. I'm using a spartan
> 2E at the moment.
> 
> Why don't just Xilinx program against the parallelport in user-space
> (ppdev) Instead of having two drivers??
> 
> 
> TEG


-- 

     *CAUTION:* Shameless self-promotion follows...


Article: 83085
Subject: Re: Xilinx Impact in Linux 2.6.x
From: Trond Egil Gran <nospam@for.me>
Date: Sat, 23 Apr 2005 00:40:12 +0200
Links: << >>  << T >>  << A >>
Yes, that just works for 2.4 kernels.

It's no longer a problem since I use XC3SPROG instead, and
then I don't need to mess with a bunch of kernel modules.

TEG

Neil Glenn Jacobson wrote:
> Have you tried this:
> 
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18612 
> 
> 
> Trond Egil Gran wrote:
> 
>> Have anyone got Impact working in Fedora Core 3? Or any similar Linux?
>>
>> I have tried this:
>>
>> http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm
>>
>> but I probably get 1000 compile errors.
>>
>> Is there any other possibilities for programming xilinx FPGA's?
>> I have read about NAXJP but can't find any places to download it,
>> I have tried http://www.nahitech.com/nahitafu/naxjp/naxjp-j.html#down
>> but can't find any links to click on to download it. I'm using a spartan
>> 2E at the moment.
>>
>> Why don't just Xilinx program against the parallelport in user-space
>> (ppdev) Instead of having two drivers??
>>
>>
>> TEG
> 
> 
> 

Article: 83086
Subject: Re: Xilinx multiplier out of slices
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 22 Apr 2005 17:14:44 -0700
Links: << >>  << T >>  << A >>
Pete,
Synplify uses an attribute called syn_multsyle. I know this doesn't answer
your question but it might help in your google searches?
Good luck, Syms.
"Peter Sommerfeld" <psommerfeld@gmail.com> wrote in message
news:1114204591.770429.197140@z14g2000cwz.googlegroups.com...
> Hi,
>
> I'm new to the Xilinx tools. How do I tell Xilinx ISE 7.1 to synthesise
> the following statement:
>
> y <= a * b;
>
> to NOT use dedicated multipliers?
>
> Thanks a bunch, Pete
>



Article: 83087
Subject: Re: Xilinx multiplier out of slices
From: Ken McElvain <ken@synplicity.com>
Date: Fri, 22 Apr 2005 18:09:59 -0700
Links: << >>  << T >>  << A >>
Synplify counts the number of multiplier uses and and if
you overflow the available resources, then it puts the
smaller mults into the logic fabric.   So you do not
normally need to use the syn_multstyle attribute.   If you
are doing bottom up design there is an available resources
attribute that lets you set the budgets for your block.

Ken McElvain
Synplicity, Inc.


Symon wrote:

> Pete,
> Synplify uses an attribute called syn_multsyle. I know this doesn't answer
> your question but it might help in your google searches?
> Good luck, Syms.
> "Peter Sommerfeld" <psommerfeld@gmail.com> wrote in message
> news:1114204591.770429.197140@z14g2000cwz.googlegroups.com...
> 
>>Hi,
>>
>>I'm new to the Xilinx tools. How do I tell Xilinx ISE 7.1 to synthesise
>>the following statement:
>>
>>y <= a * b;
>>
>>to NOT use dedicated multipliers?
>>
>>Thanks a bunch, Pete
>>
> 
> 
> 


Article: 83088
Subject: Time Borrowing
From: "Praveen" <sams235@gmail.com>
Date: 22 Apr 2005 21:15:58 -0700
Links: << >>  << T >>  << A >>
Hi all,

I came accross the concept of Time Borrowing, which I have been trying
to understand from a week. Google search gave me links to the docs
which discuss this. Unfortunately, these docs confused me more than
they helped. Could anyone please point me to any source that has a real
example?

Thanks.


Article: 83089
Subject: Re: low budget SystemC to VHDL Compiler?
From: Alan Peter Fitch <seesig@for.address>
Date: Sat, 23 Apr 2005 10:31:22 +0100
Links: << >>  << T >>  << A >>
Falk Salewski wrote:
> Does anybody know a SystemC to VHDL Compiler with a reasonable price? Maybe 
> special prices for universities?
> 
> Falk S. 
> 
> 

You could have a look at

www.systemcrafter.com

There's a SystemC to Verilog translator at
http://www.opensocdesign.com/sc2v.htm

Also have a look at www.systemc.org and click on "products and solutions".

regards
Alan
-- 
Alan Fitch (from home)
org dot ieee at apfitch

Article: 83090
Subject: Re: Xilinx multiplier out of slices
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Sat, 23 Apr 2005 12:13:40 +0100
Links: << >>  << T >>  << A >>
On 22 Apr 2005 14:16:31 -0700, "Peter Sommerfeld"
<psommerfeld@gmail.com> wrote:

>Hi,
>
>I'm new to the Xilinx tools. How do I tell Xilinx ISE 7.1 to synthesise
>the following statement:
>
>y <= a * b;
>
>to NOT use dedicated multipliers?
>

Attribute mult_style:String;
Attribute mult_style of y : signal is "lut";

(I believe you can apply the attribute to component or label names too)

- Brian

Article: 83091
Subject: DDR SODIMM on Avnet Virtex II PRO development kit
From: ZioPino <ascgroup_nospamme@tiscalinet.it>
Date: Sat, 23 Apr 2005 12:00:30 GMT
Links: << >>  << T >>  << A >>
Hi all,
I'm working on a ADS-XLX-V2PRO-DEVP20-6 (The Xilinx Virtex 2 PRO 
development kit from Avnet, with a XC2VP20 onboard), and I was wondering 
if it was possible to connect the DDR SODIMM module (the board comes 
with a Micron 128 MB module) to a Xilinx EDK 6.3 design with plb_ddr or 
opb_ddr IP. In fact the UCF that came with the board support package 
lack of any reference to a DDR clock feedback pin, so although I can 
connect every other element, without that pin I can't correctly clock 
the memory... Unfortunately, I couldn't find any design that uses DDR in 
EDK, so I don't know if that pin exists (and it isn't mentioned on the 
bsp software) or if it really isn't possibile to use the xilinx cores 
with it.

Anyone could help me, please?

Thank you very much!!!

Article: 83092
Subject: multiplier with one fixed value other user defined
From: xiibweb@hotmail.com
Date: 23 Apr 2005 05:23:12 -0700
Links: << >>  << T >>  << A >>
Hi,,
I am interested to write a code in VHDL where one input is user defined
and the
other input is fixed to some value....

for example

0X2=0
1X2=2
2X2=4
3X2=6

here two in fixed (which I want to define as fixed). and 0 , 1, 2 , 3
user defined.

This code is generated using Xilinx webpack...

================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity multo is
    Port ( p1 : in std_logic_vector(1 downto 0);
           w1 : in std_logic_vector(1 downto 0);
           ou : out std_logic_vector(3 downto 0));
end multo;

architecture Behavioral of multo is

begin

        ou <= w1 * p1;

end Behavioral;

================================================================

the code works fine.. but in a final result I hv to make a schmatic
symbol for the code.. and I want to keep the fixed input hidden. So the
user just can change the other input and see the results... but with
existing code user cn c both inputs and requires to define both.

anybody with an answer... help me out...

thanks

John


Article: 83093
Subject: Re: Spartan 3E slower that Spartan 3?
From: "Paul Leventis" <paul.leventis@utoronto.ca>
Date: 23 Apr 2005 05:29:50 -0700
Links: << >>  << T >>  << A >>
> If folks are looking for blazing speed, then I suggest they look at
> Virtex 4.  The Spartan team is all about value (lowest cost).  If you

> have already targeted a Spartan 3, and are moving to 3E because of
the
> IO vs CLB cost benefits, then I am sure the FAE's and tools are there
to
> support you.

I doubt many people who need a low-cost device can afford a V4...

If you want value AND blazing speed, I'd suggest taking a look at
Altera's Cyclone/Cyclone II, which are 50-60% faster than Spartan-3
(and thus 70-80% faster than Spartan-3E?  Eek).  But don't trust me.
Download our Quartus II Web Edition and give things a whirl.

As for Austin's story that Xilinx is guard-banding the timing models by
a lot, I'm not sure why they need to do that.  What is the cause for
the huge uncertainty?  They should know the process well and thus have
good-quality transistor models and capacictance tables.  And the
architecture really hasn't changed.  Shouldn't a good (<10% error)
timing model be a piece of cake?

See?  No hiding behind a fake address for me -- I have no qualms
trolling as me.

Paul Leventis
Altera Corp.


Article: 83094
Subject: Re: Xilinx multiplier out of slices
From: Jerzy Gbur <furia1024@wp.pl>
Date: Sat, 23 Apr 2005 16:44:21 +0200
Links: << >>  << T >>  << A >>
Hello
> 
> I'm new to the Xilinx tools. How do I tell Xilinx ISE 7.1 to synthesise
> the following statement:
> 
> y <= a * b;
> 
> to NOT use dedicated multipliers?

If you have coregen, use it for generate multiplier core and set it, not
to use multipliers. If you haven't mhm... 

Jerzy Gbur




Article: 83095
Subject: Re: DDR SODIMM on Avnet Virtex II PRO development kit
From: Paul Hartke <phartke@Stanford.EDU>
Date: Sat, 23 Apr 2005 08:46:10 -0700
Links: << >>  << T >>  << A >>
I good starting point would be to contact Avnet to get the EDK Base
System Builder (BSB) support files for this board.  The website
indicates this board is bundled with EDK so they should have this
available.

Good Luck!

Paul

ZioPino wrote:
> 
> Hi all,
> I'm working on a ADS-XLX-V2PRO-DEVP20-6 (The Xilinx Virtex 2 PRO
> development kit from Avnet, with a XC2VP20 onboard), and I was wondering
> if it was possible to connect the DDR SODIMM module (the board comes
> with a Micron 128 MB module) to a Xilinx EDK 6.3 design with plb_ddr or
> opb_ddr IP. In fact the UCF that came with the board support package
> lack of any reference to a DDR clock feedback pin, so although I can
> connect every other element, without that pin I can't correctly clock
> the memory... Unfortunately, I couldn't find any design that uses DDR in
> EDK, so I don't know if that pin exists (and it isn't mentioned on the
> bsp software) or if it really isn't possibile to use the xilinx cores
> with it.
> 
> Anyone could help me, please?
> 
> Thank you very much!!!

Article: 83096
Subject: Re: Bug in DDR template in Lattice FPGAs ?
From: "cas7406@yahoo.com" <cas7406@yahoo.com>
Date: 23 Apr 2005 08:58:34 -0700
Links: << >>  << T >>  << A >>
Andre,

I think what you are missing are the constraints. Have set your Tco,
fmax, Setup and Pin Assignment constraints? Use either the preference
file (.prf) or the Pre-Map Preference Editor to set your constraints.
Also TN1050 can help you out. 

rgds, 

cristian


Article: 83097
Subject: Re: DDR SODIMM on Avnet Virtex II PRO development kit
From: ZioPino <ascgroup_nospamme@tiscalinet.it>
Date: Sat, 23 Apr 2005 16:07:28 GMT
Links: << >>  << T >>  << A >>
Paul Hartke ha scritto:
> I good starting point would be to contact Avnet to get the EDK Base
> System Builder (BSB) support files for this board.  The website
> indicates this board is bundled with EDK so they should have this
> available.

Hi Paul!
Thank you very much for the answer!

Fact is that I've found the BSB on their site, but it only has the 
option to use SDRAM, SRAM, FLASH or COMPACT FLASH but no DDR, and it's 
also very simple, since it can just use one of this component in the 
design (you can't select more than one, because the bus for them is 
shared and you need to manually extend the design with ISE to multiplex 
it... anyhow this shouldn't be a problem since the linux designs that 
are in the Board Support Package use this technique). But no examples 
with SODIMM DDR... It really seems that DDR is not supported with EDK 
(at least with ready-to-go cores)...

I'll try to contact AVnet, but anyway if anyone has any info...

Article: 83098
Subject: Re: DDR SODIMM on Avnet Virtex II PRO development kit
From: Duane Clark <dclark@junkmail.com>
Date: Sat, 23 Apr 2005 17:15:26 GMT
Links: << >>  << T >>  << A >>
ZioPino wrote:
> Hi all,
> I'm working on a ADS-XLX-V2PRO-DEVP20-6 (The Xilinx Virtex 2 PRO 
> development kit from Avnet, with a XC2VP20 onboard), and I was wondering 
> if it was possible to connect the DDR SODIMM module (the board comes 
> with a Micron 128 MB module) to a Xilinx EDK 6.3 design with plb_ddr or 
> opb_ddr IP.

The plb_ddr and opb_ddr are for single DDR chips, not a DIMM. So you 
will need to modify them to handle multiple chips. This is actually not 
that difficult; I have done it myself and have been using the design for 
awhile.

Unless later boards have corrected the design, there is a design error 
on the Avnet boards. It turns out the when using DDR signals, the pins 
on the Virtex2p are arranged in pairs that must share a common clock. On 
DDR DIMMs, the DQS signals are special and require a different clock 
from the other DIMM signals. However Avnet shared these pairs between 
the DQS and DM signals. For example, they put DDR_DM0 on pin R22 and 
DDR_DQS0 on pin P22.

If you look at the Xilinx docs, these pins are named IO_L56P_7 and 
IO_L56N_7. Notice that they have the same L number, and differ only in 
the N/P designation. This indicates that these pins are a pair that must 
share the same DDR clock.

The solution that I used for this problem was to recognise that in my 
application, the mask (DM) bits would never change during a data 
transfer. So I let DM use the same clock as DQS, and setup the DM 
signals slightly early and hold them slightly longer than needed.

> In fact the UCF that came with the board support package 
> lack of any reference to a DDR clock feedback pin, so although I can 
> connect every other element, without that pin I can't correctly clock 
> the memory... Unfortunately, I couldn't find any design that uses DDR in 
> EDK, so I don't know if that pin exists (and it isn't mentioned on the 
> bsp software) or if it really isn't possibile to use the xilinx cores 
> with it.

You will need to simply route this feedback signal internally. That 
means that the phase of the DCM might need to be adjusted in software. 
And indeed, the DIMM test bitfile that Avnet provides does indeed 
provide the ability to determine and set the optimum DCM phase.

In practice, while I did implement the ability to alter the phase of the 
relevant DCM (the "ddr_clock" in the Xilinx ddr_clocks reference 
design), I no longer use that. I have the default startup "PHASE_SHIFT" 
set to "33" and never change it (the other DCMs have a "0" phase). I 
have used 128MB, 256MB, 512MB, and 1GB DIMMs on 2 different Avnet 
boards, all without adjusting the phase, and all operate perfectly.

Article: 83099
Subject: Re: Speed acceleration !!!
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sat, 23 Apr 2005 19:41:07 +0200
Links: << >>  << T >>  << A >>

"Johnsons. Joe" <johnsons@rhrk.tu-kl.de> schrieb im Newsbeitrag
news:d4atft$44q$1@news.uni-kl.de...
> Hello
>
> I am using a Virtex2Pro board and lately I was trying to use the PowerPC
at
> the highest speed (300MHz) on my board. I have a function which uses a lot
> of floating point instructions for calculating the log, sine, cosine and
> such stuff. When I ran this program on the PowerPC it took almost 2
minutes
> to perform 1000 iterations at 100MHz. Then we wanted the code to run a
> little more faster and so we implemented the same design at 300MHz. Even
if
> we didn't expect a three fold increase in speed, there was only an
> improvement of a couple of seconds. Can somebody tell me the reason.
>
> Well about the memory that I was using, I used a OCM interface with 32kB
for
> Instruction and 8kB for data. Cache memory was given to the PLB RAM(16kB).
> There was infact no speed difference with and without the cache memories
!!
> Can somebody please help.

Sounds like the algorithm uses heavyly IO operation (external RAM access
etc.). Since the bus speed is the same, same performance. Try to convert
your algortihm to use PPC registers, the benefit from increased clock speed.
Amybe its just a compiler option.

MfG
Falk






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