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Messages from 81750

Article: 81750
Subject: Re: Achieving required speed in Virtex-II Pro FPGA
From: v_mirgorodsky@yahoo.com
Date: 30 Mar 2005 22:54:50 -0800
Links: << >>  << T >>  << A >>
Dear Marc,

Marc Randolph wrote:
> v_mirgorodsky@yahoo.com wrote:
> [...]
>
> I'd investigate the timing analyzer output and see what is
> holding the design back.  Do you have 5 failing paths or
> 100?  Are there large fanouts involved on some of the
> failing paths?  Are there too many levels of logic on some
> of the paths, and if so, can a pipeline stage be moved >forward or
back to help break up the levels of
> logic?

I have only 10 timing errors. I have a 10-bit wide data bus inside of
the filter, delayed on SRL16 elements to save some triggers, the output
of SRL16 goes directly to two comparators and two mux'es, driven by
-ge and -lt output bits and I have two bits within this bus, violating
timing requirements. Doing manual placing I managed to cure one bit,
but got error in another. Timing report says I have about 5-7 logic
levels on failing logic paths. The fan-out for erroneous bits is 3-4
average, or at least tool reports that. Actually, I can add another
pipeline stage between 2-to-1 mux'es and comparator outputs, but this
will bring another 30+ triggers into design, which is not good. In
ACEX-1K such optimization brought the speed up to 200MHz; actually, it
was there from the beginning, but we did not need that fast solution
and trade-off speed for area. It did run in slower Altera chip, what
should I do to get the same result out of considerably faster Xilinx
chip?

> Honestly, a -6 speed grade V2Pro should pretty easily meet
> 150+ MHz if fanout and levels of logic are kept under >control.
This is the only hope :)

> > So, is there any guide about constraints strategy? I read the guide
> > about constraints, but there are too many choices. I managed to
remove
> > couple setup errors by explicit placing combinatorial logic and
> > registers in adjacent slices, but it would be horrible idea to do
> > manual chip routing :(
>
> I agree, and in this case, I suspect it would be unnecessary.  What
> synthesis tool are you using?  What clock speed are you telling the
> tools?  You might try a slightly faster target speed to see if it
helps
> you come much closer to meeting your period constraint, in addition
to
> lowering fanout limits and investigating the number of levels of
logic.

I tried to use slightly faster clock constraints. Instead of 150MHz I
asked the tool to PAR my design to meet something 166+MHz. The result
was exactly the same. 134+MHz is some sort of hard border, which is
almost never crossed :( I am using ISE 6.3 SP1 for all synthesis,
routing and placement operations.
 
With best regards,
Vladimir S. Mirgorodsky


Article: 81751
Subject: Re: Driving two DCM with same clock input pad.
From: "design" <vasus_ss@yahoo.co.in>
Date: 30 Mar 2005 22:56:46 -0800
Links: << >>  << T >>  << A >>

Thanks for all the replies. I did finally manage to fix it. All i
needed to do was select the clock source as internal for one of the
DCM.  Although i understood the part where I needed to use an explicit
IBUF or IBUFG i am not sure on how to do it. I tried instantiating the
IBUF or IBUFG module and using the output to drive the DCM's.

Regards


Article: 81752
Subject: Re: Achieving required speed in Virtex-II Pro FPGA
From: v_mirgorodsky@yahoo.com
Date: 30 Mar 2005 22:59:55 -0800
Links: << >>  << T >>  << A >>
Dear Mike Treseler,

It WAS running fast enough in slower Altera chip, so it SHOULD run the
same fmax or better in faster Xilinx chip, right?

Regards,
Vladimir S. Mirgorodsky


Article: 81753
Subject: Re: Achieving required speed in Virtex-II Pro FPGA
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 31 Mar 2005 09:02:47 +0200
Links: << >>  << T >>  << A >>

<v_mirgorodsky@yahoo.com> schrieb im Newsbeitrag
news:1112252395.759518.274210@z14g2000cwz.googlegroups.com...
> Dear Mike Treseler,
>
> It WAS running fast enough in slower Altera chip, so it SHOULD run the
> same fmax or better in faster Xilinx chip, right?
>
> Regards,
> Vladimir S. Mirgorodsky
>

wrong! dont ever assume anything like that.

the faster fmax most likely can be achived on the faster xilinx part but in
generic if one designs has some fmax on some device than retargetting to the
new FPGA architecture may require some adjustment to achive the comparable
performance. The way synthesis tools map the design to the FPGA are way
different.

Antti



Article: 81754
Subject: Re: Driving two DCM with same clock input pad.
From: "Sam" <fpga@mailinator.com>
Date: 30 Mar 2005 23:20:52 -0800
Links: << >>  << T >>  << A >>

design wrote:
> Thanks for all the replies. I did finally manage to fix it. All i
> needed to do was select the clock source as internal for one of the
> DCM.  Although i understood the part where I needed to use an
explicit
> IBUF or IBUFG i am not sure on how to do it. I tried instantiating
the
> IBUF or IBUFG module and using the output to drive the DCM's.
>
> Regards

It's pretty simple to instantiate the IBUFG's explicitly.  The code
below drives two DCM's from a single IBUFG. You will have to include
the unisim.vcomponents package for ISE to recognise the DCM and IBUFG
primitives, but if you're using DCM's you've probably figured this out
already.

Sam

        IBUFG1 : IBUFG
	port map (O=>clk_ibufg,I=>pad_clkin);

	DCM1 : DCM
	port map(
	CLKIN=>clk_ibufg,CLKFB=>internal_clk1,
	DSSEN=>'0',PSINCDEC=>'0',PSEN=>'0',PSCLK=>'0',
	RST=>'0',CLK0=>internal_clk1_bufg,
	CLK90=>open,CLK180=>open,CLK270=>open,
	CLK2X=>open,CLK2X180=>open,CLKDV=>open,
	CLKFX=>open,CLKFX180=>open,
	LOCKED=>open,PSDONE=>open,
	STATUS=>open);

	BUFG1 : BUFG
	port map (O=>internal_clk1, I=>internal_clk1_bufg);

	DCM2 : DCM
	port map(
	CLKIN=>clk_ibufg,CLKFB=>internal_clk2,
	DSSEN=>'0',PSINCDEC=>'0',PSEN=>'0',PSCLK=>'0',
	RST=>'0',CLK0=>internal_clk2_bufg,
	CLK90=>open,CLK180=>open,CLK270=>open,
	CLK2X=>open,CLK2X180=>open,CLKDV=>open,
	CLKFX=>open,CLKFX180=>open,
	LOCKED=>open,PSDONE=>open,
	STATUS=>open);

	BUFG2 : BUFG
	port map (O=>internal_clk2, I=>internal_clk2_bufg);


Article: 81755
Subject: re:IPIF
From: digitreaco@yahoo-dot-de.no-spam.invalid (digi)
Date: Thu, 31 Mar 2005 02:01:46 -0600
Links: << >>  << T >>  << A >>
Hallo

I have solve this problem with instation of IBUFs and OBUFs and
connect them to the inputs and outputs of component.

But on the outputs of components i get still an Error in the EDK but
not in the ISE!

ERROR:NgdBuild:455 - logical net
'myasimon/myasimon/USER_LOGIC_I/dataout<0>' has
   multiple drivers. The possible drivers causing this are:
     pin dataout<0> on block
myasimon/myasimon/USER_LOGIC_I/Inst_test with type
   test,
     pin PAD on block myasimon/myasimon/USER_LOGIC_I/dataout<0>
with type PAD

Can any help there?


Article: 81756
Subject: Re: How to map FPGA pin outputs and use User Constraints File (UCF) ?
From: "Kunal" <kunalshenoy@hotmail.com>
Date: 31 Mar 2005 00:19:49 -0800
Links: << >>  << T >>  << A >>
Hi,
I had the same problem too.
PACE:
Click on the package view tab at the bottom of the screen. This will
show you all the BGA package pins and their functions ( I/O, clock, Gnd
etc) on a nice graphic. Next drag the module port name from the left of
the screen to an appropriate pin on the package pin diagram and drop
it.

Then just save and exit. The UCF file will show up on your projNav.

Kunal


Article: 81757
Subject: WTB NIOS-II kit
From: "Neo" <zingafriend@yahoo.com>
Date: 31 Mar 2005 01:47:38 -0800
Links: << >>  << T >>  << A >>
Hi,
I wanted to buy a NIOS-2 eval kit, used or new. can anyone point me to
appropriate sellers who, if selling new, are offering discounts.

thanks.


Article: 81758
Subject: Re: Achieving required speed in Virtex-II Pro FPGA
From: v_mirgorodsky@yahoo.com
Date: 31 Mar 2005 02:06:09 -0800
Links: << >>  << T >>  << A >>
Dear Antti Lukats,

I am just curious, how to optimize VHDL code to use with Xilinx versus
Altera? Yes, I know, some elements may be created more efficiently in
Xilinx chips, anothers - in Altera chips. You may target your design to
use one or another element, but generic triggers, multiplexers and
adders are not optimizable for certain FPGA architecture within VHDL
language without using black box primitives.

My concern about Xilinx tools is that they are not giving comparable
performance versus Altera tools with default settings.

With best regards,
Vladimir S. MIrgorodsky


Article: 81759
Subject: Re: WTB NIOS-II kit
From: "Neo" <zingafriend@yahoo.com>
Date: 31 Mar 2005 02:53:45 -0800
Links: << >>  << T >>  << A >>
Actually, I am new to boards and want to buy one which also has
embedded processor to program and experiment with, at home. I found the
one said above attractive but little expensive. any suggestions  on
which one to go for(xilinx ?) are welcome.


Article: 81760
Subject: Re: WTB NIOS-II kit
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 31 Mar 2005 12:54:17 +0200
Links: << >>  << T >>  << A >>
"Neo" <zingafriend@yahoo.com> schrieb im Newsbeitrag
news:1112266425.535008.282930@o13g2000cwo.googlegroups.com...
> Actually, I am new to boards and want to buy one which also has
> embedded processor to program and experiment with, at home. I found the
> one said above attractive but little expensive. any suggestions  on
> which one to go for(xilinx ?) are welcome.
>

something with s3-1000 as minimal on board, xess xsa3-1000 is $199
www.xess.com

antti



Article: 81761
Subject: Re: LVPECL, Virtex II and the EP445
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 31 Mar 2005 03:04:02 -0800
Links: << >>  << T >>  << A >>
"Quiet Desperation" <nospam@nospam.com> wrote in message 
news:250320052307074615%nospam@nospam.com...
> In article <1111809749.291888.193280@f14g2000cwb.googlegroups.com>,
> Marc Randolph <mrand@my-deja.com> wrote:
>
>> For what data-rate(s)?
>
> Up to 3 Gbps on the fast side.
>
> Oh, and programmable logic levels, too. :)
>
> My currrent design is getting NCML from the upstream units.
>
> NCML. There's three other people in the world using NCML as far as I
> can tell. High level is 0 V, low level is -0.5V. Who invented that one?
>
>
> Thank goodness for On's Gigacomm parts. With differential signal they
> take almost anything from 0 to -2V.
>
> Those "any level in" buffers would be real nice in an FPGA. Hint, hint,
> Xilinx.
>
> And I want to go into an FPGA at 3 Gbps without any special Rocket I/O
> stuff.
>
> And as long as I'm dreaming, I'd like a pony.

Dear Pony Dreamer,
So, I guess I use NCML except that I call my ground signal 2.5V! Seriously, 
there are lots of designs out (t)here with 'ground' planes at voltages other 
than 0V. Maybe that's something you could consider.

Micrel make some similar parts to the On Semi ones, have you seen them?

As for 'any-level-in', you'll find that Xilinx parts have a very wide common 
mode range for their LVDS inputs. They stop working at sub-Gbit rates 
though, I reckon all that other single ended crap attached to the same pin 
makes the capacitance too high for anything faster. Does Rocket I/O help?

I hope some of this waffle helps!
Cheers, Syms. 



Article: 81762
Subject: Re: WTB NIOS-II kit
From: "Neo" <zingafriend@yahoo.com>
Date: 31 Mar 2005 03:26:58 -0800
Links: << >>  << T >>  << A >>
yeah, its HW-AFX-SP3-400-DB and has xc3s400 on it and looks quite
enticing too with ADCs/DACs, but shoot !! they are charging extra for
software and jtag cable as options.


Article: 81763
Subject: Re: WTB NIOS-II kit
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 31 Mar 2005 13:27:45 +0200
Links: << >>  << T >>  << A >>
"Neo" <zingafriend@yahoo.com> schrieb im Newsbeitrag
news:1112268418.419724.134070@l41g2000cwc.googlegroups.com...
> yeah, its HW-AFX-SP3-400-DB and has xc3s400 on it and looks quite
> enticing too with ADCs/DACs, but shoot !! they are charging extra for
> software and jtag cable as options.
>
s400 is too small for free SPARC SoC :(
xsa3-1000
includes on board cable, and has ps2 vga, but no adc dac

antti



Article: 81764
Subject: Re: FPGA board--host PC, need 20-50 Mbps speed, USB2, PCI or 1394?
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Thu, 31 Mar 2005 12:40:09 +0100
Links: << >>  << T >>  << A >>
We do a PCI to OPB bridge that would give you the PC connectivity either as
PCI target or Initiator. Using the OPB bus structure you can interface to
your logic or bought in IP. We can also offer a number of IP products in
this area. If you want a hardware platform then our Broaddown2 development
board is also available and offers a highly versatile platform for system
prototyping.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk


"dan" <Danji71@yahoo.com> wrote in message
news:1112244757.089549.232940@l41g2000cwc.googlegroups.com...
> Hi, all,
>
> Thanks for your reading!
>
> My project need transfer the data from the FPGA board to the Host PC.
> The transfer speed is about 25-50Mbps, does anyone konw if there is
> some commerical IP core/or evaluation board we could use with the
> Xilinx fpga directly?
>
> We would like to select the interface from the PCI, USB2.0 or 1394, I
> am very interested in using the usb2.0 interface, however, I only found
> the usb1.1 IP core right now, it is a little old for the future work.
>
> If you have the experience, could you provide some hints which is the
> best method and where I can find the IP cores/evaluation board, really
> appreciate you reply....
>



Article: 81765
Subject: Re: WTB NIOS-II kit
From: "Neo" <zingafriend@yahoo.com>
Date: 31 Mar 2005 03:42:51 -0800
Links: << >>  << T >>  << A >>
the one you say is from which vendor?


Article: 81766
Subject: Re: WTB NIOS-II kit
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 31 Mar 2005 14:02:21 +0200
Links: << >>  << T >>  << A >>

"Neo" <zingafriend@yahoo.com> schrieb im Newsbeitrag
news:1112269371.876755.53030@o13g2000cwo.googlegroups.com...
> the one you say is from which vendor?
>
http://www.xess.com/prod035.php3

antti



Article: 81767
Subject: Re: Bi-directional Pin Use
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 31 Mar 2005 04:05:30 -0800
Links: << >>  << T >>  << A >>
data_pins <= out_data when tristate = '0' else (others => 'Z');

"Weddick" <weddick@comcast.net> wrote in message 
news:AdSdnRNxytxe-dbfRVn-oA@comcast.com...
> Now in VHDL :)
>
>



Article: 81768
Subject: Re: Achieving required speed in Virtex-II Pro FPGA
From: "Marc Randolph" <mrand@my-deja.com>
Date: 31 Mar 2005 04:53:45 -0800
Links: << >>  << T >>  << A >>

v_mirgorodsky@yahoo.com wrote:
> Dear Marc,
>
> I have only 10 timing errors. I have a 10-bit wide data bus inside of
> the filter, delayed on SRL16 elements to save some triggers, the
output
> of SRL16 goes directly to two comparators and two mux'es, driven by
> -ge and -lt output bits and I have two bits within this bus,
violating
> timing requirements. Doing manual placing I managed to cure one bit,
> but got error in another. Timing report says I have about 5-7 logic
> levels on failing logic paths.

7 is quite a few, but probably not impossible.  Unfortunately, that
many  levels of logic, combined with almost any fanout, gives the tools
a chance to make very poor placement choices - as you've seen.

> The fan-out for erroneous bits is 3-4 average, or at least tool
reports that.

Does the fanout come directly from the LUT that is used for the SRL, or
did the tools do the right thing and use a FF?  It may or may not be
obvious from the timing report - you might have to use FPGA editor to
check.

Regardless, you might consider making your SRL one bit shorter and
forcing there to be another FF after the SRL.  You might even go so far
as to fanout the output of the SRL to two or more FF's, and have THOSE
feed the rest of your logic.  You may need a keep properity on the FF's
to keep them from being optimized out.

> Actually, I can add another
> pipeline stage between 2-to-1 mux'es and comparator outputs, but this
> will bring another 30+ triggers into design, which is not good.

What are triggers?  Do you mean FF's?  They are basicly free in most
FPGA designs, and are vital to high speed designs.

> In
> ACEX-1K such optimization brought the speed up to 200MHz; actually,
it
> was there from the beginning, but we did not need that fast solution
> and trade-off speed for area. It did run in slower Altera chip, what
> should I do to get the same result out of considerably faster Xilinx
> chip?

I'm not sure what you're asking.  For the same design, the V2Pro part
is running considerably faster than the old ACEX part, is it not?

> I tried to use slightly faster clock constraints. Instead of 150MHz I
> asked the tool to PAR my design to meet something 166+MHz. The result
> was exactly the same. 134+MHz is some sort of hard border, which is
> almost never crossed :( I am using ISE 6.3 SP1 for all synthesis,
> routing and placement operations.

If possible, try to get ahold of Synplify from Synplicity for your
synthesis.  They will often do eval's so that your purchasing
department doesn't have to get involved until AFTER you see the
(hopefully better) results.

Good luck,

   Marc


Article: 81769
Subject: Re: XC3000 non-recoverable lockup problem
From: "lecroy7200@chek.com" <lecroy7200@chek.com>
Date: 31 Mar 2005 05:27:01 -0800
Links: << >>  << T >>  << A >>
Thanks for the post Brian.

> Proper internal oscillator startup would normally be guaranteed
> by the monotonic VCC rise requirements for the part in question;
> oscillator failure would be consistent the earlier speculation of
> a hypothetical transient of some sort taking out the FPGA.

Based on this I tried several tests yesterday using different power
supply ramp rates.  I went into the seconds. Watching the oscillator
with the spectrum analyzer I can see it sweep as it begins to start and
finally locks to the normal frequency.  I tried manually adjusting the
supply by watching the oscillator to see if I could trick it that way
into not starting.  From this I never saw any of the internal
oscillators fail to start after a day of tests.

It's almost like there was some undocumented test mode that the part
gets into.  I doubt it has anything like this, but from all my tests
the part seems very robust.

An interesting thing I did note was that when the device is powered
down, the oscillators continue to run.  Who would have guessed.  They
must not wanted to deal with the time to lock.  The data sheet talks
about the 3100A drawing 5mA in power down.

>  BTW, on a failed part, have you observed DOUT for activity under
> the test conditions described in Philip's earlier posts?

No

>  Also, what value pullup/pulldown resistors are you using for the
> mode and powerdown pins? I have another vague recollection that
> that the internal pullups were "stiffer" in later 3xxx series parts,
> and needed lower values for the external resistors.

M2 uses a 1K.  M0,M1 and power down are tied directly to VCC.

>  At the risk of sounding repetitive, the method you seek is
> called "master serial mode", which lets you directly observe
> CCLK ( or a divided down version thereof ).
>
>  Yes, this requires changing another variable in your test setup,
> which might affect your chances of observing something.

Agree, and don't think I had not thought of this. The specturm analyzer
and near field probe work fine.  Not sure why Xilinx did not agree with
the technique.

>  However, it provides the benefit that you would now have a
> signal that can be directly probed, and used to catch whatever
> transient event is perturbing the FPGA: e.g., trigger a deep
> memory scope on "loss of CCLK" while probing any likely suspects
> (VCC, configuration pins, VEE, translator output pins, etc.) at
> a high sample rate with plenty of pretrigger storage.

This is a very good idea.  Had I been able to replicate the problem,
using this as a positive trigger would have been a good idea.


Article: 81770
Subject: Re: FPGA board--host PC, need 20-50 Mbps speed, USB2, PCI or 1394?
From: "dan" <Danji71@yahoo.com>
Date: 31 Mar 2005 06:55:20 -0800
Links: << >>  << T >>  << A >>
hi, John:

I have some question about your product:

1. If I buy your IP, is it easy to realize in the Xilinx Virtex2(PRO)
FPGA?
   How much work will need?
2. Is there the PCI DMA function in your IP core? I am concerned about
that.
3. Will you provide the Windows driver for the PCI card?
Thanks for your reply!


John Adair wrote:
> We do a PCI to OPB bridge that would give you the PC connectivity
either as
> PCI target or Initiator. Using the OPB bus structure you can
interface to
> your logic or bought in IP. We can also offer a number of IP products
in
> this area. If you want a hardware platform then our Broaddown2
development
> board is also available and offers a highly versatile platform for
system
> prototyping.
>
> John Adair
> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3
Development
> Board.
> http://www.enterpoint.co.uk
>
>
> "dan" <Danji71@yahoo.com> wrote in message
> news:1112244757.089549.232940@l41g2000cwc.googlegroups.com...
> > Hi, all,
> >
> > Thanks for your reading!
> >
> > My project need transfer the data from the FPGA board to the Host
PC.
> > The transfer speed is about 25-50Mbps, does anyone konw if there is
> > some commerical IP core/or evaluation board we could use with the
> > Xilinx fpga directly?
> >
> > We would like to select the interface from the PCI, USB2.0 or 1394,
I
> > am very interested in using the usb2.0 interface, however, I only
found
> > the usb1.1 IP core right now, it is a little old for the future
work.
> >
> > If you have the experience, could you provide some hints which is
the
> > best method and where I can find the IP cores/evaluation board,
really
> > appreciate you reply....
> >


Article: 81771
Subject: Re: exp(-x) function
From: Kolja Sulimma <news@sulimma.de>
Date: Thu, 31 Mar 2005 17:01:16 +0200
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> andpaoli wrote:
> 
>> I'm new to math function on FPGA, but I need to calculate exp(-x) with
>> a Spartan3 in fixed point 16bit numbers. How can i do that? What's the
>> best way? Can someone help
>> me?[size=24:ae1f1145a8][/size:ae1f1145a8]
>>
>>  
>>
> I've posted on this subject before (search google using andraka and 
> exp)  here is one such posting that is probably the closest to what you 
> want:
> http://groups-beta.google.com/group/comp.arch.fpga/browse_thread/thread/47feb1a180f72f78/3cfe528ea11418b3?q=andraka+exp&rnum=5#3cfe528ea11418b3 

Most likely that's the way to do it. An alternative would be a 
hyperbolic CORDIC, also explained by Ray:
http://www.andraka.com/files/crdcsrvy.pdf

Kolja Sulimma

Article: 81772
Subject: One or two DLLs for a SDRAM controller?
From: Marius Vollmer <marius.vollmer@uni-dortmund.de>
Date: Thu, 31 Mar 2005 17:16:12 +0200
Links: << >>  << T >>  << A >>
Hi,

I have a Xess board with a Xilinx Spartan 3 (XC3S1000) on it and a
SDRAM.  There is of course code out there for accessing this SDRAM
from the FPGA, but I decided to write my own controller, just so that
I could learn what is going on.

Now, all the SDRAM controllers that I have looked at use two DLLs (or
DCMs) to produce the main clock for the controller.  The Xilinx
Applicatin note xapp134 even says:

    It is not possible to use one DLL to provide both the FPGA and
    SDRAM clocks since the SDRAM clock goes through an OBUF delay
    creating skew between the two clocks. Using two DLLs with the same
    clock input and separate feedback signals achieves zero-delay
    between the input clock, the FPGA clock, and the SDRAM clock.

I have only used one DCM for my SDRAM controller, and it seems to work
just fine (i.e., I can use the SDRAM as the framebuffer for a 1024x768
VGA display), but I am of course worried that this is only by
accident.

The "Two DLL" setup looks like this:

       :                                     
 OSC --:--> IBUFG -+--> DLL0 ---> BUFG -+---> main clock
       :           |     ^              |              
                   |     +--------------+       
       ext clock ->|                            
                   |                        :         
                   +--> DLL1 ---> OBUF -----:--+      
                         ^                  :  | SDRAM
                         |                  :  |
                         +------ IBUFG <----:--+< sdram clock
                                            :
                 buf data <----- IBUF <-----:--- sdram data
                                            :

OSC is the external oscillator.  If I understand this arrangement
right, it works as follows: DLL0 will make it so that there is zero
phase difference between "main clock" and "ext clock".  Likewise, DLL1
will produce zero phase difference between "sdram clock" and "ext
clock".  Thus, there is zero phase difference between "sdram clock"
and "main clock".  Consequently, "main clock" can be used for the
sdram controller, since "sdram data" will have the proper setup/hold
times for "main clock".


What I am using right now looks like this:

       :                                    :
 OSC --:---------------------------> OBUF --:---+
       :                                    :   | SDRAM
       :                                    :   |
          +---------------------------------:---+
          |                                 :
          |            buf clock
          |           v
          +-> IBUFG ----> DLL0 ---> BUFG -+--> main clock
                           ^              |
                           +--------------+

DLL0 will produce a zero phase difference between "main clock" and
"buf clock", which is not exactly the "sdram clock" because of the
IBUFG.  Will that be a problem?  My reasoning is that the data signals
go thru a IBUF as well, and thus it is OK to synchronize relative to
the buffered clock.  Assuming that a IBUFG and an IBUF produce the
same amount of delay, it might even be 'more correct' than
synchronizing to the unbuffered clock "sdram clock", since it is "buf
data" which must have the correct setup/hold times.

I fully expect my reasoning to be wrong.  But where?

Thanks!

Article: 81773
Subject: Re: FPGA board--host PC, need 20-50 Mbps speed, USB2, PCI or 1394?
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Thu, 31 Mar 2005 16:44:19 +0100
Links: << >>  << T >>  << A >>
We have already targetted this design to V2-Pro, in a PC104Plus format, on 
one of the boards we have here in development. I should say this IP works in 
conjuction with Xilinx PCI core to make the full bridging function although 
we have plans to make this a direct connect to PCI sometime in the future.

We don't have DMA integrated into the Bridge but we have already done 2 
different DMA engines on the OPB side of core which work with Bridge and can 
DMA internally or over the PCI via the Bridge.

We do have a driver for windows coming. Its availability is linked to a GUI 
interface we are doing for Broaddown2. We are probably 8-12 weeks away from 
that being available dependent on how much client work comes in. So far the 
Bridge has been used by customers using Linux and they have sourced their 
own driver in all cases so far.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk


"dan" <Danji71@yahoo.com> wrote in message 
news:1112280920.744625.293240@l41g2000cwc.googlegroups.com...
> hi, John:
>
> I have some question about your product:
>
> 1. If I buy your IP, is it easy to realize in the Xilinx Virtex2(PRO)
> FPGA?
>   How much work will need?
> 2. Is there the PCI DMA function in your IP core? I am concerned about
> that.
> 3. Will you provide the Windows driver for the PCI card?
> Thanks for your reply!
>
>
> John Adair wrote:
>> We do a PCI to OPB bridge that would give you the PC connectivity
> either as
>> PCI target or Initiator. Using the OPB bus structure you can
> interface to
>> your logic or bought in IP. We can also offer a number of IP products
> in
>> this area. If you want a hardware platform then our Broaddown2
> development
>> board is also available and offers a highly versatile platform for
> system
>> prototyping.
>>
>> John Adair
>> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3
> Development
>> Board.
>> http://www.enterpoint.co.uk
>>
>>
>> "dan" <Danji71@yahoo.com> wrote in message
>> news:1112244757.089549.232940@l41g2000cwc.googlegroups.com...
>> > Hi, all,
>> >
>> > Thanks for your reading!
>> >
>> > My project need transfer the data from the FPGA board to the Host
> PC.
>> > The transfer speed is about 25-50Mbps, does anyone konw if there is
>> > some commerical IP core/or evaluation board we could use with the
>> > Xilinx fpga directly?
>> >
>> > We would like to select the interface from the PCI, USB2.0 or 1394,
> I
>> > am very interested in using the usb2.0 interface, however, I only
> found
>> > the usb1.1 IP core right now, it is a little old for the future
> work.
>> >
>> > If you have the experience, could you provide some hints which is
> the
>> > best method and where I can find the IP cores/evaluation board,
> really
>> > appreciate you reply....
>> >
> 



Article: 81774
Subject: Re: FPGA board--host PC, need 20-50 Mbps speed, USB2, PCI or 1394?
From: "JJ" <johnjakson@yahoo.com>
Date: 31 Mar 2005 08:22:49 -0800
Links: << >>  << T >>  << A >>
Why don't you consider IEEE1355 or SpaceWire interface, easily does
upto 200MBits in cu and far more in glass.

It came out of the remnants of the Transputer Links from the T9000, and
is commercially available from

4links.com using Virtex & no doubt other FPGAs.

Its premise was simplicity & low cost implementation, way less than a
uart and vastly less than USB or FW, self clocking, fairly long
cabling, not sure if its LVDS or the T9000 alternate DS clock edge
scheme.

Hope that help

johnjakson at usa dot com




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