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Atleast I am dead serious, the joke is inverted on the current boring state of PC cpu architecture and Windows hell that we use every other day of the year. Ofcourse FPAGs make it possible to escape the madness and think about something better. JJArticle: 81826
JJ wrote: > If anyone is still interested in Transputers, I am now releasing the > 1st half of a new FPGA Transputer through email, mostly docs but also > an Instruction Set simulator, the C cycle model and Verilog sources for > later, all works in progress > > better than spam I presume Much better, was April 1st a pre-meditated release date ? :) > see comp.sys.transputer > > regards all > > johnjakson at usa dot com Cheers, RupertArticle: 81827
Hi, I use an RAM Block of 28x64 words in my design (Ouartus II 4.2 SP1). I have built the RAM with the integrated MegaFunction Editior. The problem is that this nice SRAMBlock is synthesized away ( Warning: Synthesized away node 4ksram:srama|altsyncram:altsyncram_component|altsyncram_j3u:auto_generated|ram_block1a0" ... up to 27) When I add JTAG capability or add direct output pins I can see that writing into the RAM works(Functional Simulation), because in this case the RAM is not Synthesized away. In the Quartus II Manual I read that in some conditions this may happen and they say that the help may help, but I can not find anything about this in the help. I use the RAM as a ring buffer I read Adress A put this into an register an write a new value to Adress A I got from outside, after this I add one to the Adress Counter (running i circles for the Adress counter works). I hope you can help me and tell me what I did wrong and what I can do to make it work. Thanks in advance for your help. With best regards. AlexArticle: 81828
Hi ALL, I got the problem solved in not very efficient way. I replaced SRL16 elements with conventional triggers and now design flys in the sky - the fmax went all the way up to 214+MHz. The only thing left to figure out - why conventional triggers do such a good job and "very efficient" SRL16 apeared to mess up everything :( With best regards, Vladimir S. MirgorodskyArticle: 81829
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:idap41d22l2oqgfvos2lfuvpcbuuo4cvnu@4ax.com... > > Just measured a Spartan3. In LVDS mode the inputs work nicely over a > common-mode range of < 0.2 to *over* +3.3. I suspect the single-ended > modes would work with a Vref in that range, too. > Hi John, Wow, that's better than I expected! I'm pretty sure that there's no accurate spec for Vicm because otherwise Xilinx would have to test the inputs meet timing and Vid over a large range of Vicm. Thanks for the heads up mate, Syms.Article: 81830
<v_mirgorodsky@yahoo.com> schrieb im Newsbeitrag news:1112375908.017059.293810@g14g2000cwa.googlegroups.com... > Hi ALL, > > I got the problem solved in not very efficient way. I replaced SRL16 > elements with conventional triggers and now design flys in the sky - > the fmax went all the way up to 214+MHz. > > The only thing left to figure out - why conventional triggers do such a > good job and "very efficient" SRL16 apeared to mess up everything :( hm thats strange there is on usually unused flip flop at the 'end' of SRL 16 so doing the SRL16 1 clock shorter and using that flop should have the same performance as only flips if what you say is so, then it must be a bug in the timing estimation ?? anttiArticle: 81831
Hi Rupert No actually I was shooting for last Thanksgiving, then Xmas, then return from Taiwan a month ago, its just a question of whether rotating through the ISA simulator, the C cycle model, the verilog code or the compiler and not letting anyone in or polish up some existing docs and open the door a crack. for some comments or exposure and maybe some help. Actually I keep wondering why JS doesn't do a ISA simulator too, then I admitted I hadn't either, buts its needed to verify the much more complex cycle model that was my baseline so thought it would be a good idea to describe the IS as simply as a ISA simulator does and release that openly. Not actually giving the whole farm away, yet. Anyway what with Cell getting some air time I wouldn't want people to think that that was an acceptable Transputer replacement unless somebody tells me they are seriously porting Occam to it, nothing Transputer like has really showed up yet. I'll stick you on the list anyway. regards johnjakson at usa dot com PS anyway thanks for your previous efforts and being the ideas soundboard, much of that stuff is now starting to work its way through the models.Article: 81832
Hi Vic, I am using PC version software. Do you have an idea how to optimize the XST for spped or for area? During my experiments any touch to efforts/packing/spped controls were bringing fmax down. I understand, that all of them should be tuned all together in some special fassion, but there are too many variants and relations between controls is not evident. With best regards, Vladimir S. MirgorodskyArticle: 81833
<v_mirgorodsky@yahoo.com> schrieb im Newsbeitrag news:1112377002.879128.294460@l41g2000cwc.googlegroups.com... > Hi Vic, > > I am using PC version software. Do you have an idea how to optimize the > XST for spped or for area? During my experiments any touch to > efforts/packing/spped controls were bringing fmax down. I understand, > that all of them should be tuned all together in some special fassion, > but there are too many variants and relations between controls is not > evident. > > With best regards, > Vladimir S. Mirgorodsky > hm stupid question did you constrain the clock for the speed you need? the clock can be constrained to higher than the fmax is reported when running with no constrains also dont constrains too high just to the fmax you actually need, if the timing can not be met by a small margin it yields to timing far worse than it is possible to achive. anttiArticle: 81834
There is only one question left in such case - ho to instruct ISE to put unused flip-flop at the end of the SRL16 shifter in the same slice without doing explicit placement operation? Yes, there is a constrain, called RLOC. And if you put special constraints on SRL16 block and trigger than they may got to the same slice, but this leads to completelly unportable code even between Xilinx family chips. Design with pure triggers runs fast enough and I don't have any clue why SRL16's are not. With best regards, Vladimir S. MirgorodskyArticle: 81835
Sure, I constrained the clock path and I explicitly told to tools that my Clk line is clock for my design :) I put constrain on the clock line about 155+MHz, requiring only 150MHz - it is always good to have a couple percent backup :) Doing manual routing I was able to correct timin errors on data bits, so I am wandering why tool can not do the same :(Article: 81836
Hi, I want to build a dvi to lvds konverter. Betweeen there two busses, I have a 24 bit parallel bus. Eventually I want to do some signal processing with the parallel data too. Will an FPGA be fast enough for this task? regards, BenArticle: 81837
> Is "bulk hull" the same as "convex hull"? That's the > form you get by (conceptually) pulling a piece of string > tight around the shape, so that it hugs all the external > convex parts and stretches across any concave regions of > the shape's outline. Yes, bulk hull, I think so. I might have misspoken here. Nice analogy, the string. > AIUI the concavity is 1-(A/H) where A is the shape's > area and H is the area of its convex hull. But I could > easily be wrong - it's ages since I did any of this stuff. Right. The convex hull is what is left if you subtract away the original shape. But how do you calculate, or otherwise detect the concavities? I have done some initial work with small areas and bit patterns but one soon runs out of logic gates. -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 81838
Don't know this software but perhpas there is a switch to keep it from optimizing the SRAM away. Can you bring the SRAM outputs to IOs?Article: 81839
Hi Austin, > Are all of the posts today in honor of April Fools day? > > I am having a hard time seeing if these are serious, or not..... All of this is serious, as far as I can tell. However, I liked the following article: http://www.theage.com.au/news/Breaking/SMEGmail-offers-1-terabyte-storage/2005/03/31/1111862522200.html Best regards, BenArticle: 81840
85Mhz parallel buses are not an issue for newer fpgas. Are you proposing to interface the fpga directly to the DVI serial pin or interface to a stand alone serdes? Lattice has a new low cost fpga with built in DSP blocks, the ECP. It is an ideal device to process signals. It does not have serdes built in though. http://www.latticesemi.com/products/fpga/ecp/index.cfmArticle: 81841
hi
I need help with my async desgin. I'm using xilinx virtex-ii. I'm very
new with async stuff and so my understanding is very limited--
particularly different fpga architechures. (and async terminology.)
Here is what I want to do:
module async(clk,loopbackclk,....)
input clk;
output loobackclk; reg loopbackclk;
// decl , init and reset stuff omitted
always @(clk)
begin
case (state)
case 0: begin // do stuff
state <= state +1;
loopbackclk <=state;
end
case 1: begin // do stuff
state <= state +1;
loopbackclk <= state;
end
....
endcase
end
endmodule
Now in my top module:
module top()
wire clk,loopbackclk;
async a(clk,loopbackclk,...);
// now depends on what I use for synthesis --
module SOME_BUF_STUFF?(O,I); // if using xilinx tools
assign clk <= I; // maybe O
assign loopbackclk <=O; // maybe I
endmodule // end loopback
// I'm totally blank here , please tell me what do I do if using Icarus
verilog
param(.... clk .... // if using Icarus verilog
param(.... loopbackclk ... // if using Icarus verilog
endmodule // top module
A few questions:
First, is there some generic "buffer" or "pipe" (or insert correct
terms here)
for differenct FPGA's that I can loopback my "state" back as "clk", so
that my state transition only depends on internal circuit, not on a
global clock.
Please give me specific "names" for them. So that I can actually try
it.
Since I prefer using generic tools like Icarus verilog, please help if
you now how to do it. (If possible, I only use vendor specific tools
for P and R)
Thanks.
Article: 81842Antti Lukats wrote: > but with the Virtex 4 bug, thats a bit scarier > > a simple design with 16 counters connected to 16 pin locked GCK inputs. > > P&R fails, saing one signal is not fully routed Hello Antti, If PAR only fails to route a single signal, that's usually an indication of a packing or placement problem leading to an unroutable connection, rather than a congestion issue. These problems are usually not too difficult to understand and correct with packing or placement constraints. Although you are focused on the number of clocks in the design, you don't say whether the unrouted signal is a clock net or something else, so I won't speculate on the root cause. I suggest examining the design in FPGA Editor and trying to understand where the routing conflict is. If you are unable to make any progress with this method, I suggest opening a webcase and providing a test for investigation. Regards, Bret Wade Xilinx Product ApplicationsArticle: 81843
Hi all, This is a really trivial question, but I just can't seem to think correctly, so I thought I'll throw this out here. I am building a non-coherent DPSK receiver in the FPGA. Its all 2's complement arithmetic. Two 12*12 multiplers with an adder that adds the result of the multiplies (matched filter implementation). Then I have a moving average filter which basically boils down to 10 adders (all signed) which adds 10 samples of 24 bit data(result of the adder post multiplication) I use the result of the moving average filter to decode the data. I have two questions 1. In 2's complement arithmetic, do I need to handle the overflow issues when multiplying and adding (i thought you could safely ignore the overflow in 2's complement). If I do, how? 2. Does anyone have a good idea for a data decoding scheme. Right now I am using the "poor man's" detection scheme of deciding a bit based on the sign bit of the moving average sum and its not giving me the required fidelity? Thes questions may sound a little cryptic but any help would be appreciated. Thanks MORPHEUSArticle: 81844
Thank you very much! I used corGen to make a "Single Port Block Memory" and used that for my lineBuffer, and it synthesizes! Thanks so much.Article: 81845
This is usually indicative of a problem with the synthesis tool thinking that the RAM (or any block synthesize away) is not used. Typically because the outputs go to another block which is also synthesized away because of a syntax error. When you add chipscope or bring pins to output .. then suddenly RAM is not synthesized away because outputs used elsewhere. So two techniques to isolate are : [1] If the outputs go from blk A to blk B to Blk C, etc . Bring first the outputs of block A to I/O pins ... if there e error is in block A ... block A and Ram will be trimmed away. If not ... keep moving outputs down the chain until block disappears. This can slip through if there is a subtle port mismatch in width .... or a name mismatch within offending block. [2] Easier way is to use a simulator. Tie all inputs to a known level ... and start to track forward flow of signals until Z's start to show up ... this means nets are not driven. If you are not using a simulator ... take the effort to learn ... Quite easy once you get over the learning curve ... curve can be shortened quite a bit with sample test benches ... scripts to follow ... but payback is huge. Regards, John Retta Owner and Designer Retta Technical Consulting Inc. email : jretta@rtc-inc.com web : www.rtc-inc.com "Alexander Korff" <alexander.korff@t-online.de> wrote in message news:d2jv6g$pg5$01$1@news.t-online.com... > Hi, > > I use an RAM Block of 28x64 words in my design (Ouartus II 4.2 SP1). I have > built the RAM with the integrated MegaFunction Editior. The problem is that > this nice SRAMBlock is synthesized away ( Warning: Synthesized away node > 4ksram:srama|altsyncram:altsyncram_component|altsyncram_j3u:auto_generated|r am_block1a0" > ... up to 27) When I add JTAG capability or add direct output pins I can see > that writing into the RAM works(Functional Simulation), because in this case > the RAM is not Synthesized away. > In the Quartus II Manual I read that in some conditions this may happen and > they say that the help may help, but I can not find anything about this in > the help. I use the RAM as a ring buffer I read Adress A put this into an > register an write a new value to Adress A I got from outside, after this I > add one to the Adress Counter (running i circles for the Adress counter > works). I hope you can help me and tell me what I did wrong and what I can > do to make it work. > > Thanks in advance for your help. > > With best regards. > > Alex > >Article: 81846
Hi,
I dont know if this will help you are not..Did u include ur
component in *.pao file
--
Parag Beeraka
Article: 81847
Hi everyone ,
Can any one in brief tell me how to design a Master -
Slave IP Core on the OPB - Bus ..I just need a design which could read
from and write to any address that I specify ... I know how to design a
slave and I was successful in it but I am not able to understand how
the interaction between and Master and Slave should be because I know
that we cannot design a master alone .. I m using EDK 6.3 and
the ML 310 Board which has a XC2VP30 on it ..
--
Parag Beeraka
Article: 81848Hi all, I'm trying to install ModelSim XE (both II and III) on a WindowsXP box but I can't get it working when I login as a simple no privileged User. I installed the software logged as Administrator, and I loaded the license.dat file, in this situation the software works correctly, but when I use the computer as a normal User (I'm not the Administrator of that computer) ModelSim doesn't work, It prints and error like this: ---------------------------------------------------------------------- Your evaluation license has been invalidated because a text file necessary for licensing cannot be written. In order to continue with the evaluation of Modelsim you will need to correct the error, re-install the evaluation copy and re-request an evaluation license from Model Technology. Evaluation Error: 104 ---------------------------------------------------------------------- I also changed the permissions on the ModelSim folder, and gave full controll on it, but nothing changed. Is there a way of using ModelSim not being Administrator on WindowsXP? -- Confucius say... Man who run in front of car get tired |\ | |HomePage : http://nem01.altervista.org | \|emesis |XPN (my nr): http://xpn.altervista.orgArticle: 81849
Hello,
my experiment has shown that high-quality sine wave can be
easily generated using linear interpolation. A simple look-up
table and a small multiplier is necessary, however I use two
LUTs instead of one, because this reduces complexity of the
circuit. But for a specialized IC the one LUT-based approach
should be considerably cheaper. The idea is as follows: the
first LUT contains 256 unsigned 18-bit sine values in the
interval of [0,pi/2), sampled uniformly. The second LUT
contains differences between consecutive samples (as
I said above, this can be computed on-line, but is not well-suited
for an FPGA chip because of long latency compensation paths,
i.e. many wasted LEs). This ROM has only 11 bits, because
max{(sin(2*pi*(k+1)/256) - sin(2*pi*k/256))*2^18} is just 1609.
An 18-bits wide phase word is composed of three parts:
quadrant_indicator (the upper 2 bits), lut_index (the next 8 bits)
and phase_residue (remaining 8 bits). This provides:
my_sin(x) = sign * lut_val[lut_index] + lut_dif[lut_index] *
phase_residue;
Of course sign, lut_index and phase_residue depend on
currently selected quadrant, but this just a trivial remark.
This simple scheme provides sine wave with 17 bits of accuracy,
which can be used directly to feed a quadrature mixer. Another
important property is that the interpolation error near pi/2 is
negative (i.e. forall x . |my_sin(x)| < 1), so there is no need for
guard bits. I have some ideas how to further increase accuracy,
but I am not sure whether I should start developing them, because
17 bits are far better than any modern digital RF front-end expects.
I have implemented a complete quadrature mixer (not just an NCO)
on a multiplierless Cyclone 1C6 and it occupies only 815 LEs, where
the majority of them is consumed by a 17x16 shared multiplier. Its
top performance is limited by M4K RAMs and for -6, -7 and -8 speed
grades this is, respectively, 255.9 MHz, 226.3 MHz and 197.0 MHz.
So, this low cost and low complexity method needs 256 times
smaller number of ROM cells than classical ROM-based designs
and much less LEs than CORDIC-based approaches. Moreover,
this is achieved without signal quality nor performance degradation.
Best regards
Piotr Wyderski
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