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On 25 Apr 2005 09:25:55 -0700, akiriwas@gmail.com wrote: >Thanks! But, I was almost sure that I had read that a floating point >adder was much more expensive (in terms of slices or CLBs) than a >floating point multiplier since it needed to normalize one of the >operands. Was I wrong about this? Hey, they were just guesses. I guessed that since you ruled out any support logic (like the carry that is built into ALL logic elements of ALL current products, regardless of vendor), that also ruled out things like the multipliers that most current products also include. So I guessed that the multiplier array more or less was as big as as the normailzing logic. If you add in my +/- 50% wishy-washy ness, I am probably in the right ballpark, or at least the right time zone. These are all fairly easy to code up for current synthesys tools, providing you arent trying to do all the silly exception stuff in IEEE 754. PhilipArticle: 83176
Markus Meng schrieb: > Hi all, > > we face a strange problem with our synchronized reset signal coming > from the ISA-Bus. It seems that some part of the logic is not > functioning correctly after reset-release. However I'am not shure. > > I would like to implement a digital debounce logic for this reset > signal, and for this reason I would like to have part of the > logic on reset-ed ONCE after power-up and configuration. Is there > a way to connect to this internal power-up reset signal, or shall I > leave the reset connection of such a debounce block always negated > by connecting it to permanent '0', for a active '1' reset? > > Best Regards > Markus > > ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet > News==---- > http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ > Newsgroups > ----= East and West-Coast Server Farms - Total Privacy via Encryption =---- Coming One Step further, we now have the following situation. The very similar Spartan-II design is working perfectly in a clean 3.3Volt ISA bus environment. Several thousand test runs using the the synchronized Reset logic never produces an error. The card is working as expected. The very same card in a 'old' fashioned 5V ISA-Bus System with some overshoot on the signals crashes from time to time after RESET. Once this crash occurs, there is NO-WAY to reset the FPGA again. It remains "kind-of-dead". Only Power-Off and Power-On again can 'solve' this deadlock situation... The configuration is loaded from an external prom only once after power-up. The ISA-Bus reset does not reload the bitstream but resets the internal FF to their initial state ... Has somebody also seen this kind of strange behavior, where the FPGA can not be reseted anymore by subsequent resets. It remains in this state until power-off. Is this a 5Volt compatibility issue of Spartan-II? Best Regards Markus ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==---- http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups ----= East and West-Coast Server Farms - Total Privacy via Encryption =----Article: 83177
"Ziggy" <Ziggy@TheCentre.com> wrote in message news:_c8be.14332$c24.10134@attbi_s72... > Acceed See wrote: >> Ziggy, >> >> For this board, can buyer specify a Spartan 3 1000K FPGA? >> On this page, it mentioned the board can accomodate three types of FPGA, >> http://www.digilentinc.com/Products/Programmable.cfm >> but on the actual page, this information is missing. >> http://www.digilentinc.com/info/S3Board.cfm >> >> Thank you for your attention. >> >> >> > > Donno, but im sure they would respond to an email. > > Personaly i was interested in the Virtex-2, as its got 2 real PPC cores. > Could have lots of fun with that * drool *.. > > The S3 board does have a 1M option now, you see it in the shopping cart. > And in reality that is what im going to be getting, unless i can find a > way to be declared a student.. Its like only 120 or so with the 1M > upgrade, much more affordable to a simple hobbiest like myself. Says quarter 3 2005 Spartan3e starter kit http://www.xilinx.com/products/spartan3e/s3eboards.htm for US$149 ethernet , usb , 32MB sdram, XC3S500E-4FG320 maybe with an upgrade option ? AlexArticle: 83178
Jason, Use the on line power estimator tool. Less accurate, but it should allow you to get a good feeling for the power needed for you design. Austin jason.stubbs wrote: > XPower says I need a completely mapped NCD file to get started. I dont > have anything from the FPGA designer that I can use yet. > > Can I do anything without requiring the NCD file? > > Jason >Article: 83179
Hi, why is nstate bad syncronous? It works when I remove rising_edge(clk_250k)... (I want to generate a signal which is a clock at 250k but with period of the clk_8m) nextstate:process (clk_8m,clk_250k) begin case state is when state1 => if clk_250k='1' and rising_edge(clk_250k) then state <= state2; end if; when state2 => if clk_8m='1' then nstate<=state3; end if; when state3 => if clk_8m='0' then nstate<=state1; end if; end case; end process; regards, BenjaminArticle: 83180
Alex Gibson wrote: > "Ziggy" <Ziggy@TheCentre.com> wrote in message > news:_c8be.14332$c24.10134@attbi_s72... > >>Acceed See wrote: >> >>>Ziggy, >>> >>>For this board, can buyer specify a Spartan 3 1000K FPGA? >>>On this page, it mentioned the board can accomodate three types of FPGA, >>>http://www.digilentinc.com/Products/Programmable.cfm >>>but on the actual page, this information is missing. >>>http://www.digilentinc.com/info/S3Board.cfm >>> >>>Thank you for your attention. >>> >>> >>> >> >>Donno, but im sure they would respond to an email. >> >>Personaly i was interested in the Virtex-2, as its got 2 real PPC cores. >>Could have lots of fun with that * drool *.. >> >>The S3 board does have a 1M option now, you see it in the shopping cart. >>And in reality that is what im going to be getting, unless i can find a >>way to be declared a student.. Its like only 120 or so with the 1M >>upgrade, much more affordable to a simple hobbiest like myself. > > > Says quarter 3 2005 > > Spartan3e starter kit > http://www.xilinx.com/products/spartan3e/s3eboards.htm for US$149 > ethernet , usb , 32MB sdram, XC3S500E-4FG320 > maybe with an upgrade option ? > > Alex > > > All i know is if you order the S3 board direct from digiliant, when you check out you get the option today to upgrade the chip... Guess ill find out in a week or two if its really there when i order mine. If its not real, then ill wait..Article: 83181
Hi, this works now in the simulator and is synthesizable. But is it a good methodology too? Actually I would like to add a if clk_8m'event to the top of the process, but this is not synthesizable. nextstate:process (clk_8m) begin case state is when state1 => if clk_250k='1'then state <= state2; end if; when state2 => if clk_8m='0' then state<=state3; lcd_tick <= '1'; end if; when state3 => if clk_8m='1' then state<=state4; end if; when state4 => lcd_tick<='0'; if clk_250k = '0' then state<=state1; end if; end case; end process; reagards, BenjaminArticle: 83182
Hi, I have tested it now on the board and it doesnt work? Does anybody know why? regards, BenjaminArticle: 83183
Benjamin Menküc wrote:
> I have tested it now on the board and it doesnt work? Does anybody know
http://groups-beta.google.com/groups?q=vhdl+synchronous+template
-- Mike Treseler
Article: 83184Austin, The online tool also requires details of the design that I dont have. Can you guide me in what I have to enter to estimate the worse case? Thanks JasonArticle: 83185
Hi, this works now... Does anybody have a better way to do it? nextstate:process (clk_8m) begin if falling_edge(clk_8m) and clk_8m='0' then case state is when state1 => if clk_250k='1'then state <= state2; end if; when state2 => lcd_tick<='1'; state<=state3; when state3 => lcd_tick<='0'; if clk_250k = '0' then state<=state1; end if; end case; end if; end process; regards, BenjaminArticle: 83186
Hi Info, I have implemented the LCD stuff now, but it doesnt work, I can not display characters. Have you tested it before on Hardware? The datasheet of my lcd controller KS0066 does the initialization in different order.... regards, BenjaminArticle: 83187
Acceed See wrote: > Ziggy, > > For this board, can buyer specify a Spartan 3 1000K FPGA? > On this page, it mentioned the board can accomodate three types of FPGA, > http://www.digilentinc.com/Products/Programmable.cfm > but on the actual page, this information is missing. > http://www.digilentinc.com/info/S3Board.cfm > > Thank you for your attention. As Ziggy says, it's available. I have one in front of me now with an XC3S1000 - it cost an extra $50 ($149 total) from Digilent. Yes, they need to enhance their web page, I wasn't aware of this option until I went to buy a 200 (400 is an extra $20, click on 'Add to cart' to see these). I'm impressed with this board - good value for money and it arrived quickly. -- Lawrence Wilkinson lawrence@ljw.me.uk Ph +44(0)1869-811059 http://www.ljw.me.ukArticle: 83188
Ziggy wrote: > The S3 board does have a 1M option now, you see it in the shopping cart. Alex Gibson wrote: > Says quarter 3 2005 > > Spartan3e starter kit > http://www.xilinx.com/products/spartan3e/s3eboards.htm for US$149 > ethernet , usb , 32MB sdram, XC3S500E-4FG320 > maybe with an upgrade option ? Ziggy was talking about the S3 board, not the S3E board. The S3 board is available from Digilent with the XC3S400 or XC3S1000 in place of the usual XC3S200. It does not have Ethernet, USB, or SDRAM, though. It does have static RAM.Article: 83189
Has anyone experince with Hitech Global (www.hitechglobal.com) prototyping boards? Do they stick to their board manufacturing deadlines? What about Xilinx -- is their Virtex 4 already shipping, how long are waiting times? Thanks a lot for your answers, Regards SimonArticle: 83190
Jason, The 'worst case'? For a FPGA the 'worst case' is probably something you don't even want to consider. For example, if you put in all 100% of the CLB FF's toggling at 300 MHz, you are likely to see that the power required is so large that you can not heatsink the device (would melt the solder and fall off the pcb). The power estimators need your case, not the 'worst case'. Austin jason.stubbs wrote: > Austin, > > The online tool also requires details of the design that I dont have. > Can you guide me in what I have to enter to estimate the worse case? > > Thanks > > Jason >Article: 83191
Simon, The Virtex-4 LX25, LX60, LX100, LX200, SX25, SX35, SX55, and FX12 FPGAs are shipping today. Xilinx now has a total of 20 FPGAs shipping at 90nm -- three times as many 90nm FPGAs as its nearest competitor. All there, all ready for you, AustinArticle: 83192
I have a 402 Virtex 4 board from Xilinx. I don't have one of the special cables required to load it so I am trying to use the System Ace method and adding my configuration as MyAce. I'll withhold my comments on why they require a special cable but don't supply it with the board. I seem to be able to generate a MyAce.ace file ok, but it is 1,674 KB long and I get an error when I select it. I notice that all the other working .ace files are 1,686 KB long, so I assume I am doing something wrong. Any idea what or any recommendations? I wanted to order a cable kit but they were out of stock. Any other sources? Thanks in advance, Marco ________________________ Marc Reinig UCO/Lick Observatory Laboratory for Adaptive OpticsArticle: 83193
>> The online tool also requires details of the design that I dont have. >> Can you guide me in what I have to enter to estimate the worse case? Make some estimates or guesses. That will at least give you a number. Then go back and change the numbers you aren't sure about. If the answer doesn't change much then don't worry much. If the answer depends a lot on your wild guesses then you have learned that you have to work on that part of the design so you will have meaningful numbers to feed to the power-estimator. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 83194
DAMN, my data bus was in the wrong order :)Article: 83195
rgebru wrote:
> I started using the Analog devices AD7814 and I'm having trouble
> understanding how to interface it to the Spartan 3 board. :( Does
> anyone have any suggestions to get me started? I could REALLY use the
> help!! Thanks!!
>
Less talk, more action !
Check that your temp sensor works like this one (Max6627) but it
shouldn't be a difficult task to adapt the code if it doesn't :-)
Bert Cuzeau
-- ------------------------------------------
-- MicroWire Temp Sensor (c) Bert Cuzeau --
-- ------------------------------------------
-- do not use without prior written consent
-- from the author.
-- Check with info at alse-fr dot com
-- ------------------------------------------
-- With on-the-fly Bin -> BCD conversion.
-- Has been tested on the new Altera MaxII board. Worked 1st try.
--
-- Note : Bin -> BCD conversion is simplified, okay up to +/- 99 included.
-- Note that we handle the negative values !
-- TEMP_CSN : out std_logic;-- Temp Sensor SPI Select
-- TEMP_SCK : out std_logic;-- Temp Sensor SPI Clock
-- TEMP_SDO : inout std_logic;-- Temp Sensor SPI Data
SPI_i: block
begin
-- DO NOT DO THIS below : you won't get a pullup and the input will disappear !
--TEMP_SDO <= 'H'; -- we don't drive it
-- This is okay :
TEMP_SDO <= 'Z'; -- we don't drive it
-- don't forget the pullup in the pin assignment ! (or on your board)
process (Clk, Rst)
variable BitCnt : integer range 0 to 16;
begin
if Rst='1' then
WrTemp <= '0';
TEMP_CSN <= '1';
TEMP_SCK <= '0';
Sign <= '0';
stSPI <= spiBoot;
BitCnt := 0;
FPGA_uW_SIOr<= '0';
TempH <= (others=>'0');
TempL <= (others=>'0');
elsif rising_edge (Clk) then
WrTemp <= '0';
FPGA_uW_SIOr <= TEMP_SDO or TEMP_SDO;
case stSPI is
when spiBoot =>
if Tick4us='1' then
stSPI <= spiIdle;
end if;
when spiIdle =>
TEMP_CSN <= '1';
TEMP_SCK <= '0';
if Cnt05s(Cnt05s'high) = '1' then -- read temperature ~ 2 times / s
TEMP_CSN <= '0';
TempH <= (others=>'0');
TempL <= (others=>'0');
BitCnt := SPi_Nbits;
stSPI <= spiRead1;
end if;
when spiRead1 =>
if Tick4us='1' then
TEMP_SCK <= '1'; -- rising edge
stSPI <= spiRead2;
if BitCnt = SPi_Nbits then
Sign <= FPGA_uW_SIOr; -- Shift the sign in...
else
if TempL < 5 then
TempH <= TempH(2 downto 0) & '0'; -- no carry
TempL <= TempL(2 downto 0) & (FPGA_uW_SIOr xor Sign);
else
TempL <= "-"(TempL,5) (2 downto 0) & (FPGA_uW_SIOr xor Sign);
TempH <= TempH(2 downto 0) & '1'; -- carry
end if;
end if;
BitCnt := BitCnt-1;
end if;
when spiRead2 =>
if Tick4us ='1' then
TEMP_SCK <= '0';
if BitCnt /= 0 then
stSPI <= spiRead1;
else -- No more bit
TEMP_CSN <= '1';
if Cnt05s(Cnt05s'high) = '0' then
WrTemp <= '1'; -- signal we want to display the temp
stSPI <= spiIdle;
end if;
end if;
end if;
end case;
end if;
end process;
end block;
Article: 83196Preben Holm wrote: >> Looks like it's a functional simulation. > > > Post-map (but only for the single module) What do you mean ? You have a test bench and do a post-map pre-layout unitary timing simulation ? Did you attach the sdf file properly ? (I don't see delays in the output) Did you perform functional sim and did it work ? Seems you simulate a 100Mhz clock. What does the Static timing Analysis report (when you P&R) ? BTW: Didn't you change the inputs at the same time as the rising edge of the clock ? The zoom of the waveform wasn't high but it looked like you did. A simple (& better) idea is to change (apply) the inputs on the inactive (falling) edge of the clock. Simpler to understand in functional sim, and definitely more friendly in timing sim ! Anyway, the weirdest things often have the simplest explanations ! I guess this is the case here and the solution could be trivial. If you post all your code, we could help you. > > Async reset? Why not sync reset? Long debate, refer to previous posts. Sync reset isn't bad intrinsically. Your call. > > if rising_edge(clk) and hold = '1' then > ... > end if; > is worse than > if rising_edge(clk) then > if hold = '1' then Yes ! Definitely worse ! Some synthesis tool may believe that you want a gated clock. I'm sure you don't want this, do you ??? I published a VHDL coding style guide which probably would have avoided these issues. See http://www.alse-fr.com/english/tech_corner.html and http://www.alse-fr.com/archive/VHDL_Coding_eng.pdf Bert CuzeauArticle: 83197
Benjamin Menküc wrote:
> DAMN, my data bus was in the wrong order :)
This and other issues.
Spend more time verifying and studying existing good code.
Don't use a 250 kHz clock.
Don't write processes like the one you posted.
Understand what clock domains are and what issues they bring.
And SIMULATE !
And, yes, I've used and tested my LCD controller on many different boards :
Altera Apex, Altera Flex, Altera Cyclone, Tornado, Nios Cyclone,
Nios Stratix, Lattice, Atmel FPSLIC, Xilinx XS40, Spartan II, Seytronix,
Insight-Memec, and probably a few others. And 5 different makes of LCD modules.
(HD74780 compatible, OTOM)
Read and re-read :
http://www.alse-fr.com/archive/VHDL_Coding_eng.pdf
Tick generation doesn't seem difficult :
-- ----------------------------
-- 1 us, 4us & 10 us Tickers
-- ----------------------------
process (Clk, Rst)
begin
if Rst='1' then
Div1 <= 0;
Div4 <= 0;
Div10 <= 0;
Tick1us <= '0';
Tick4us <= '0';
Tick10us <= '0';
Cnt05s <= (others=>'0');
elsif rising_edge (Clk) then
Tick1us <= '0';
Tick4us <= '0';
Tick10us <= '0';
if Div1 = Div1us_c-1 then
Div1 <= 0;
Tick1us <= '1';
else
Div1 <= Div1+1;
end if;
if Tick1us='1' then
if Div10 = 9 then
Div10 <= 0;
Tick10us <= '1';
else
Div10 <= Div10+1;
end if;
end if;
if Tick1us='1' and Div4 = 3 then
Div4 <= 0;
Tick4us <= '1';
elsif Tick1us='1' then
Div4 <= Div4+1;
end if;
if Tick10us='1' then
Cnt05s <= Cnt05s + 1;
end if;
end if;
end process;
-- ----------------------------
More efficient implementations are easy to imagine, but
this one is obvious.
Article: 83198
Benjamin Menküc wrote:
> Hi,
>
> why is nstate bad syncronous? It works when I remove
> rising_edge(clk_250k)...
> (I want to generate a signal which is a clock at 250k but with period of
> the clk_8m)
>
> nextstate:process (clk_8m,clk_250k)
> begin
>
> case state is
>
> when state1 =>
> if clk_250k='1' and rising_edge(clk_250k) then
> state <= state2;
> end if;
>
> when state2 =>
> if clk_8m='1' then
> nstate<=state3;
> end if;
>
> when state3 =>
> if clk_8m='0' then
> nstate<=state1;
> end if;
>
> end case;
> end process;
>
> regards,
> Benjamin
Benjamin Menküc wrote:
> DAMN, my data bus was in the wrong order :)
This and other issues !
- Spend more time verifying and studying existing good code.
- Don't use a 250 kHz clock.
- Don't write processes like the ones you posted.
- Understand what clock domains are and what issues they bring.
- >>> And SIMULATE ! <<<<
And, yes, I've used and tested my LCD controller on many different boards :
Altera Apex, Altera Flex, Altera Cyclone, Tornado, Nios Cyclone,
Nios Stratix, Lattice, Atmel FPSLIC, Xilinx XS40, Spartan II, Seytronix,
Insight-Memec, and probably a few others. And 5 different makes of LCD modules.
(HD74780 compatible, OTOM)
So I suggest you make it work "as is" without breaking it, and bringing
changes only when you fully understand how it works, and you're sure
you have something to change.
Read and re-read (and adopt) :
http://www.alse-fr.com/archive/VHDL_Coding_eng.pdf
Tick generation didn't seem difficult so I didn't
include it in the LCD module :
-- ----------------------------
-- 1 us, 4us & 10 us Tickers
-- ----------------------------
process (Clk, Rst)
begin
if Rst='1' then
Div1 <= 0;
Div4 <= 0;
Div10 <= 0;
Tick1us <= '0';
Tick4us <= '0';
Tick10us <= '0';
Cnt05s <= (others=>'0');
elsif rising_edge (Clk) then
Tick1us <= '0';
Tick4us <= '0';
Tick10us <= '0';
if Div1 = Div1us_c-1 then
Div1 <= 0;
Tick1us <= '1';
else
Div1 <= Div1+1;
end if;
if Tick1us='1' then
if Div10 = 9 then
Div10 <= 0;
Tick10us <= '1';
else
Div10 <= Div10+1;
end if;
end if;
if Tick1us='1' and Div4 = 3 then
Div4 <= 0;
Tick4us <= '1';
elsif Tick1us='1' then
Div4 <= Div4+1;
end if;
if Tick10us='1' then
Cnt05s <= Cnt05s + 1;
end if;
end if;
end process;
-- ----------------------------
More efficient implementations are easy to imagine, but
this one is obvious.
Bert Cuzeau
Article: 83199At $2500 Ed, it's even more out of my price-range than the $1600 one first mentioned. I guess I should have said 'at last an *affordable* ...' (at least if you're a student...) It might actually be worth enrolling in some course just to get the board, given the difference in cost ($1600 becomes $300...) Simon
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z