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Hi Peter, > It is much safer to use a proven circuit designed by experts. It may > sometimes be overkill, but it works, and lets you spend your energy on the > really important and unique parts of your design. As commercially biased as I am, I have to agree with you. Designing a good dual-clock FIFOs can take many weeks of devising algorithms, testing them, throwing them out of the (for stress relief, preferrably closed) window etc. When I designed my first cross-clock bus it was on OTP parts, so I truly learned to simulate before burning, and even then it took me six or seven failing designs (equalling 3 fully equipped worth about $800 each) before getting it Right. If you have three or four weeks of spare time and a powerful computer to research the subject, then by all means, please do find an efficient way to build a dual-clock FIFO construct we haven't thought of. Otherwise, please use $VENDOR's implementation. Project pressure usually is way too high to waste on a FIFO. Best regards, BenArticle: 83276
Peter Alfke wrote: > Berty, I disagree. > While it is good for every young engineer to learn the basic skills, > designing an asynchronous FIFO is far from "basic". > Using a dual-ported RAM makes most of the design trivial, but the EMPTY > and FULL detection and arbitration at high asynchronous clock rates is > far from simple. I have a few patents and several magazine articles, > and Clifford Cummings has published extensively. It is still considered > wizardry, and grown men can get into deep arguments, since this > involves Gray counter decoding and metastability. It is much safer to > use a proven circuit designed by experts. It may sometimes be overkill, > but it works, and lets you spend your energy on the really important > and unique parts of your design. > Peter Alfke, Xilinx Applications > Excellent post IMO. We (who spend weeks coding complex designs) are _so_ happy that gifted engineers took the pain to build asynchronous stuffs that _work_, guaranteed :-) Clock domain crossing isn't usually a problem thanks to these little "cores" that we use everyday without thinking. Interestingly, it seems that, today, fewer and fewer engineers are even curious to know how modern FFT cores are implemented internally ! Well, I believe there is still room for creativity and clever engineering, but the level of abstraction is just moving up one other notch. The challenge also moved towards verification, but I think there is no verification methodology which will ever fix a poor design. But thanks again anyway to the creators of the async Fifos !!! Bert CuzeauArticle: 83277
This is a Question to Xilinx experts. One of our customers for whom we did design (not so long ago !) an XC4044XL reports today that he has to move to a 4052 for obsolescence reason. Since I see in some posts that Xilinx is still seeling some venerable 3k parts, I'm surprised. I also find increasingly difficult to find these "mature" "classic" devices on the Xliinx Web, but I certainly understand the marketing logic behind this. Is the 4044XL production stopped ? Thx in advance, Bert Cuzeau (btw : this customer has _valid_ reasons to stick with this family for the time being)Article: 83278
Hi, I tried to do what you said about using the data as the address for the RAM, then increase Data_out and then write back, but this for some reason doesn't work right. I can see that if my write signal changes from 0 to 1 from state read to state write on every clk edge, there is no data in the RAM. If I just let the write signal remains constant, then there will be data in the RAM. But this wouldn't be a histogram, it's just raw data. Has anyone successfully doing this? I don't want to use the dual port RAM because if you read from port A and write to port B, then the next time when you read again, your data from A hasn't changed, so basically you are not really doing anything to your memory content in the end, except increase by 1. Thanks, ALArticle: 83279
http://www.xilinx.com/bvdocs/notifications/pdn2004-21.pdf Is the discontinue notice for somw parts that had extremely low volumes. Austin info_ wrote: > This is a Question to Xilinx experts. > > One of our customers for whom we did design (not so long ago !) > an XC4044XL reports today that he has to move to a 4052 for > obsolescence reason. Since I see in some posts that Xilinx is > still seeling some venerable 3k parts, I'm surprised. > I also find increasingly difficult to find these "mature" "classic" > devices on the Xliinx Web, but I certainly understand the marketing > logic behind this. > > Is the 4044XL production stopped ? > > > Thx in advance, > > Bert Cuzeau > > (btw : this customer has _valid_ reasons to stick with this family for > the time being) >Article: 83280
> 1) Xilinx politics: ISE is FPGA tool, EDK is embedded development tool. So
> picoblaze would not be integrated to ISE
I'm not too familiar with Xilinx politics, etc but the way I see it
(heck, the way Ken Chapman sees it), Picoblaze is meant to replace state
machines which have got too hairy to do the usual way, not the kind of
stuff Microblaze/PPC is meant for.
> 2) A few releases ago it was possible to create own cores for coregen, with
> latest ISE releases this seems to be more hidden than it used to be.
> Picoblaze could be added to coregen, that would be possible - unfortunatly I
> can not do it (see before it was possible in ISE 5.x)
Yeah, I read the XAPP, tried, and failed. I now do things the hard
way (instantiate LUTs and FFs, and apply attributes in VHDL).
> 3) All the 'integration' actually isnt so necessary - all that is needed is
> the ability of DATA2MEM to initialize the parity bits (sorry maybe that is
> fixed in 7.x I havent checked). So you can just add the picoblaze with empty
> BRAM and run a batch/shell script that uses DATA2MEM to combine the .PSM
> into the ISE generated .BIT, pretty much similarly as EDK is doing it.
So if all that's needed is this, just include one tiny button in
ISE to do this... can't be so hard, can it? If any such scripts are
freely available, please point me to them. Thanks!
-Jim
Article: 83281Anybody can advise me to configure the RocketIO attribute correctly to emulate TLK3101 or TLK2501 SerDes. John.Article: 83282
I'd like to double check my assumptions about using the Spartan 3 DCM in combination with a BUFGMUX. I am trying to use a BUFGMUX as input to the clk pin of the DCM so that I can switch between 2 clock sources. In this regard, I assume that each clk input goes through an IBUFG, the outputs of these IBUFs feed into the inputs of the BUFGMUX, and the output of the BUFGMUX then feeds the clk pin of the DCM. The output of the DCM uses both clk0 and clk2x, both of which feed into the inputs of yet another BUFGMUX. The reason for this configuration is that when I use one clock input I want to double its frequency (clk2x) while for the other clock I just want clk0. Is there anything wrong with this configuration? A related question is the inclusion of "defparam DCM_INST.CLK_FEEDBACK = "1X";" (In Verilog template.) I presume that the other value can be "2X". Since I am using external feedback, does this parameter matter, or does switching between clk2x and clk1x make a difference?Article: 83283
>The online tool does not really help if you are planning on getting the >best perfomance yeild off the FPGA, and need to know the power >constraints before hand. I think the problem is that the worst case is so nasty that it isn't interesting. Can you go backwards? How much power can you get rid of? How big a heat sink and/or fan are you going to have? There isn't much need for a power supply to put out more than that. Maybe 2x or 10x if you want to run in short bursts. Another approach is to look at several prototyping boards and see what they have. If you don't hear complaints about it here that's probably big enough. You could also add some big connection points so at worst you can add wires over to an external power supply. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 83284
Where is the initialization of Sincos_Rom? Mohammed A Khader wrote: > Hi all, > > I am using Synplify Pro for synthesis. My target FPGA is APEX20KE. I > have the following code for rom but the attribute rom_style is not > working instead it gave me the following warnings. > > 1) CL159 Input addrs_in is unused > 2) Signal sincos_rom is undriven > > > entity Lookup is > port( > Addrs_In : in signed(ROM_DEPTH-3 downto 0); -- 10 bit > Data_Out : out signed(ROM_WIDTH-1 downto 0) -- 16 bit > ); > end entity Lookup; > > architecture Lookup_Synth_Arch of Lookup is > -- Declaration for Rom type > type Sincos_Rom_Type is array (0 to 2**(ROM_DEPTH-2) -1) of > WORD; > signal Sincos_Rom: SinCos_Rom_Type; > > -- Attributes to map Rom to availbale techology library > attribute syn_romstyle : string; > attribute syn_romstyle of Sincos_Rom : signal is "block_rom"; > > begin > > Data_Out <= Sincos_Rom(TO_INTEGER(Addrs_In)); > > end architecture Lookup_Synth_Arch; >Article: 83285
Dear all,
While I tried to infer SRAM in synplify7.3. It came out the
following warning. Though I see the log and 7.1 did gen the SRAM by
Block RAM. I wonder if there's any answer or solution to this warning.
Thank you very much!~
@W: Could not implement Block RAM. Is the read address registered using
the same clock as the RAM?
Article: 83286austin wrote: > http://www.xilinx.com/bvdocs/notifications/pdn2004-21.pdf > > Is the discontinue notice for somw parts that had extremely low volumes. Thanks Austin. The "port" won't be too difficult anyway :-) BertArticle: 83287
Duane Clark wrote: >It makes no sense to say that you are going to "synchronize the data bus >with some register stages". What will invariably happen when you try to >do that is that some of the portions of the data bus will occasionally >exit the last stage on different clocks. Each individual bit of the bus >may be synchronized correctly, but the bus as a whole will not, without >taking additional measures. Thank you for your answers. The external data stream I am talking about comes form an USB transceiver which sends the data synchronous to 60MHz clk which I can use in my FPGA as FIFO write clock. Under this assumption of synchronous data stream the portions of the data bus will NOT occasionally exit the last stage on different clocks, will they ? My idea was to use additional register stages to improve the performance of the data flow. Rgds AndréArticle: 83288
Hi Bert, > You sure you define your address as SIGNED ??? I have also synthezied with unsigned but the same error persist. > It's also asynchronous. Maybe a clocked process ? > did you simulate ? Its a part of a design , so I have to add some more logic after the Rom Output. I have used a different architecture for simulation which does the initialization of ROM from a file but rest is same. Yes, I have simulated and it worked. But after learning the APEX20KE ESBs I am thinking to add a register at Rom Output(to make it synchronus) and make some changes to compensate for extra cycle. I cannot initialize the ROM in a case statement with 1024 of words(tooooooo Laborious).Is there any other way to do it . I thought attribute syn_romstyle(From synplicity ) would help me in recognizing so that I could initialize the ROM Later while programming the FPGA. How do you do for such cases. Thanks a lot. -- Mohammed A Khader.Article: 83289
Hi ken, Rom is having 1k of 16bit words. Hence I could'nt initialize it in a case statement. I thought attirbute syn_romstyle would help me in this . Is there any other way to do it . Thanks . -- Mohammed A Khader.Article: 83290
Hello, Thanks for the responses. The reason I need to do it is because I get a (signed) quotient from a divider in a range I already know. I divide a 8x8 DCT by 1 out of 2 preset Quantization matrices, which in turn are scaled by an integer ranging from 1-32. Sometimes I will get a 0 from the divider, during this case I don't want to transmit "too many" bits. I do however realise that this might be impossible, but I appreciate answers given me here. Thanks, DanArticle: 83291
Thank you for the response, I am making a simple 640x480 24bit graphics card which can be updated through the PCI bus. The core reads the current pixel to display using the contents from the onboard SRAM. I am using AVNET's S3-1500 demonstration board with onboard Cypress SRAM 1MB (32bit). It also resides an ADV7123 Triple Video DAC converter for video display (RGB- 8 bits each). I only need to update a 2D image on the screen which will only display text images not moving graphics, for instance a simple touch screen menu. Whats double buffering? Is it more suitable for the current application. Also cant i just use the serial port for updating the contents of SRAM since its just a text image? Furthermore, what might happen if I try writing to a specific address while the graphics core is access it for reading? Thanks "DerekSimmons@FrontierNet.net" <DerekSimmons@FrontierNet.net> wrote in message news:<1114521095.744784.299120@f14g2000cwb.googlegroups.com>... > When you say VGA what do you exactly mean? VGA was an implementation of > a graphics adapter made by IBM. It became the standard for PCs because > other venders picked it up and supported it on the PC. > > Are you trying to create an implementation of a VGA card or are you > trying to create display card for displaying images from a PC using the > PCI bus? > > DerekArticle: 83292
On Wed, 27 Apr 2005 11:42:58 +0000, Uwe Bonnes wrote: > In comp.arch.fpga license_rant_master <none@nowhere.net> wrote: > : I am an ASIC engineer who frequently 'takes work home' with me. > : Recently, I began using ssh to remotely login to our company's > : servers to run some Verilog/VHDL simulations. Launching > : sims (from the UNIX command line) is fairly easy and painless, > : but any kind of interactive (GUI) operations are pitifully > : slow over an WAN/internet connection. In the past, I > : haven't needed to do much more than check on running jobs, > : restart them, then logout. Now, I find the need to do some > : interactive debugging work (waveform viewing, code editing, > : etc.) > > Look at NX. It what LBX (Low Bandwidth X ) promised, but NX > delivers. Probably not to easy to set yet, but worth a try. > It's easy enough to set up the server (either look at the commercial version from www.nomachine.com, or google for "freenx" or "nxserver") on linux, and clients are even easier (download free from nomachine). It is said to be usable over a modem connection - I have certainly found it works well over ADSL for most work. It's definitely faster than tightVnc (which is also okay for many things - and works well for pretending you are sitting at your office windows desktop). > ByeArticle: 83293
Mohammed A Khader wrote:
>Hi ken,
>
> Rom is having 1k of 16bit words. Hence I could'nt initialize it in a
>case statement. I thought attirbute syn_romstyle would help me in this
>.
> Is there any other way to do it .
>
> Thanks .
>
>-- Mohammed A Khader.
>
>
>
You can define a constant array of integers (even put it in a separate
package) for the rom contents. You'll need to also have functions to
convert the array of integers into the init generics and attributes for
the BRAMs. The advantage of doing it this way is that it is relatively
easy to handle data that is bit sliced over several BRAMs (the init
value function can take care of this) using plain text data. The
integer array constant can be easily copied from Excel or Matlab and
pasted into the constant declaration.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 83294Hello, license_rant_master wrote: > 1) Modelsim/PE "Personal Edition" -- *exact* same license agreement > as their premiere Modelsim/SE. > > "Mentor Graphics > grants to you, subject to payment of appropriate license fees, a > nontransferable, nonexclusive license to use > Software solely: (a) in machine-readable, object-code form; (b) for your > internal business purposes; and (c) on > the computer hardware or at the site for which an applicable license fee > is paid, or as authorized by Mentor > Graphics. A site is restricted to a one-half mile (800 meter) radius." My understanding of "on the computer hardware or at the site for which an applicable license fee is paid" is that it can be either used on different computers at the same site *or* on one computer at different locations, i.e. a portable computer. Am I wrong? PaulArticle: 83295
Moti Cohen wrote:
>Hi all,
>I would like to get into a CAM design for FPGA.
>Does any of you know about where can I find material on this subject? I
>will appreciate stuff like tutorials and reference designs (examples in
>any HDL)..
>
>Thanks in advance, Moti.
>
>
>
How big a memory do you need? How sparse is it?
For small CAMs, you can use the Xilinx SRL16 capability to essentially
make custom LUTs that are dependent on the stored words. These take 16
clocks to write, but provide an address look-up in a single cycle once
they are programmed. I believe Xilinx has an app-note on this
technique. I think you can extend the idea to use a BRAM as well,
although the write time starts getting unreasonably large.
As your allowed time for access increases, so do your options. Let us
know what your requirements are, and perhaps one of us can steer you to
a solution that works for your case.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 83296Your port is a bunch of wires that represent your results. If you want to transmit the result in one clock cycle and you have 4096 different results from your 12-bit divider there is no way you can get along with less than 12 bits, you need them to distinguish the different results. In that case a 0 bit is not unused: It is used to tell the receiver that it is not 1. If you know in advance that ALL your results are allways less than 2**N you can get along with less bits. To be exact: If you know that you will have less than 2**N different results you can get along with N bits, no matter how large the results are. Kolja Sulimma Dan Nilsen wrote: > Hello, > > Thanks for the responses. > > The reason I need to do it is because I get a (signed) quotient from a > divider in a range I already know. I divide a 8x8 DCT by 1 out of 2 > preset Quantization matrices, which in turn are scaled by an integer > ranging from 1-32. Sometimes I will get a 0 from the divider, during > this case I don't want to transmit "too many" bits. I do however > realise that this might be impossible, but I appreciate answers given > me here. > > Thanks, > > DanArticle: 83297
xilinx_user wrote: > I'd like to double check my assumptions about using the Spartan 3 DCM > in combination with a BUFGMUX. > > I am trying to use a BUFGMUX as input to the clk pin of the DCM so > that I can switch between 2 clock sources. > > In this regard, I assume that each clk input goes through an IBUFG, the > outputs of these IBUFs feed into the inputs of the BUFGMUX, and the > output of the BUFGMUX then feeds the clk pin of the DCM. > This sounds reasonable as long as you reset the DCM after switching clock inputs. > The output of the DCM uses both clk0 and clk2x, both of which feed into > the inputs of yet another BUFGMUX. The reason for this configuration is > that when I use one clock input I want to double its frequency (clk2x) > while for the other clock I just want clk0. > When you say DCM "uses both clk0 and clk2x" , do you mean for feedback? You can't change the feedback path from clk0 to clk2x without changing parameters, and thus not in the same design. If you mean both outputs are used for the downstream logic this is O.K. > Is there anything wrong with this configuration? > > A related question is the inclusion of "defparam DCM_INST.CLK_FEEDBACK > = "1X";" (In Verilog template.) I presume that the other value can be > "2X". As noted above you can't change the feedback type without re-loading the bitstream, so it can't change dynamically in one design. However it sounds like what you want is to always use clk0 for feedback on the DCM and feed either clk0 or clk2x (depending on requirements for doubling) to the downstream logic. This should work O.K. > Since I am using external feedback, does this parameter matter, or does > switching between clk2x and clk1x make a difference? The parameter tells the DCM whether it needs to divide the feedback clock to match the input clock and will definitely matter. Any DCM should not change the feedback path within the same design. Changing the feedback path to 2X does not cause clock doubling. The clk2x output always has 2x the input frequency. You shouldn't need to use 2x feedback unless you need precise alignment of the 2x clock to the input. If you can live with the normal clk0 to clk2x skew you should be O.K. The external feedback path requires either clk0 or clk2x to be tied directly to an OBUF or the tools complain and give up. Are you trying to regenerate the clock for external devices? If not you don't really need external feedback. In any case you can't use the output of your BUFGMUX for feedback. You need a separate path from the clk0 output to your DCM feedback. The Virtex 2 user guide has a very good write-up on using the DCM (this is not the datasheet). see: http://direct.xilinx.com/bvdocs/userguides/ug002.pdfArticle: 83298
license_rant_master wrote: > (c) on > the computer hardware or at the site for which an applicable license fee > is paid, or as authorized by Mentor > Graphics. A site is restricted to a one-half mile (800 meter) radius." > > *RIDICULOUS* If I were a design-consultant, and my laptop were > my primary compute platform, how am I supposed to comply with a > 'site' radius? By their language, I can't run Modelsim > if I drive more than 0.5mi from my home-residence/business?!? As someone fluent in Verilog you surely know the meaning of the word "or", don't you? So if you license it for a certain computer hardware you can take that hardware werever you want in full complience with their license. Seriously: Your boss can call your distributor and ask them to extend the license to the company site plus the workplace of one teleworker. This should be no hassle. If you purchase or download software at home (e.g. not signing a site license contract) you perform a purchase instead of licensing the software and the principle of first sale applies. The manufacturer has no right to control who runs the software where, as long you there allways is only a single copy. (Disclaimer: IANAL) Kolja SulimmaArticle: 83299
On Wed, 27 Apr 2005 11:43:00 GMT, Rene Tschaggelar <none@none.net> wrote: >The whole is solved by a notebook being the work machine at >the expense of reduced performance. > >But yes, the whole is a bit silly. ..and of course entirely unenforceable in practice, unless they insist you have a GPS receiver on the machine.... How is anyone ever going to know where you physically are when you use it ?
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