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Messages from 86975

Article: 86975
Subject: Re: Announce: Impulse C-to-RTL Version 2 now available
From: "David Pellerin" <dpellerin@verizon.net>
Date: Mon, 11 Jul 2005 23:17:28 GMT
Links: << >>  << T >>  << A >>
>>I am not really convinced of basic un RTL C to RTL conversion myself,
>> since its already possible to write  RTL in C to some degree
>
> The problem is that any HDL language is still timed and you have to sort 
> out the concurrency.

That's exactly right. We (Impulse) are not going to pretend that "RTL in C" 
is a useful replacement for VHDL and/or Verilog programming. As has been 
pointed out, if you need to decompose the problem to the level of 
register-by-register, clock-by-clock behaviors, then there is little benefit 
to rewriting in C. There is also little benefit in doing "baby applications" 
(small filters and the like) in C if there are already existing hand-crafted 
hardware equivalents or pre-optimized library blocks (Simulink or otherwise) 
available to you.

So we don't do "RTL in C".

What we are promoting is a way to develop larger, highly parallel software 
applications in C, and to compile these applications into hardware without 
HDL programming. These applications represent untimed behavior (no explicit 
clocks or resets, little or no explicit description of parallel vs. 
sequential statements). We optimize the code for parallelism by scheduling 
operations, identifying clock boundaries, pipelining loops, and other 
techniques. We also provide CSP-like functions (in a C-compatible library) 
useful for creating larger parallel systems using a "processes and streams" 
programming model. These parallel systems of processes can span embedded 
processors and FPGA fabric in platforms such as the Xilinx Virtex-4 and 
Altera Nios 2.

Again, the goal with this tool is to allow software programmers access to 
FPGAs, not to replace existing hardware design methods. A secondary goal is 
to provide hardware designers a faster way to generate hardware (whether a 
prototype or an actual end-product) using software-to-hardware compiler 
tools. If the result is a prototype, then perhaps the hardware-savvy 
engineer will eventually replace the generated code with hand-crafted HDL. 
We aren't offended when that happens, though as FPGAs and their applications 
grow larger (and the compilers get better and better) we'll see that sort of 
hand-optimizing happening less and less often.

The analogy of C and assembly is a good one: there are many application 
domains (DSP for example) where assembly code is still the best approach, 
but as C compilers have improved and applications have grown larger, the 
need for assembly-level programming has diminished. VHDL and Verilog are the 
assembly languages of FPGAs.

Comparisons to other tools? Well, there's that villa in France, for one 
thing... But I'll leave it there, because this isn't the right forum for 
competitive comments and blatant sales pitches. There are some good 
C-to-hardware tools out there, and we believe we have some unique 
advantages, price being just one of them. We have 30-day evaluation software 
(with many examples) available free on request.

David Pellerin



Article: 86976
Subject: Testbenching and verification
From: "Paul Solomon" <psolomon@tpg.com.au>
Date: Tue, 12 Jul 2005 09:47:57 +1000
Links: << >>  << T >>  << A >>
Hi All,

I am using Quartus and I have acess to Modelsim, and I have been working on 
a project that is RF based containing lots of filters and other demodulation 
elements. As I have been going along writing each filter etc, I have been 
testing it by downloading the finished code to my board and then looking at 
the output of a filter etc on a spectrum analyser and deciding 
(subjectively) if it looks right or not. I dont feel this is the right way 
to go however and I wanted some advise on how you would do test benching on 
such a project. I have little experience here so I am sure that any advise 
would be helpful.

I have seen examples using all the testbench directives such as $DISPLAY 
etc, but I dont think that Quartus likes these directives being in its final 
code. Also I have writted simulation models for Matlab to confirm the 
concepts before I write the verilog modules, so if there was someway of 
comparing a Matlab module to a Verilog module then that would be fantastic.

If anyone could give any advise then that would be most appreciated.

Regards,

Paul Solomon 



Article: 86977
Subject: Re: Ethernet reference design for ML310?
From: "Joseph" <joeylrios@gmail.com>
Date: 11 Jul 2005 17:36:02 -0700
Links: << >>  << T >>  << A >>
Thanks for the response Mike.  I have tried two different approaches
and in each I have come up with errors I can't get around.

First I tried including the PCI bridge core to the base linux design
that Xilinx provides, I realized that it would be better to see how a
PCI bridge is included by the Base System Builder so I made a dummy
system with PCI capability.  Found out I also need a pci_arbiter and
another DCM module.  The number of connections and ports were a bit
overwhelming to do by hand so I abandoned trying to 'upgrade' the base
system provided.

I instead tried to build a system from scratch that had all the parts
the provided reference system had but with a PCI bridge and arbiter.
Went through and made minor adjusments to some parameters in the
software platform settings and the address mappings and built my BSP.
When I try and generate my bitstream, I get an error in PAR:

ERROR:Place:249 - Automatic clock placement failed.  Please attempt to
analyze
   the global clocking required for this design and either lock the
clock
   placement or area locate the logic driven by the clocks so that that
the
   clocks may be placed in such a way that all logic driven by them may
be
   routed.  The main restriction on clock placement is that only one
clock
   output signal for any Primary / Secondary pair of clocks may enter
any
   region.  For further information see the "Global clocks" section in
the V-II
   Hand-Book (Chapter 2: Design Considerations)

This worries me because I didn't make any changes to what the base
system builder generated that should affect placement (or so I think).
What should I look at to fix this sort of error?  I do see that I have
more DCM modules than the reference system (4 vs 2) due to the
inclusion of PCI.  Any advice on where I should look or an explanation
of this error (did some searching on it and no reference to this error
with 6.3i)?

I can provide more detail if it is helpful...

Thanks,
Joey


Article: 86978
Subject: QII simulation annoyance
From: tns1 <tns1@cox.net>
Date: Mon, 11 Jul 2005 18:21:46 -0700
Links: << >>  << T >>  << A >>
Many of the nodes I want to probe seem unavailable in the simulation. 
They are either optimized away, or refuse to show up in the simulation 
window even when selected in the vwf.

Is there a way to prevent this from happening such as a setting an 
optimization level or marking registers so they will be available?

thanks


Article: 86979
Subject: Unrolled Pipeline Implementation
From: "Paul Solomon" <psolomon@tpg.com.au>
Date: Tue, 12 Jul 2005 11:57:15 +1000
Links: << >>  << T >>  << A >>
Hi Guys,

I am writing some verilog to implement an unrolled pipeline for a vector 
mode cordic function.

What I end up having is a bunch of repeating statements with slight 
differences, such as..

  if (y[3] > 0) begin
   x[4] <= x[3] + {{3{y[3][W-1]}},y[3][W-1:3]};
   y[4] <= y[3] - {{3{x[3][W-1]}},x[3][W-1:3]};
   z[4] <= z[3] + 14'b00000010000000;
  end else begin
   x[4] <= x[3] - {{3{y[3][W-1]}},y[3][W-1:3]};
   y[4] <= y[3] + {{3{x[3][W-1]}},x[3][W-1:3]};
   z[4] <= z[3] - 14'b00000010000000;
  end

I was wondering is there is anyway to code this in verilog so that this is 
only written once and I could have the number of itterations, (or 
repetitions in this case for the unrolled pipeling) as a parameter?

This would make the code more versitile as in some cases the pipeline needs 
to be only 6 long and in others it needs to be 11, and having 2 seperate 
files to do this seems wrong.

Regards,

Paul Solomon 



Article: 86980
Subject: Re: Unrolled Pipeline Implementation
From: Ray Andraka <ray@andraka.com>
Date: Mon, 11 Jul 2005 22:33:58 -0400
Links: << >>  << T >>  << A >>
Paul Solomon wrote:

>Hi Guys,
>
>I am writing some verilog to implement an unrolled pipeline for a vector 
>mode cordic function.
>
>  
>
Use hierarchy.  Create a parameterized component that is one iteration, 
with the iteration number being a parameter, then in the next level up 
you instantiate these components.  This is one of those instances where 
VHDL is easier than Verilog.  With VHDL, you use a generate statement to 
instantiate as many of the interation components as you need.  The 
generate loop index gets plugged right into the iteration number generic 
for the iteration component and viola, an unrolled CORDIC processor that 
is parameterized for the number of iterations.  Verilog 2000 has a 
generate capability, but it is a little awkward passing the generate 
index as a parameter into a sub-module like that, especially if you are 
also doing placement in the code.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 86981
Subject: Re: Announce: Impulse C-to-RTL Version 2 now available
From: "gallen" <arlencox@gmail.com>
Date: 11 Jul 2005 21:06:19 -0700
Links: << >>  << T >>  << A >>
*snip*
>The analogy of C and assembly is a good one: there are many application
>domains (DSP for example) where assembly code is still the best approach,
>but as C compilers have improved and applications have grown larger, the
>need for assembly-level programming has diminished. VHDL and Verilog are the
>assembly languages of FPGAs.

I disagree.  VHDL and Verilog are the C/C++ of FPGAs.  They're pretty
good, they're reasonably optimized, but they'll never take full
advantage of the hardware features that are available in structural
netlists (which are the assembly of FPGAs).  VHDL and Verilog replaced
structural netlists (mostly) because they were higher level, quicker
and easier to write.  Synthesized C is the Java of FPGAs.  It's
passable, but will nevery be as efficient or well suited for the task
as the lower level languages.

Good day,
Arlen


Article: 86982
Subject: Quartus 5.0sp1 -- Error: Unexpected error in JTAG server -- error
From: Tommy Thorn <foobar@nowhere.void>
Date: Tue, 12 Jul 2005 04:23:12 GMT
Links: << >>  << T >>  << A >>
I figure I should finally ask about this problem that I've had with 
every Quartus version I've used (since pre-4.2): The built-in programmer 
in Quartus stops working after a few sessions -- always.  Typically I 
get one or two successful programming done (using a Nios Dev kit, 
Cyclone ed) before it fails with:

  Info: Started Programmer operation at Mon Jul 11 20:54:11 2005
  Error: Unexpected error in JTAG server -- error code 33
  Error: Operation failed
  Info: Ended Programmer operation at Mon Jul 11 20:54:11 2005

At this point any attempt at programming is futile and will just repeat 
the error above.  However, closing the programmer window/tab and 
relaunching Tools/Programmer makes it work again for a bit. It's really 
kind of annoying, but googling for a solution to the problem didn't turn 
up anything.

While we're at it, why isn't the programmer integrated into the build 
instead of forcing a manual invokation?

Thanks,
Tommy (fpga at numba-tu.com)


Article: 86983
Subject: Re: Quartus 5.0sp1 -- Error: Unexpected error in JTAG server -- error code 33
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 12 Jul 2005 08:02:07 +0200
Links: << >>  << T >>  << A >>
"Tommy Thorn" <foobar@nowhere.void> schrieb im Newsbeitrag
news:QAHAe.3899$p%3.23990@typhoon.sonic.net...
> I figure I should finally ask about this problem that I've had with
> every Quartus version I've used (since pre-4.2): The built-in programmer
> in Quartus stops working after a few sessions -- always.  Typically I
> get one or two successful programming done (using a Nios Dev kit,
> Cyclone ed) before it fails with:
>
>   Info: Started Programmer operation at Mon Jul 11 20:54:11 2005
>   Error: Unexpected error in JTAG server -- error code 33
>   Error: Operation failed
>   Info: Ended Programmer operation at Mon Jul 11 20:54:11 2005
>
> At this point any attempt at programming is futile and will just repeat
> the error above.  However, closing the programmer window/tab and
> relaunching Tools/Programmer makes it work again for a bit. It's really
> kind of annoying, but googling for a solution to the problem didn't turn
> up anything.
>
> While we're at it, why isn't the programmer integrated into the build
> instead of forcing a manual invokation?
>
> Thanks,
> Tommy (fpga at numba-tu.com)
>

this due the quartus tools are organized

programmer is separate application, but actual programming is done by
jtagserver which again runs as separate application/process

the error 33 simple means that programmer application can not talk to
jtagserver anymore, as example the jtagserver may be stalled or terminated
because of internal software error.

in your case the relaunch of the progtrammer fixes the problem i would say
the jtagserver died and self terminated, you can look in task manager if it
is still alive

but no matter what my guess is that the error 33 is FATAL and you can not do
anything excpet waiting for service pack

Antti






Article: 86984
Subject: Clock recovery in FPGA at 300 MHZ
From: praveen.kantharajapura@gmail.com
Date: 11 Jul 2005 23:11:58 -0700
Links: << >>  << T >>  << A >>
Hi all,

I want to implement a clock extraction circuit from data at 300 Mbps.
What i wanted to know is that is it really feasible in FPGA's( CYCLONE
II).

 Is any reference design available on clock extraction circiuit.

 Thanks in advance 

Regards,
Praveen


Article: 86985
Subject: Re: Search for FPGA
From: usenet_10@stanka-web.de (Thomas Stanka)
Date: 11 Jul 2005 23:18:30 -0700
Links: << >>  << T >>  << A >>
"Antti Lukats" <antti@openchip.org> wrote:
> "Thomas Reinemann" <Thomas.Reinemann@masch-bau.uni-magdeburg.de> schrieb:
> > I'm looking for a small FPGA which needs only one voltage source and has
> > about 10 kByte internal RAM.Since we have experience with Xilinx, I
> > would prefer a Spartan, but they need three voltages. That's right?
>
> almost all devices need more than one voltage, with the exception of
> LatticeXP that comes in several variants and can be powered from single 3.3V
> supply. Ah ok the ProAsic3 is also single voltage capable but to my
> knoweledge there is no ProAsic3 shipping at the moment. Butr Lattice XP10
> should be already available.

Actel ProAsic Plus is also single voltage capable and should be still
available. No need to look at the newest technology when searching
small fpgas :=).

bye Thomas

Article: 86986
Subject: Re: QII simulation annoyance
From: ALuPin@web.de
Date: 12 Jul 2005 01:09:10 -0700
Links: << >>  << T >>  << A >>
Are you talking about functional simulation of your code,
rtl functional simulation or rtl timing simulation ?

Rgds
Andr=E9


Article: 86987
Subject: Re: Connecting TigerSharc TS201 EzKIT to PCI with Spartan 3
From: "katherine" <weston_katherine@yahoo.co.uk>
Date: 12 Jul 2005 02:31:08 -0700
Links: << >>  << T >>  << A >>
Transtech DSP were doing stuff with tigersharcs and FPGAs. It was some
time ago that I looked but I'm fairly certain I saw a block diagram
with a link going to an FPGA.

Elder Costa wrote:
> Hello.
>
> I want to control an ADSP-TS201S EZ-KIT Lite from a PC by connecting it
> to an Avnet evaluation kit which contains a Spartan 3 on a PCI form
> factor through one of the EZ-KIT link ports pairs. My application data
> throughput is not very demanding so it=B4s my understanding I can
> program the SPD bits to divide the 500MHz CCLK by 4 giving me a
> transfer clock of 125MHz (transfer rate of 250Mbps) wich is much higher
> than I need (I wish I could reduce it even more - 100 or even 50MBps
> would do just fine). So my first question is if Spartan 3 (-4 grade to
> stay in the worst case) would allow such a rate reliably. May I clock
> the receiving side at a lower rate then the trasmitter?
>
> I also would like to know if somebody could indicate resources other
> than Xilinx=B4s xapp634/xapp635, including commercial cores. Google
> hasn=B4t been of much help unfortunately. I am also considering other
> ways (Bittware=B4s ASIC, AMCC=B4s Matchmaker etc.) to do the final design
> but the scheme above seems to be the simplest that would allow me to
> develop with TS before I have a workable prototype (I may be missing
> something though and would appreciate your inputs.)  If it works fine I
> may even use it in the final design as it=B4s going to have a FPGA (much
> likely a Spartan 3) anyway.
>=20
> Thank you very much in advance for your insights.
>=20
> Elder.


Article: 86988
Subject: Re: Xilinx MAP problem (>1 External Macro Output Pin on single net)
From: "Ian" <i.colwill@sussex.ac.uk>
Date: 12 Jul 2005 03:19:55 -0700
Links: << >>  << T >>  << A >>


Gabor wrote:
> Ian wrote:
> > Hi Everyone,
> >
> > I would be really for any help or advice you can offer me on the
> > following.
> >
> > I have created a simple tri-state bus as a macro using xdl. The design
> > consists of two TBUFs driving a single long line.
> >
> > (Diagram at http://www.comms.scitech.susx.ac.uk/~ian/files/tbuf.gif)
> >
> > <img src="http://www.comms.scitech.susx.ac.uk/~ian/files/tbuf.gif">
> >
> > I attach external macro pins to Out, Enable and In of each TBUF.
> > However, when I try to include the macro in a design, the DRC in the
> > map phase complains that the Out pin is being driven by two sources.
> > MAP Error Message:
> >
> >
> > ERROR:MapLib:22 - Bus M0_DATA_LEFT_O_OBUF driven by bm_instance and
> > bm_instance has multiple active drivers.
> >
> >
> > This is not correct, as the O pins are external macro outputs! Is there
> > anyway to prevent this?
> >
> > Xilinx don't list any help for this Error.
> >
> > /Ian.
>
> What device are you targetting?  Newer FPGA's don't have TBUF's
> anymore.  CPLD's never did...




I am targeting Spartan 2 devices.


Article: 86989
Subject: FPGA to ASIC + JTAG chain insertion
From: Laurent Gauch <laurent.gauch@DELETEALLCAPSamontec.com>
Date: Tue, 12 Jul 2005 13:16:03 +0200
Links: << >>  << T >>  << A >>
Hi all,

We have to do a FPGA-to-ASIC conversion with JTAG chain insertion.

The design was tested on spartan-II and was converted to ATMEL MG2 
successfully via Leonardo Spectrum (functional test and sdf timing).

Now we have to use MENTOR DFT Suite for the JTAG insertion and test 
coverage.

The documentation from MENTOR is very complet, and/or maybe a bit too 
complet.

My questions is:

Do you have any experience with the MENTOR DFT Suite.
Are there any application note, paper ... resuming experiences with this 
design flow?

Thank you in advance,

Laurent Gauch
www.amontec.com

Article: 86990
Subject: Re: Clock recovery in FPGA at 300 MHZ
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Tue, 12 Jul 2005 13:56:17 +0200
Links: << >>  << T >>  << A >>
Hi praveen,

> Hi all,
> 
> I want to implement a clock extraction circuit from data at 300 Mbps.
> What i wanted to know is that is it really feasible in FPGA's( CYCLONE
> II).
> 
>  Is any reference design available on clock extraction circiuit.

Altera has two reference designs for Cyclone I that do clock/data recovery
at 270MHz for DVB/ASI and SDI. It may be possible to crank this up to
300MHz when using the fastest speed grade Cyclone but it's going to be
tricky.

Best regards,


Ben


Article: 86991
Subject: Xilinx PLEASE HELP
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 12 Jul 2005 15:37:08 +0200
Links: << >>  << T >>  << A >>
why is it so that whatever I do, I am stuck with (Xilinx) problems?! I need
urgently, within 2 days to implement a programming solution for XCF08P,
unfortunatly the only devices for whicht the IEEE1532 BSDL files are not
available are exactly the XCFxxP series Platform Flash !!!

Allmost all other devices have proper ieee1532 files available. For XCF08P
impact is able to generate the .ISC file ok, but when I try to generate a
SVF file from ISC (in order to reverse the ISC commands) then of course
impact complains about missing bsdl files, giving an error, and soon after
that there comes C asserition error

FATAL_ERROR: WinAPP.C:710

then of course follows quick self termination!!!

nice! thats 3 days after the release of 7.1 SP3

Antti
if anyone (in or outside Xilinx) can help in either obtaining the ieee1532
BDSL files or proper programming specs for XCFP platform flash, I would be
very glad :)
I really dont wanna go reverse engineerinf the SVF files in order to get the
programming algorithm.





Article: 86992
Subject: Xilinx Conversion 3.1 --> 6.1
From: "Max" <softwareNOSPAM@udicom.it>
Date: Tue, 12 Jul 2005 13:49:59 GMT
Links: << >>  << T >>  << A >>
Hi all,
i have an old xilinx project developed with version 3.1 (schematic file)
Now i work with Xilinx Project Navigator v.6.1
I'm unable to open it. There is any way to convert schematic from 3.1 to
6.1?

Thank's in advance

Max

Udicom




Article: 86993
Subject: Re: Xilinx Conversion 3.1 --> 6.1
From: "Gabor" <gabor@alacron.com>
Date: 12 Jul 2005 07:22:09 -0700
Links: << >>  << T >>  << A >>
Max,

Unfortunately your old schematic is in a proprietary Aldec
format.  Xilinx no longer uses Aldec for their ISE environment.

You have few options.

1. If you just need to update and build the old project for
the original parts (that were supported in version 3.1) the
best bet is to continue to use 3.1 - I am using 4.1 (the last
of the Aldec-based versions) on the same machine with 6.1
and all I need to do is change my Xilinx environment variable
to switch between modes.

2. Use the export option in version 3.1 schematics to generate
structural VHDL code from your old schematic.  This code will
of course lose your graphics and text comments, but with some
coercing can be made to compile under ISE (you may need to
add some library elements that are no longer in unisims).  It
may actually be less work to re-create the schematics by hand.

3.  Hand Aldec a pile of money for their latest tools which
allow you to continue using your old schematics while running
the latest Xilinx back-end.

Max wrote:
> Hi all,
> i have an old xilinx project developed with version 3.1 (schematic file)
> Now i work with Xilinx Project Navigator v.6.1
> I'm unable to open it. There is any way to convert schematic from 3.1 to
> 6.1?
> 
> Thank's in advance
> 
> Max
> 
> Udicom


Article: 86994
Subject: Re: QII simulation annoyance
From: tns <tns1@cox.net>
Date: Tue, 12 Jul 2005 07:34:24 -0700
Links: << >>  << T >>  << A >>
I see only two types of simulation in QII, functional and timing. I have 
tried both, and they both have this problem. The project I am trying to 
simulate has both verilog and VHDL files. It is a subset of the entire 
project, so I just take the part I want to simulate and create a new 
project around it. I don't have a .pin file. Do I need one?

In the node finder, I can search for registers or 'design entry' to see 
all objects. Many of the objects I select for my vwf will not show up in 
the subsequent simulation, even for functional simulations.

It sure seems like an optimization thing, since I can make the problem 
signals probe-able by tying them to known working outputs. There is also 
the problem of having nodes renamed so they are not recognizable. Isnt 
there a 'debug' mode of simulation that will preserve all nodes?

ALuPin@web.de wrote:
> Are you talking about functional simulation of your code,
> rtl functional simulation or rtl timing simulation ?
> 
> Rgds
> André
> 


Article: 86995
Subject: Re: Xilinx Conversion 3.1 --> 6.1
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Tue, 12 Jul 2005 15:59:35 +0100
Links: << >>  << T >>  << A >>
I have not done it for a while but if you have the 3.1 tools I think you can 
export the design to VHDL. It isn't friendly as you basically get a vhdl 
netlist style output but it does allow then to take the output into the new 
tools.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk


"Max" <softwareNOSPAM@udicom.it> wrote in message 
news:bUPAe.149895$75.6440042@news4.tin.it...
> Hi all,
> i have an old xilinx project developed with version 3.1 (schematic file)
> Now i work with Xilinx Project Navigator v.6.1
> I'm unable to open it. There is any way to convert schematic from 3.1 to
> 6.1?
>
> Thank's in advance
>
> Max
>
> Udicom
>
>
> 



Article: 86996
Subject: Re: Unrolled Pipeline Implementation
From: "John_H" <johnhandwork@mail.com>
Date: Tue, 12 Jul 2005 16:17:06 GMT
Links: << >>  << T >>  << A >>
Verilog 2001 allows generate loops for just this sort of purpose.
The genvar variable in the loop can be used for indexing, selecting +/- and
generating the constant.
Look up the generate "for" loop in your synthesis (or simulation) tool
reference.


"Paul Solomon" <psolomon@tpg.com.au> wrote in message
news:42d32380@dnews.tpgi.com.au...
> Hi Guys,
>
> I am writing some verilog to implement an unrolled pipeline for a vector
> mode cordic function.
>
> What I end up having is a bunch of repeating statements with slight
> differences, such as..
>
>   if (y[3] > 0) begin
>    x[4] <= x[3] + {{3{y[3][W-1]}},y[3][W-1:3]};
>    y[4] <= y[3] - {{3{x[3][W-1]}},x[3][W-1:3]};
>    z[4] <= z[3] + 14'b00000010000000;
>   end else begin
>    x[4] <= x[3] - {{3{y[3][W-1]}},y[3][W-1:3]};
>    y[4] <= y[3] + {{3{x[3][W-1]}},x[3][W-1:3]};
>    z[4] <= z[3] - 14'b00000010000000;
>   end
>
> I was wondering is there is anyway to code this in verilog so that this is
> only written once and I could have the number of itterations, (or
> repetitions in this case for the unrolled pipeling) as a parameter?
>
> This would make the code more versitile as in some cases the pipeline
needs
> to be only 6 long and in others it needs to be 11, and having 2 seperate
> files to do this seems wrong.
>
> Regards,
>
> Paul Solomon
>
>



Article: 86997
Subject: Re: QII simulation annoyance
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 12 Jul 2005 09:21:06 -0700
Links: << >>  << T >>  << A >>
tns1 wrote:
> Many of the nodes I want to probe seem unavailable in the simulation. 
> They are either optimized away, or refuse to show up in the simulation 
> window even when selected in the vwf.

For complex designs, it is common practice
to write HDL source and simulate *that* using
a vhdl simulator, before running Quartus.

        -- Mike Treseler

Article: 86998
Subject: Re: Bazix introduce FPGA based One Chip computer system
From: Sander Zuidema <s.zuidema@bazix.nl>
Date: Tue, 12 Jul 2005 18:39:09 +0200
Links: << >>  << T >>  << A >>
Hello Antti,

> so I copy a bitrstream to the sd card and new computer is ready to go?
> how come? I dont see an intelligent configuration controller, only the
> serial config eprom :(

Actually the SD card can be used as a FAT16-compatible storage device,
similar to connecting a SCSI or IDE interface to a real MSX computer.
The MSX-DOS included with the device will come with a tool to change the
code inside the FPGA chip.

> the onechipmsx just promises lots of configs, anything ready ?
> commodore64 is 100% working ???
> or is it just someone wishful thinking?

The only upgrade announced and promised by Bazix is an upgrade to MSX2
compatibility. Other systems were merely mentioned to give an idea of
the potential of the device for people who are not that familiar with
FPGA as of yet.

Cheers,

Sander Zuidema


--------------------------------------
Bazix VOF
Hoge der A 30-2
9712 AE
Groningen

T: +31(0)50-3112518
I: www.bazix.nl
--------------------------------------

Article: 86999
Subject: Re: Bazix introduce FPGA based One Chip computer system
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 12 Jul 2005 18:48:07 +0200
Links: << >>  << T >>  << A >>
"Sander Zuidema" <s.zuidema@bazix.nl> schrieb im Newsbeitrag
news:11d7sh842qsp2d6@corp.supernews.com...
> Hello Antti,
>
> > so I copy a bitrstream to the sd card and new computer is ready to go?
> > how come? I dont see an intelligent configuration controller, only the
> > serial config eprom :(
>
> Actually the SD card can be used as a FAT16-compatible storage device,
> similar to connecting a SCSI or IDE interface to a real MSX computer.

thats obvious of course, would not make sense to have it otherwise at all.

> The MSX-DOS included with the device will come with a tool to change the
> code inside the FPGA chip.

hm.. by doing what? reprogramming the ASMI memory and re-inforcing config?
that sure is doable, but this may render the system unusable if power is
disconnennected during update.

or is there a cyclone runtime reconfiguration back door discovered?

or what you mean by 'code' inside FPGA, there is bitstream and there is
softcore processor, your code applies to machine codes for the softcore CPU
or for FPGA configuration data?

> > the onechipmsx just promises lots of configs, anything ready ?
> > commodore64 is 100% working ???
> > or is it just someone wishful thinking?
>
> The only upgrade announced and promised by Bazix is an upgrade to MSX2
> compatibility. Other systems were merely mentioned to give an idea of
> the potential of the device for people who are not that familiar with
> FPGA as of yet.
>
> Cheers,
>
> Sander Zuidema

ok, well so I understood that they are just mentioned, that maybe some one
some day does that...

Antti





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