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> It seems like you want to "count" the 1s in a 150-bit wide word, coming > in every 100 ns = 10 MHz. > > Here is how I would do it: > Use 6 or 7 dual-ported BlockRAMs as LUTs. > Each BlockRAM is used as a ROM, organized 4k x 4,i.e. with 12 address > bits and 4 output bits. > The ROM stores the value of the number of ones on the address inputs. > One ROM takes care of 12 inputs, but since it is dual-ported, each > BlockRAM takes care of 24 inputs, generating two independent 4-bit > outputs. > Six BlockRAMs thus cover 144 inputs, and generate 12 independent 4-bit > binary numbers in less than 4 ns. The remaining 96 ns can be used in > simpler adder structures, or in a 12-step sequential accumulator > running at, say, 200 MHz. > Peter Alfke, Xilinx Applications That's great guide for me. Thanks a lot!Article: 89676
Brad I think you need a tutorial on testbenches... The usual way is to create a design (let's call it 'design') that will be synthesized. Then you create some sort of wrapper, the testbench, usually called design_tb in which you instantiate your design and all its environment (CPU, memory, DAC, ADC... ). This is where you will also generate the clock and reset signals. Don't worry about bidirectionnal signals at the testbench level. Treat all signals the same. NicolasArticle: 89677
Quick add to my previous post: a VHDL tutorial is available here http://www.vhdl-online.de/~vhdl/tutorial/englisch/inhalt.htm, including testbenches. NicolasArticle: 89678
Thanks Subroto, you are always a great help. Rgds Andr=E9Article: 89679
Well done Mark, I designed the back end of "small C" compiler for Picoblaze. do you want to integrate the compiler with your IDE? If you are interested please go on www.poderico.co.uk and download it! I'll send you the code if you are interested. Francesco M6 wrote: > I've created an IDE for the picoblaze-3 microcontroller (Xilinx TM). > The IDE is an open-source project (GPL-license) and works under the > Linux operating system. > > The IDE supports the following: > - Editor with syntax highlighting, > - Assemble and export to: HEX, VHDL or MEM files, > - Simulate the source code and see/modify the scratchpad, registers and > I/O ports. > > For those who are interested, checkout: http://www.xs4all.nl/~marksix > > Regards, > > Mark SixArticle: 89680
could you explain your first more in depth? because i did solve this. could you also explain your nature of work with ML310Article: 89681
I have bought the PCI logicore from the xilinx inorder to communicate with the USB port of Xilinx Ml310 board. but i have to configure my user logic to enable the core to activate the communication between USB port of camera and virtex 2p. any help in this regard is appreciatedArticle: 89682
acetylcholinerd@gmail.com schrieb: > Our application is we have one main board and 3 daughter boards, up to > 1m away, and we are constrained to essentially using seven wires to > connect each daughter board to the main board. For this sort of > distance, we wanted to go LVDS in both directions, but to keep > everything synchronous, that would require that the B->D lvds pair also > contain the clock; clock recovery was going to let us still keep > everything synchronous. We knew we'd need a PLL :) > > We've decided to go with a single-ended clock/data pair on one set of > wires and a (clock-multiplied) LVDS pair for the receiver (from > daughterboard -> mainboard), Hmm. Seven wires. That is - GND - LVDS pair data D->M - LVDS pair data M->D - LVDS pair clk M->D That's enough for a synchronous system. Somehow I do not see your problem. You can use one clock for data transfer in both directions. Kolja SulimmaArticle: 89683
Hi Subroto,
I think the use of attributes in VHDL modules can be helpful for the
purpose of
clearness and readability.
Regarding tristate buffers I have the following additional question:
Let's assume the following description of a bidirectional bus with
tristate buffer:
ENTITY xy IS
PORT ( ...
DataInOut : INOUT std_logic_vector(15 downto 0);
...
END xy;
ARCHITECTURE gt OF xy IS
BEGIN
DataInOut <=3D ls_datareg WHEN ls_drive=3D'1' ELSE (OTHERS =3D> 'Z');
-- with ls_datareg and ls_drive being registers.
END gt;
What does the Altera fitter do if I use the
useioff attribute for the bidirectional DataInOut ?
Does the fitter implement fast input registers as well as fast output
registers ?
Best regards
Andr=E9
Article: 89684Hi, does anyone know where I could find on the internet resources about network architectures and switches w/ support for both best-effort and guaranteed services? Any VHDL implementation would be of particular interest. Many thanks, EricArticle: 89685
Jon Elson wrote: > stbcasa wrote: > > >Hi, > > > >I am trying to implement a schematic design. My problem is that when I > >try to assign a constant binary number to one of the two inputs of a > >comparator, I can't find the way to do it. Anyone know how it can be > >done in Xilinx schematic? Thanks in advance for your help. > > > > > You use XBLOX to create a new library part, from the "CONST" type. > You assign the value to it as needed. You need a different library part > for each constant value, kind of cumbersome, but that's how it works. > Then, you instantiate the library part on your schematic, and connect the > output bus to the input as needed. > > Jon If you only need to provide a single 1 or 0 (not a bus), use the vcc and gnd symbols provided in the libraries. In my schematics I usually attach a wire to each and label the vcc signal "V" and the gnd signal "G" for ease of use elsewhere in the schematic.Article: 89686
Same price as Digikey... and more expensive shipping. Not to mention, no volume discount.Article: 89687
Our configuration is:
GND
LVDS pair M->D
GND
LVDS pair D->M
GND
The cables we are using only have the wires 2&3 and 5&6 as "pairs"
internally.
If we break one of those pairs and run a (say) 70 MHz clock on the +
wire and a 70 MHz data stream on the -, and then just feed that clock
directly into the DCM, I think this could work... I just worry about
the SI problems with running a 70 MHz clock over 1m of cable...
Eric
Thanks,
...Eric
Article: 89688The file sizes should be exactly the same for similarly named files. I believe the only reason for a full bitstream to be a different size is if the source filenames differ. The bitstreams encode the filename of the NCD file used to produce the bitstream, so different NCD files will produce different file lengths. But, in general, the files should be the same length. To see if the bitstreams differ, I suggest a quick-and-dirty diff command (under linux or using cygwin, if you're running Windows). For more information you can diff the hexdumps of the two bitstreams.Article: 89689
There are two scenarios, and I don't know which you are going to be doing. One is to not use the FPGAas the PCI interface chip, which means you can program the FPGA through the PCI interface chip, either something like a PLX or a CPLD... Or, you want to put the PCI interface in the FPGA. If you want to do that, you will need to provide a configuration PROM...which can be programmed through the FPGA by hooking up it's programming pins to a register inside the FPGA and writing software (or attempting to use some that already exist) to reprogram it. Regards, Austin <john.orlando@gmail.com> wrote in message news:1127155888.358108.107850@g44g2000cwa.googlegroups.com... > Hello, > I am working on a new project with a Xilinx FPGA (Virtex 2 or Virtex > 4...TBD) on a PCI card (actually, a PCI Mezzanine Card (PMC), which is > the PCI interface in a slightly different form factor). Anyway, in > architecting this project, we are discussing how to re-configure the > FPGA from the host machine (in this case, a Processor PMC card running > Linux that will be doing the PCI bus enumeration). Solutions we have > discussed would be to have the ability to write to a PROM through > custom logic through the PCI bus, and then allow the FPGA to boot from > this PROM. We have also big-banged the serial-loading protocol in the > past from an ARM processor directly connected to the FPGA, but not over > PCI. > > However, with our forray into PCI, being able to load the FPGA through > the PCI bus is quite attractive. Obviously, if the FPGA is providing > the PCI bus interface, we would have the chicken-before-the-egg > syndrome (i.e., no PCI interface to load the FPGA since the PCI > interface is IN the FPGA). So what about using dedicated PCI bus > interface chips? These seem to provide a PCI interface on one end, and > a memory-interface on the other, making them pretty simple to use. But > I still don't see how this will bring the ability to re-program the > FPGA image. > > I don't need to do it on the fly while the system is up and running; I > would simply like to be able to, at power up, have the Processor PMC > card open a bitstream file it has on its local file system, dump the > bitstream down to the FPGA over the PCI interface, and then have the > FPGA start in its normal user mode. > > I've looked around a bunch and people are certainly doing this. But I > can't find many good explanations as to how its working. Are they > bit-bangging JTAG??? > > Any help is appreciated... > > TIA, > John O. >Article: 89690
Greetings, I am implementing a design whose system clock is generated by an MGT (the TXOUTCLK pin), based on higher frequency differential reference clock inputs to that MGT. The frequency generated at TXOUTCLK is correct, but the issue is that Xilinx ISE (7.1i, SP4) does not route this clock as a CLK Net. The particular error, generated after PAR, is "WARNING:Route - CLK Net: net_name may have excessive skew because xx NON-CLK pins failed to route using a CLK template." This design cannot tolerate the max skew that is reported (about 20% of a period), or the resulting max delay of about 40%. How can I force this net to use the CLK template I specified in the UCF, or otherwise remedy this issue? Thanks much, Julian KainArticle: 89691
Hello everybody, I'm interested in the implementation of a 32x32 bit multiplier (unsigned values). The target FPGA is Virtex V300e I would like to implement a system that is not too big, while I have not a lot of timing constraints. Using a behavioral approach I obtain a multiplier that needs about 17% of the FPGA, I would like to reduce this size and the target frequency is about 70Mhz. Where can I find some good manual that can help me in this task? can you give me some advice about how to code this device? Any help will be appreciated.Article: 89692
Well, maybe you can show me an example, because I simply don't get it. You say you instantiate the CPU, memory, etc, but how does the simulator know what is connected to what? Perhaps you can snip out one of your test-benches designs with bidirectional signals for me and the group? "Nicolas Matringe" <nic_o_mat@msn.com> wrote in message news:1127371032.791876.191140@g43g2000cwa.googlegroups.com... > Brad > I think you need a tutorial on testbenches... > The usual way is to create a design (let's call it 'design') that will > be synthesized. Then you create some sort of wrapper, the testbench, > usually called design_tb in which you instantiate your design and all > its environment (CPU, memory, DAC, ADC... ). This is where you will > also generate the clock and reset signals. > Don't worry about bidirectionnal signals at the testbench level. Treat > all signals the same. > > Nicolas >Article: 89693
That's a nice primer on VHDL but I don't see an example of a board design testbench. Would you care to point out the chapter? "Nicolas Matringe" <nic_o_mat@msn.com> wrote in message news:1127371215.841231.113800@o13g2000cwo.googlegroups.com... > Quick add to my previous post: a VHDL tutorial is available here > http://www.vhdl-online.de/~vhdl/tutorial/englisch/inhalt.htm, including > testbenches. > > Nicolas >Article: 89694
> Its possible to use the PLX9054 PCI bridge chip to load Xilinx FPGA in 8 > bit slave mode with no added hardware except a resistor or three. We do > this on some or our cards. > > Peter Wallace Interesting...I just downloaded the datasheet for the PLX9054 to look it over to see how it is possible accomplish this. Can you give some more details about how you actually set this up? Did you need a CPLD sitting between the PLX's local bus interface and the slave-mode programming interface? Any info here would be helpful...thanks! JohnArticle: 89695
On 22 Sep 2005 08:18:54 -0700, "Giox" <giovanniparodi79@yahoo.it> wrote: >Hello everybody, I'm interested in the implementation of a 32x32 bit >multiplier (unsigned values). The target FPGA is Virtex V300e >I would like to implement a system that is not too big, while I have >not a lot of timing constraints. Using a behavioral approach I obtain a >multiplier that needs about 17% of the FPGA, I would like to reduce >this size and the target frequency is about 70Mhz. >Where can I find some good manual that can help me in this task? can >you give me some advice about how to code this device? >Any help will be appreciated. Suppose you want to calculate p * q. If p = a * 2^16 + b and q = c * 2^16 + d then p * q = (a*c * 2^32 + (a*d+b*c) * 2^16 + b * d) which says that you can use 4 16 bit multipliers to do a 32 bit multiplication or use one 16 bit multiplier and run it over 4 cycles to get what you want.Article: 89696
Hi Francesco, I took a look at your compiler, looks nice. Perhaps I'll find the time to add your backend to the IDE. For the moment I'm busy trying to get JTAG support into the IDE. With the JTAG-option you then can update the Block RAM, and so reprogram the picoblaze. Regards, MarkArticle: 89697
Hi All I want to download bit file to the FPGA to program it w/out using any GUIs like the JTAG programmer. I need to write some kind of APIs for this. Could anyone suggest how to do this and what would be the kind of interface required for the same. please help AnujaArticle: 89698
"Anuja" <thakkar.anuja@gmail.com> schrieb im Newsbeitrag news:1127419460.738414.320340@g43g2000cwa.googlegroups.com... > Hi All > I want to download bit file to the FPGA to program it w/out using any Every datasheet explains the serial downloading procedure. Very easy to do. Also downloading via JTAG isnt too difficult. Have a look into the xapps. Regards FalkArticle: 89699
john.orlando@gmail.com writes: > I've looked around a bunch and people are certainly doing this. But > I can't find many good explanations as to how its working. Are they > bit-bangging JTAG??? I've done this. I could write data through my PCI driver to control the JTAG chain to program an 18V04 (this was long time ago on a Virtex-E device) in which my FPGA was loaded from. The tricky part is do to write the software to generate the JTAG patterns. Once you done this the rest is pretty straightforward. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z