Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 93975

Article: 93975
Subject: Remapping from Virtex-II to Virtex-4
From: "Lars" <larthe@gmail.com>
Date: 4 Jan 2006 04:06:56 -0800
Links: << >>  << T >>  << A >>
Anyone done any "what-if" remapping of Virtex-II designs to Virtex-4? I
wanted to do this to see how the new technology performed, mainly to
see if it was worth the trouble to upgrade some existing designs. We
did this quite successfully some years back, stepping from Virtex-E to
Virtex-II. The main obstacle then was the new size Block RAM going from
4kbit to 18 kbit apiece. If we left our Unisim and CoreLib components
untouched we wasted 3/4 of the RAM, but if the number of Block RAMs in
the chip was sufficient, all we had to do was to update the
LOC-constraints for pins and DCM's in the .ucf-file. ISE even managed
to re-target the Virtex-E DLLs to Virtex-II DCMs. Brilliant!

So I hoped it would be even better this time, since the Block RAMs are
the same size, but there seems to be more to this than meets the eye. I
commented out all the LOC-constraints in the ucf and had a go, after
resynthesizing to XC4VLX instead of XC2V. But alas, I get a fatal error
in MAP, complaining about SLICEL and SLICEM types of components. I
suspect that this has to do with some of our CoreLib components, since
they are the only place where there might be RLOC constraints in the
EDIF, but before I go and re-generate all these I am curious to know if
there is an easier way.

I am not out to squeeze the full performance out of the XC4VLX right
now, but would like a "ball-park" figure of what might be expected in
terms of utilization and speed, before we go ahead and commit to a
full-scale conversion. That is why I don't want to spend too much time.

Regards,
/Lars


Article: 93976
Subject: Re: DCM and buffers
From: "jerzy.gbur@gmail.com" <jerzy.gbur@gmail.com>
Date: 4 Jan 2006 05:04:47 -0800
Links: << >>  << T >>  << A >>
Hello
> feedback loop. CLK0 -> BUFG -> CLKFB.
> Is that necessary?

Yes, it is.
To CLKFB you can connect signals from BUFG or IBUFG.

> Do I have to use an IBUFG for the CLKIN of a DCM if nothing else is
> connected to that CLK signal?

Yes, you have.

Why? - it's good question for homework.

If you looking for advice here, be more specific:
- What tool you use?
- What chip-device, you want to configure?

good luck.

Jerzy Gbur


Article: 93977
Subject: Re: Remapping from Virtex-II to Virtex-4
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Wed, 4 Jan 2006 13:10:55 -0000
Links: << >>  << T >>  << A >>
One problem you have is that in Virtex-4 only half of the slices can support 
lut used as memory. In V2 all slices could be used. We have seen similar 
things in Spartan-3 particularly if you have used elements such as 32x1 ram. 
Alternative you may have tried to use a memory type lut where there isn't 
one due to using a RPM or constraint that simply isn't valid.

John Adair
Enterpoint Ltd. - Home of MINI-CAN. The Spartan-3 CAN Bus Development Board.
http://www.enterpoint.co.uk


"Lars" <larthe@gmail.com> wrote in message 
news:1136376416.676830.143490@g49g2000cwa.googlegroups.com...
> Anyone done any "what-if" remapping of Virtex-II designs to Virtex-4? I
> wanted to do this to see how the new technology performed, mainly to
> see if it was worth the trouble to upgrade some existing designs. We
> did this quite successfully some years back, stepping from Virtex-E to
> Virtex-II. The main obstacle then was the new size Block RAM going from
> 4kbit to 18 kbit apiece. If we left our Unisim and CoreLib components
> untouched we wasted 3/4 of the RAM, but if the number of Block RAMs in
> the chip was sufficient, all we had to do was to update the
> LOC-constraints for pins and DCM's in the .ucf-file. ISE even managed
> to re-target the Virtex-E DLLs to Virtex-II DCMs. Brilliant!
>
> So I hoped it would be even better this time, since the Block RAMs are
> the same size, but there seems to be more to this than meets the eye. I
> commented out all the LOC-constraints in the ucf and had a go, after
> resynthesizing to XC4VLX instead of XC2V. But alas, I get a fatal error
> in MAP, complaining about SLICEL and SLICEM types of components. I
> suspect that this has to do with some of our CoreLib components, since
> they are the only place where there might be RLOC constraints in the
> EDIF, but before I go and re-generate all these I am curious to know if
> there is an easier way.
>
> I am not out to squeeze the full performance out of the XC4VLX right
> now, but would like a "ball-park" figure of what might be expected in
> terms of utilization and speed, before we go ahead and commit to a
> full-scale conversion. That is why I don't want to spend too much time.
>
> Regards,
> /Lars
> 



Article: 93978
Subject: Re: RTL for Z8000 series CPU?
From: "Bill Davy" <Bill@SynectixLtd.com>
Date: Wed, 4 Jan 2006 13:16:44 +0000 (UTC)
Links: << >>  << T >>  << A >>

"Totally_Lost" <air_bits@yahoo.com> wrote in message 
news:1136368133.136751.34120@g44g2000cwa.googlegroups.com...
> ok, sorry for the brief break ... in 1980 Wang was chewing up the
...
> Replacing over a decade of selectric typewriters, and several years of

And how many had an 8051 to interface a Selectric to a Centrnics port as a 
printer? 



Article: 93979
Subject: Serious Typo in the Xilinx Floating-Point Core Manual?
From: "Robin Bruce" <robin.bruce@gmail.com>
Date: 4 Jan 2006 05:24:06 -0800
Links: << >>  << T >>  << A >>
http://www.xilinx.com/bvdocs/ipcenter/data_sheet/floating_point.pdf

With regard to the speed-optimised single-precision floating-point
core, look at:

Table 6: Latency of Speed Optimized Core (Page 10)
Table 10: Characterization of Speed-Optimized Single-Precision Core
(Page 18)

These are the characteristics of the speed-optimised floating-point
cores from Xilinx. For virtex-4 there's a multiplier version that
uses a single DSP48 block, as opposed to the standard 4x DSP48 version.
My question is: What's the point of it? There's a pure logic one
there that uses less slices, has a lower latency and operates
as-near-as-damn-it at the same frequency. More to the point you're not
throwing away a DSP48...

I've spoken to colleagues about this, and the best guess we can come to
is that there's a typo, most likely on the slice count for the single
DSP48 + slices version. Anyone know better?

Cheers,

Robin Bruce


Article: 93980
Subject: Spartan 3 PCI development card
From: eternal_nan@yahoo.com
Date: 4 Jan 2006 05:24:08 -0800
Links: << >>  << T >>  << A >>
Hi All,

Can anyone reccommend a good PCI development board with a spartan 3 and
some DDR SDRAM on it?

Thanks


Article: 93981
Subject: Re: Timing problem in ModelSim, Post-Route Simulation.
From: "Dan NITA" <dnita@digitalsurf.fr>
Date: Wed, 4 Jan 2006 14:36:42 +0100
Links: << >>  << T >>  << A >>
Hello,

> I don't think the .TWR example is complete since I'd expect to see some
> additional delay like clock-to-Q of the first synchronous element in
> the list. But in general I'd expect to see ROUTE delays of the TRACE
> report that match the INTERCONNECT delays of the SDF.

Indeed, the route delays of the Trace report matches the interconnect delays
of the SDF. That is OK.


>
> I wonder if the SDF file is simply out of synch with the TRACE report?
> Or maybe you're overriding the speed grade with TRACE? See Tools >
> TRACE Options... in the Project Navigator. Also check the SDF setup in
> ModelSim. See Simulate > Start Simulation... and the SDF tab where you
> can specify the Min|Typ|Max delay to be applied.

I will investigate this Multi-Source Delay options on the SDF tab. Thanks
for all
the suggestions.




> Troy Scott
> Lattice Semiconductor TME


Dan.



Article: 93982
Subject: Re: Remapping from Virtex-II to Virtex-4
From: "Lars" <larthe@gmail.com>
Date: 4 Jan 2006 05:42:39 -0800
Links: << >>  << T >>  << A >>
Aha! I knew that, but the access to that particular memory cell in my
decaying brain was not operating at the time. That would make it hard
to re-target CoreLib components I suppose...

Thank's for setting me straight!
/Lars


Article: 93983
Subject: Re: Remapping from Virtex-II to Virtex-4
From: Ray Andraka <ray@andraka.com>
Date: Wed, 04 Jan 2006 08:52:54 -0500
Links: << >>  << T >>  << A >>
Lars wrote:
> Anyone done any "what-if" remapping of Virtex-II designs to Virtex-4? I
> wanted to do this to see how the new technology performed, mainly to
> see if it was worth the trouble to upgrade some existing designs. We
> did this quite successfully some years back, stepping from Virtex-E to
> Virtex-II. The main obstacle then was the new size Block RAM going from
> 4kbit to 18 kbit apiece. If we left our Unisim and CoreLib components
> untouched we wasted 3/4 of the RAM, but if the number of Block RAMs in
> the chip was sufficient, all we had to do was to update the
> LOC-constraints for pins and DCM's in the .ucf-file. ISE even managed
> to re-target the Virtex-E DLLs to Virtex-II DCMs. Brilliant!

FOr the most part, a VirtexII design can be pretty much dropped into a 
virtex 4.  You hit on one of the places you will have trouble: the slice 
M/slice L thing.  The V4 CLB structure is substantially similar to the 
V2 structure except only even columns have the logic for LUT ram.  Thus 
if you have an RPM with SRL16's or RAM16's placed in it, those have to 
go in even columns.  There is also a bug in the mapper that causes 
problems if an RPM macro with memory elements straddles a BRAM or DSP 
column such it thinks that that any memory elements to the right of the 
DSP/BRAM column are in the wrong type of column even if they aren't. 
The work-around is to break the RPM up into smaller sub-RPMs that fit 
between the BRAM/DSP columns.

The other place you will have difficulty is if you have instantiated 
MULT18x18 primitives in the design, as these have to be converted to 
DSP48's.  With only one register like the Mult18x18s, you will be 
disappointed with the performance, but it will work with a 1:1 replacement.

OK, so paying attention to these two issues will get your design into a 
Virtex4, but you won't reap the full benefit.  You'll find the fabric 
carry chains are not any faster than the same speed grade (and in some 
cases are actually slower) V2.  Also, the clock to output times on the 
BRAM without an added output register and unpipelined multiplier are not 
any faster.  To get the performance promised, you need to turn on the 
pipelining in these elements so that the multiplier has a 3 clock 
pipeline (input, middle and output registers) and the BRAM a 2 clock 
pipeline (there is an added output register).

The big gains in V4 for signal processing type stuff are had with the 
DSP 48 slice's adder, which is quite a bit faster than the fabric carry 
chains.  Unfortunately, using it is basically a clean sheet redesign 
because you also need to use the pipeline registers there to get the speed.

So in short, you can put your V2 design into V4 without a lot of effort, 
but you will likely be disappointed when it doesn't run any faster.  In 
order to get the speed advantages, you need to redesign to the architecture.

Article: 93984
Subject: DCM spartan 3 variable frequency divider
From: "Monica" <monica_dsz@yahoo.com>
Date: 4 Jan 2006 06:07:47 -0800
Links: << >>  << T >>  << A >>
Hello all,

I am monica from germany.I am using xilinx spartan 3 FPGA.I have a
peculiar problem with DCM in spartan 3 FPGA.

The input frequency to the FPGA is from another system which gives a
frequency arround 40 MHz and the FPGA is supposed to generate 1/8 th of
the input frequency,I have implemented it by using DCM.dcmLocked is
asserted(dcm locked) and it works fine.

On certain conditions the input frequency changes from 40 MHz to
60MHz,now dcmLocked is still  asserted(shows that dcm locked) but the
output divided clock's duty cycle is not 50% it is varying spuriously
which is really annoying.

i think DCM still thinks that it is having 40MHz input signal and tries
to lock to it,but it is giving dcmLocked as '1' which is wrong.Either
it should give dcmLocked as '0' or give the correct clock output,but it
is giving wrong clock output as well as wrong dcmLocked signal.

Can anybody give me an idea how to solve this frequency division
problem?

 I will be obliged if anyone can give me a hint/pointers to solve this
problem.

Thank you very much
Monica Dsouza,
Germany


Article: 93985
Subject: Re: DCM spartan 3 variable frequency divider
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Wed, 4 Jan 2006 14:16:49 -0000
Links: << >>  << T >>  << A >>
Monica

The "locked" signal is notoriously unreliable and basically shouldn't be 
used. The status lines are better. Generally if your frequency changes like 
that I would recommend applying a reset to the DCM if possible.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan3 Development 
Board.
http://www.enterpoint.co.uk

"Monica" <monica_dsz@yahoo.com> wrote in message 
news:1136383667.647681.243150@o13g2000cwo.googlegroups.com...
> Hello all,
>
> I am monica from germany.I am using xilinx spartan 3 FPGA.I have a
> peculiar problem with DCM in spartan 3 FPGA.
>
> The input frequency to the FPGA is from another system which gives a
> frequency arround 40 MHz and the FPGA is supposed to generate 1/8 th of
> the input frequency,I have implemented it by using DCM.dcmLocked is
> asserted(dcm locked) and it works fine.
>
> On certain conditions the input frequency changes from 40 MHz to
> 60MHz,now dcmLocked is still  asserted(shows that dcm locked) but the
> output divided clock's duty cycle is not 50% it is varying spuriously
> which is really annoying.
>
> i think DCM still thinks that it is having 40MHz input signal and tries
> to lock to it,but it is giving dcmLocked as '1' which is wrong.Either
> it should give dcmLocked as '0' or give the correct clock output,but it
> is giving wrong clock output as well as wrong dcmLocked signal.
>
> Can anybody give me an idea how to solve this frequency division
> problem?
>
> I will be obliged if anyone can give me a hint/pointers to solve this
> problem.
>
> Thank you very much
> Monica Dsouza,
> Germany
> 



Article: 93986
Subject: Re: Xilinx upgrade issues
From: "Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com>
Date: 4 Jan 2006 06:19:40 -0800
Links: << >>  << T >>  << A >>
Hi John,

I'll try to be explicit.

> But the same letter says that WebPack 8.1i is free with "no loss of
> device support or design tools."
>
> Q: Is that true?

Yes.

Basically there was 3 version :
 - WebPack
 - BaseX
 - Foundation

Foundation has all features and devices supported. BaseX a little less
than foundation and Webpack a little less than BaseX. Now (since 8.1),
every features/devices that was in BaseX is in the WebPack so if the
BaseX 7.1 was good enough for you,

> Q: is WebPack something we can download and keep, or is it some sort
> of java thing that Xilinx can change or kill at any time? Longterm
> ability to maintain designs is crucial to us.

The WebPack is a real application and can run/install disconnected.
(It's in fact the same application as the complete one but with some
files missing afaics).

Just be sure to download the "Full package" (ofter around 300-400 Mb)
and not just the "Installer" (around 15 Mb). The latter one will
download and install the webpack for you but doesn't contain everything
and must connect to Xilinx at install time.


>
> Q: why would anybody pay $2500 a year if the free version is the same?

The new WebPack 8.1 supports every features that was supported in BaseX
7.1.
But it doesn't have all the feature/devices of the Foundation series
(7.1 or 8.1). So instead of
three levels of feature set, now there is just 2 ...



Sylvain


Article: 93987
Subject: Re: Start up condition of flip flops in FPGA?
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 4 Jan 2006 14:33:18 -0000
Links: << >>  << T >>  << A >>
"Ray Andraka" <ray@andraka.com> wrote in message 
news:xBxuf.37716$Mi5.13602@dukeread07...
> Thomas Rudloff wrote:
>
>> The best is to have an asynchronous reset that is released synchronous.
>> This works even if the clock is not running. Eg with a broken crystal.
>> There are app notes how to do this. Basicly it is a shift register
>> stage resetted asynchronously with an inactive signal at the data input.
>> After release of reset the inactive reset will clock towards the output.
>> With this you can even build up a tree for large FPGAs to prevent
>> slowing down clock rate because of large routes.
>
> Actually, with Xilinx FPGA's you are better off using a strictly 
> synchronous reset, and only on the flip-flops that need it.
>
> If you need the behavior of an async reset, meaning the pins all go to a 
> safe state, pull the program pin low.  That immediately puts the FPGA into 
> the programming state, which will look like it has been reset.
Agreed. I'd also comment that it's worth considering adding a global 
asynchronous reset to your design which you only use for simulation, i.e. 
tied inactive in the real hardware. Makes life in ModelSIM-land easier as 
ModelSIM doesn't necessarily 'know' that you're targetting an FPGA that 
sets/resets the FFs on configuration.
Cheers, Syms. 



Article: 93988
Subject: Re: Xilinx upgrade issues
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Wed, 04 Jan 2006 06:52:49 -0800
Links: << >>  << T >>  << A >>
On 4 Jan 2006 06:19:40 -0800, "Sylvain Munaut
<SomeOne@SomeDomain.com>" <246tnt@gmail.com> wrote:

>Hi John,
>
>I'll try to be explicit.
>
>> But the same letter says that WebPack 8.1i is free with "no loss of
>> device support or design tools."
>>
>> Q: Is that true?
>
>Yes.
>
>Basically there was 3 version :
> - WebPack
> - BaseX
> - Foundation
>
>Foundation has all features and devices supported. BaseX a little less
>than foundation and Webpack a little less than BaseX. Now (since 8.1),
>every features/devices that was in BaseX is in the WebPack so if the
>BaseX 7.1 was good enough for you,
>
>> Q: is WebPack something we can download and keep, or is it some sort
>> of java thing that Xilinx can change or kill at any time? Longterm
>> ability to maintain designs is crucial to us.
>
>The WebPack is a real application and can run/install disconnected.
>(It's in fact the same application as the complete one but with some
>files missing afaics).
>
>Just be sure to download the "Full package" (ofter around 300-400 Mb)
>and not just the "Installer" (around 15 Mb). The latter one will
>download and install the webpack for you but doesn't contain everything
>and must connect to Xilinx at install time.
>
>
>>
>> Q: why would anybody pay $2500 a year if the free version is the same?
>
>The new WebPack 8.1 supports every features that was supported in BaseX
>7.1.
>But it doesn't have all the feature/devices of the Foundation series
>(7.1 or 8.1). So instead of
>three levels of feature set, now there is just 2 ...
>
>
>
>Sylvain


Thanks!

Sounds like we should transition from BaseX to WebPack and save the
money for the bonus fund.

John


Article: 93989
Subject: Re: DCM spartan 3 variable frequency divider
From: "Monica" <monica_dsz@yahoo.com>
Date: 4 Jan 2006 07:03:32 -0800
Links: << >>  << T >>  << A >>
Hallo,

Thank you very much for the suggestion.

If I understand the datasheet of the DCM correctly,status bits indicate
the following things.

status[0] indicate if phase shifter has reached its maximum value
status[1] indicate if CLKIN is present or not
status[2] indicate CLKFX and CLKFX180 are present or not
 and remaining status bits are reserved(invalid).

How can we determine whether DCM has locked or not using these status
lines?Did I interpret the data sheet incorrectly?

yes I will reset the DCM if it can show that it is not locked.The
problem is it is showing that it has locked but giving incorrect
clock.if it can give an indication that it cannot lock or lock is
lost,then I can reset the DCM.

Unfortunately system which changes the frequency cannot reset or give
an indication to the FPGA.if we have to do it then we must redesign our
hardware to give an addtional line from that system to the FPGA.We will
do it only if nothing else can be done to solve the problem(because it
costs heavily).

Kindly let me know how can i deal with this problem.

Thank you very much,
Monica


Article: 93990
Subject: Re: FPGA DVI output with CH7301
From: "RobJ" <rsefton@abc.net>
Date: Wed, 04 Jan 2006 15:29:26 GMT
Links: << >>  << T >>  << A >>
"Antti Lukats" <antti@openchip.org> wrote in message 
news:dpe5qu$gmj$00$1@news.t-online.com...
>
> Hi Andre,
>
> that was it! I should really to the RTFM thing more often, I had looked at 
> those regs
> but they had 'use default' value for them so I assumed they have some good 
> default
> at powerup but they dont - thats actually written in the datasheet as well
>
> so after writing the proper defaults the DVI TFT monitor did come alive, 
> no issues!
>
> Thank you!
>
> Antti
>

Antti -

I'm starting a design where we'll be using DVI to distribute display data 
within an embedded system and I'd like to be able to also drive a monitor 
for demos and debug. Did you need to communicate with the monitor via 
SMBus/I2C or did it come up in VGA mode by default?

Thanks,
Rob 



Article: 93991
Subject: Re: DCM spartan 3 variable frequency divider
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Wed, 4 Jan 2006 15:33:51 -0000
Links: << >>  << T >>  << A >>
Monica

The status lines may not be enough. Depending on what happens when you clock 
changes but you may get the "not present" showing long enough that you can 
register the event.

Other ways to detect clocks running fast or slow but usually you need some 
kind of reference clock to compare or run logic from. With the large step 
frequency you have it would be easy to detect. Either way you will need more 
than the DCM alone to get an indicator. I don't think Xilinx every envisaged 
coping with a dynamic clock input as you describe. DCMs tend to like nice 
stable clocks.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk


"Monica" <monica_dsz@yahoo.com> wrote in message 
news:1136387011.980099.285940@f14g2000cwb.googlegroups.com...
> Hallo,
>
> Thank you very much for the suggestion.
>
> If I understand the datasheet of the DCM correctly,status bits indicate
> the following things.
>
> status[0] indicate if phase shifter has reached its maximum value
> status[1] indicate if CLKIN is present or not
> status[2] indicate CLKFX and CLKFX180 are present or not
> and remaining status bits are reserved(invalid).
>
> How can we determine whether DCM has locked or not using these status
> lines?Did I interpret the data sheet incorrectly?
>
> yes I will reset the DCM if it can show that it is not locked.The
> problem is it is showing that it has locked but giving incorrect
> clock.if it can give an indication that it cannot lock or lock is
> lost,then I can reset the DCM.
>
> Unfortunately system which changes the frequency cannot reset or give
> an indication to the FPGA.if we have to do it then we must redesign our
> hardware to give an addtional line from that system to the FPGA.We will
> do it only if nothing else can be done to solve the problem(because it
> costs heavily).
>
> Kindly let me know how can i deal with this problem.
>
> Thank you very much,
> Monica
> 



Article: 93992
Subject: Re: FPGA DVI output with CH7301
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 4 Jan 2006 16:35:40 +0100
Links: << >>  << T >>  << A >>
"RobJ" <rsefton@abc.net> schrieb im Newsbeitrag 
news:qRRuf.9548$ka.1573@tornado.socal.rr.com...
> "Antti Lukats" <antti@openchip.org> wrote in message 
> news:dpe5qu$gmj$00$1@news.t-online.com...
>>
>> Hi Andre,
>>
>> that was it! I should really to the RTFM thing more often, I had looked 
>> at those regs
>> but they had 'use default' value for them so I assumed they have some 
>> good default
>> at powerup but they dont - thats actually written in the datasheet as 
>> well
>>
>> so after writing the proper defaults the DVI TFT monitor did come alive, 
>> no issues!
>>
>> Thank you!
>>
>> Antti
>>
>
> Antti -
>
> I'm starting a design where we'll be using DVI to distribute display data 
> within an embedded system and I'd like to be able to also drive a monitor 
> for demos and debug. Did you need to communicate with the monitor via 
> SMBus/I2C or did it come up in VGA mode by default?
>
> Thanks,
> Rob

there is no need to talk to the monitor at all, its only informative to 
query the capabilities, monitor does not care if that info is accessed or 
not.

CH7301 however needs I2C initialization in order to be operational, this 
both for Analog bypass and for DVI modes, with cold start defaults there is 
no useable output from the CH7301, I assume its the same thing with the 
other DVI transmitters

we use an small PicoBlaze design to feed the CH7301 with register 
initialization sequence

if you are interested we have PCB boards ready for DVI tests, the PCB can be 
fitted for you with just the DVI part that is the board would hold

1 DVI connector
2 CH7301
3 power input jack
4 power supply ics
5 Cable IV header
6 Virtex 4LX15 (or LX25 or FX12)
7 Clock oscillator

the board has some other components as well that can be fitted, unfortunatly 
I dont have full specs or pictures ready, please email me if interested

Antti

















Article: 93993
Subject: Re: Why 'a plurality of N' must be used for 'N' in patent claims
From: Dirk Bruere at Neopax <dirk.bruere@gmail.com>
Date: Wed, 04 Jan 2006 15:53:05 +0000
Links: << >>  << T >>  << A >>
Robert Baer wrote:

> Eric Smith wrote:
> 
>> wtxwtx@gmail.com writes:
>>
>>> Why 'a plurality of N' or 'the plurality of N' must be used fo 'N' in
>>> patent claims?
>>
>>
>>
>> Because patents are written to be legal documents, not engineering
>> documents.  Legal documents are written using traditions that have
>> evolved over hundreds of years.  Since patent examiners, lawyers, and
>> judges all expect patents to be written in a certain way, if you
>> submit an application that isn't written that way, you're just wasting
>> money.
> 
>   Again, that is what i call "patent-ese".
>   Instead of "many" or "multiple" one sees "a plurality of".
>   Like i said, follow the terminology and useage that you find in other 
> patents that are closely related to your particular idea.

Legalese is a very precise language, quite comparable to computer languages.
If you ever see "...time is of the essence..." in a contract, prepare to run.

-- 
Dirk

The Consensus:-
The political party for the new millenium
http://www.theconsensus.org

Article: 93994
Subject: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
From: Rene Tschaggelar <none@none.net>
Date: Wed, 04 Jan 2006 17:10:53 +0100
Links: << >>  << T >>  << A >>
Jan Panteltje wrote:

> Is there any reason I should be interested in a segmented processor?

Yes, there are many tools available for it. Even the DOS
versions beat many current embedded development environments.
Why should I shell out 6k$ for some embedded C compiler
when I can use turbopascal ?

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 93995
Subject: Re: DCM spartan 3 variable frequency divider
From: "Monica" <monica_dsz@yahoo.com>
Date: 4 Jan 2006 08:11:38 -0800
Links: << >>  << T >>  << A >>
Dear John Adair,

Thank you very much for the reply.I need an addtional lines to the FPGA
to indicate this frequency change.Time to fight with PCB engineer to
provide one additional line.

Thanks a lot,
Monica


Article: 93996
Subject: Re: DCM spartan 3 variable frequency divider
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 04 Jan 2006 08:12:31 -0800
Links: << >>  << T >>  << A >>
Monica,

Not sure you can deal with this problem.

If you have 8 MHz output, be sure you are not going below the min output 
frequency specification.  It would be safer to use CLKDV, and divide 
down to 8 MHz from a hiugher frequency (like a divide by 5 from 40 MHz).

Then, I would use two DCM's.

One DCM is used to monitor the quality, and is periodically reset so 
that it can be used as a monitor (checking that it is always able to 
re-lock properly).

The other DCM is used to provide the output.  If the monitor DCM 
indicates after a reset that its status is better (ie it is locked and 
OK), then that would tell you that it would would be useful to reset the 
DCM providing the output.

One can also have a difference detector from the output of the two DCMs. 
  If the reset and test DCM output is different from the operating DCM; 
that is also an indication that the input has drifted too far, and the 
operating DCM is lost.

Just a couple thoughts,

Austin

Monica wrote:

> Hallo,
> 
> Thank you very much for the suggestion.
> 
> If I understand the datasheet of the DCM correctly,status bits indicate
> the following things.
> 
> status[0] indicate if phase shifter has reached its maximum value
> status[1] indicate if CLKIN is present or not
> status[2] indicate CLKFX and CLKFX180 are present or not
>  and remaining status bits are reserved(invalid).
> 
> How can we determine whether DCM has locked or not using these status
> lines?Did I interpret the data sheet incorrectly?
> 
> yes I will reset the DCM if it can show that it is not locked.The
> problem is it is showing that it has locked but giving incorrect
> clock.if it can give an indication that it cannot lock or lock is
> lost,then I can reset the DCM.
> 
> Unfortunately system which changes the frequency cannot reset or give
> an indication to the FPGA.if we have to do it then we must redesign our
> hardware to give an addtional line from that system to the FPGA.We will
> do it only if nothing else can be done to solve the problem(because it
> costs heavily).
> 
> Kindly let me know how can i deal with this problem.
> 
> Thank you very much,
> Monica
> 

Article: 93997
Subject: Re: DCM spartan 3 variable frequency divider
From: "Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com>
Date: 4 Jan 2006 08:16:11 -0800
Links: << >>  << T >>  << A >>
If you have

clk_in -> DCM -> clk_out

with clk_out being 1/8th of the frequency of clk_in, you can add a
small logic block clocked from clk_in that samples clk_out 8 times,
then count the number of 1 to find out the duty cycle (or 16/24/32
times, juste to be sure) and if the duty changes too much, then that
means the DCM needs to be reset.


Article: 93998
Subject: Re: Using posedge and negedge causing me grief
From: "Andy" <jonesandy@comcast.net>
Date: 4 Jan 2006 08:39:34 -0800
Links: << >>  << T >>  << A >>
crurval is reset in the posedge block, and assigned in the negedge
block. Move the reset to the negedge block, and it should work.

Andy


Article: 93999
Subject: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Wed, 04 Jan 2006 16:44:01 GMT
Links: << >>  << T >>  << A >>
On a sunny day (Wed, 04 Jan 2006 17:10:53 +0100) it happened Rene Tschaggelar
<none@none.net> wrote in <43bbf404$0$1159$5402220f@news.sunrise.ch>:

>Jan Panteltje wrote:
>
>> Is there any reason I should be interested in a segmented processor?
>
>Yes, there are many tools available for it. Even the DOS
>versions beat many current embedded development environments.
>Why should I shell out 6k$ for some embedded C compiler
>when I can use turbopascal ?
>
>Rene
I though, just before dinner I will read c.a.f as i will not have to give
one of those very complicated replies.. (just did in some other group), and
have the pizza in peace ;-)
Sure, you want to use turbo Pascal on a x86 in FPGA sure.
I never continue to be amazed at what people do.
I followed one of the links Antti gave, and ended up with Linux on an ipod...
Looked up what processor that was... never heard of it :-)
And I can imagine if somebody made a Linux based board with an AMD 64 HDL.
But Pascal, just for the record, I thought it was dead? (as ADA ;-)?
As for the 6K .. gcc outputs for many processors.....
'embedded C compiler? never seen one that was good... Write asm or use a
normal C compiler with asm includes.
Maybe I am old fashioned, but I never use debugger either in C, just print
statements.
Even more so I do not use ICE or debugger in asm in embedded, just a scope
and assembler.
This comes from learning to write in machine code (00101010) programming in
EPROM and if it did not work erase for 20 minutes or so and try again... 
It is as simple as editing text files with cat and cut.
Hope you see the humor of this.
Pizza is waiting


 






Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search