Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Antti Lukats wrote: > well you really sound paranoid about the issue. If you do some tools that > produce XDL and help xilinx to sell their silicon they will not go hunting > you down. In how many different ways I have to say that? Or we could set the stage for another open source witch hunt, with Xilinx lawyers going after all the competitors and users asking for license payments like SCO. The whole SCO wake up call is that we deal with IP rights properly, up front, or stay clear -- and don't expect everyone to be greatful when you steal IP from some big company.Article: 95826
Alex Gibson wrote: > "Larry Doolittle" <ldoolitt@localhost.localdomain> wrote in message > news:slrndtfapv.u3t.ldoolitt@localhost.localdomain... > >>On 2006-01-25, Eli Hughes <emh203@psu.edu> wrote: >> >>>Dave Feustel wrote: >>> >>>>Are there any open source programs for programming fpgas? >>> >>>Don't waste your time. Vendor's spend a *VERY* long time working out >>>bugs in their software. >> >>"There are two ways of constructing a software design. One way is >>to make it so simple that there are obviously no deficiencies >>and the other is to make it so complicated that there are no >>obvious deficiencies." >> - C A R Hoare >> >> >>>With the level of complexity of an FPGA, you >>>don't want to waste time with buggy software that is developed in >>>someone else's spare time. All of the actually chip programming, >>>routing stuff is vendor locked(for good reason), so your out of luck on >>>that. >> >>In other words, "shut up and get back on the couch". >> >> >>>That being said, Xilinx does offer their software for Linux. It is not >>>opensource but it does give you a non-windows alternative. >> >>"I won't run software written by cowards." >> - Adam Stiles, referring to software provided without source code >> >> - Larry > > > You obviously don't develop using any fpga or most dsps then ? > > I guess its a difference between embedded hardware and 'software' developers. I have spent most of my time developing embedded hardware where assembly/C/Verilog rules. I remember when we hired a 'software' (also insert *nix advocate, open source advocate, corporations are evil, etc) to help out with a project. We had a working product when things started. Tight embedded code, streamlined hardware, etc. Week 1: Software Guy:" OK guys, I see you wrote your DSP code in Assembler and C. Lets re-write algorithms. What do you mean you statically allocated your 128K of memory? Let's dynamically allocate. By the way, I only run Linux on my PC" Week 2: (Things are broke, still trying to get Linux Desktop to work on our network) Software Guy: "I can't code on this system. Where is your O.S. to handle threads? What is an interrupt routine? What, no OS memory management. Lets Load Linux. After all, its open source and free. We can modify it to fill our needs. Its free." Week 3: (Things are really Broke, still trying to get Linux Desktop to work on our network) Software Guy: "What, gcc doesn't compile on a TI C6000? I need an OS. What? TI doesn't open source its compiler for the VLIW architecture. What , people want money for there hard work? Lets re-write all the development with GPL compatible stuff. All development tools should be open source. After all its free. Many weeks later : (Things are FUBARed, still trying to get Linux Desktop to work on our network) Software Guy: "My super-uper-duper modified lLinux version is too slow. I need a Quad Power PC system with 2GB of ram that uses 100watts of power to replace you single chip solution that is 2 Watts. But is has a open-source O.S. and is GPL compatable. Its FREE. Software Guy gets shit-canned. Hardware guys never ask for software help again. We will hire more hardware guys. We could have bought 30 'proprietary development kits' for the cost of the 'free' stuff. And it would be documented better! Moral of the story: There are people that have to ship product in very little time. Things have to work. We don't have time to re-write code because we refuse to use something that doesn't have the source released. There are some good open source projects out there but they took a long while to get documented and running good. Sure I use thunderbird mail. Its a cool opensource app. I use open source where its good. But I also have serious time lines and goals to meet. At some point one needs to rely on chip makers. -EliArticle: 95827
Ron, OK. Austin Ron Huizen wrote: > Austin, > > Sorry if I didn't make it clear - the board already exists and provides a > 2.5V supply to the XO, so while LVDS is LVDS, it does matter to us what the > supply voltage is. We could hack up the board to change the supply voltage, > but would rather not. That's why we want a drop in replacement for the > Epson. > > The first issue is finding one with extended temperature (we can do that) > but the problem we have is figuring out in advance if the XO performance > will be good enough for the V2Pro's MGTs. Do you have any performance > requirement specs for the XO used for the MGTs that we could use in this > search? > > My reason for coming to the group was to find a part others have used with > success > > --- > Ron > > > "Austin Lesea" <austin@xilinx.com> wrote in message > news:dr8j0r$igb6@xco-news.xilinx.com... > >>Ron, >> >>Look for an LVDS output oscillator. >> >>Then the matter of supply voltage does not matter. >> >>LVDS is LVDS: does not matter if it runs off of 2.5V, or 3.3V. >> >>Austin >> >>Ron Huizen wrote: >> >> >>>Does anyone have experience using any oscillators for the MGTs on the >>>V2Pro other than the two listed in Xilinx's app note (Epson and >>>Pletronics)? >>> >>>We've always used the Epson part (100, 125, or 156.25 MHz) in the past >>>but now need an extended temp version which they don't have, and >>>unfortunately the Pletronics part, which does have an extended temp >>>version, has a 3.3V supply instead of the 2.5 supply like the Epson. >>> >>>Ideally, we want a drop in for the Epson, which is a 6 pin 5x7 package, >>>pin 1 enable, 2.5V supply. Issues or concern are termination and jitter. >>> >>>------------ >>>Ron Huizen >>>BittWare > > >Article: 95828
Eli Hughes wrote: > Software Guy gets shit-canned. Hardware guys never ask for software > help again. We will hire more hardware guys. We could have bought 30 > 'proprietary development kits' for the cost of the 'free' stuff. And it > would be documented better! starting the hardware software bigot wars just isn't useful, or productive, it's actually outright trolling. > Moral of the story: There are people that have to ship product in very > little time. Things have to work. We don't have time to re-write code > because we refuse to use something that doesn't have the source > released. There are some good open source projects out there but they > took a long while to get documented and running good. Sure I use > thunderbird mail. Its a cool opensource app. I use open source where > its good. But I also have serious time lines and goals to meet. At some > point one needs to rely on chip makers. There is a simlar point about hardware guys being frozen in paralysis because the project is too undefined to specify ... and the software guys jump in over their heads and steadily work toward a solution while the hardware guys are still paniced that the design isn't yet complete and signed off. The real moral of the story is that we are all people, and we do the best we can with the experience and tools at hand. JohnArticle: 95829
"hutzelbutz" <joachim.becker@imtek.uni-freiburg.de> writes:
>I don't know enough about multi-processor load distribution in Linux,
>but this behavior is reproducable. Could it be that those 4 minutes
>come from the time, the OS needs to find out that one process should be
>switched to the other CPU???
No, at least process migration should not matter. Maybe they have a race
condition which doesn't appear in the sequential single-CPU case.
>I would be curious to hear the experts about this topic!
Simply do a "strace -p <pid>" and you will see what is going on at the
syscall-level. Most of the time it is also possible to start the program directly
with "strace -f <program>", but it can have problems with catching forked threads.
BTW: Haven't yet used 8.1 myself, but I suspect an issue either with thread
handling (mutexes, etc.) or some name resolution (for whatever cause they need
it).
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 95830On a sunny day (25 Jan 2006 08:45:51 -0800) it happened Larry Doolittle <ldoolitt@localhost.localdomain> wrote in <slrndtfapv.u3t.ldoolitt@localhost.localdomain>: >> That being said, Xilinx does offer their software for Linux. It is not >> opensource but it does give you a non-windows alternative. > >"I won't run software written by cowards." > - Adam Stiles, referring to software provided without source code > Guys, take a step back. I am all for open source, released many programs under GPL for Linux. But NEVER in the last 12 years? or so have a 'demanded' somebody else to release source. I ran Netscape on Linux when there still was no source. There are plenty cases where a company will not release source (run Eagle on Linux?) just so these companies can stay in business. I did have a quick look at those jbits(or what was it called), and it was 'sponsored' by X. So that gives them every right to stop sponsoring it.... I am sure there are some reasons. However I do not think anybody can stop anyone from writing open source applications for their FPGAs unless it reveals some crucial details. Today I have read that even MS will now license source of their servers to comply with EU an US law to allow competition. Must be really hard for them. I know managers who NEVER would do that. So plz do not make some religion out of open source, it is not. Linus today wrote he will not accept GPL3 for the kernel (GPL3 has DRM restrictions). 2~Let us all be reasonable please.Article: 95831
Anand schrieb: > I am writing veerilog code for DDR2 SDRAM controller using the micron > memory module and I want to implement it on Virtex-4 FPGA.......but I > am a new comer to verilog and due to time constraints I am afraid that > i won't be able to write the complete code(complete all > modules)......so can any one provide me a synthesizable code......the > one i cud get from the xilinx web site( reference design) is not > synthesizable.....plz help > Hi, concerning DDR2 you will not be able to just download a bunch of Vlog / VHDL press the button and your done. In DDR2 the IO-Level, the way you interconnect the DDR2 device and the IO-Logic of your DDR2 controller heavily depend on the ASIC / FPGA infrastructure you have. So for example for Virtex-IV on the IO-Level it will not be same 'behavioral' code as it is for Altera Cyclone / Stratix-II devices. - Data Capturing, Clocking etc. depend on the FPGA you use. By the way, what did you download and what is not synthesizable. The more info we got, the better we may be able to help ... Cheers Markus P.S. DDR2 and FPGA is NOT an easy task... ----== Posted via Newsfeeds.Com - Unlimited-Unrestricted-Secure Usenet News==---- http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups ----= East and West-Coast Server Farms - Total Privacy via Encryption =----Article: 95832
On Thu, 26 Jan 2006 10:04:40 -0000, "Symon" <symon_brewer@hotmail.com> wrote: >"Jim Granville" <no.spam@designtools.co.nz> wrote in message >news:43d897a9$1@clear.net.nz... >> Kevin Morris wrote: >>> I'm finishing up an FPGA Journal article called "Stop. Go. Yield. - >>> Dude! Where's my Chip?" >> >> Hmm.. Not a title that travels internationally very well... >> -jg >> >Hi Jim, >Not sure it even travels out of CA! But I like it. I can see Jeff Bridges >out of "The Big Lebowski" waiting for FPGAs. >Maude Lebowski: What do you do for recreation? >The Dude: Oh, the usual. I bowl. Drive around. Wait for V4 MGTs. The >occasional acid flashback. Or maybe John Goodman? Walter: I can get you a V4 by 3 o'clock this afternoon... with MGTs. Bob Perlman Cambrian Design WorksArticle: 95833
Jan Panteltje wrote: > Guys, take a step back. > I am all for open source, released many programs under GPL for Linux. > But NEVER in the last 12 years? or so have a 'demanded' somebody else > to release source. We are not asking that Xilinx release Xilinx source, just that they relax their very tight NDA on EVERYTHING that is ISE related. > I did have a quick look at those jbits(or what was it called), and it was > 'sponsored' by X. > So that gives them every right to stop sponsoring it.... > I am sure there are some reasons. This is the issue ... sponsered by is NOT the same as completely fair market paid for. I doubt that when Xilinx finally decided to block this project that they fairly compensated the entire team for their total labor hours and materials for the project that were forced to be forfieted behind the enforced NDA. I doubt the outcome here is that Xilinx "bought" the project and decided to bury it ... prove me wrong please. > However I do not think anybody can stop anyone from writing open source > applications for their FPGAs unless it reveals some crucial details. Crucial is everything ... file formats, library interfaces, usage procedures, etc EVERYTHING that is a derivative of the documentation, and use, of the product. > So plz do not make some religion out of open source, it is not. > Linus today wrote he will not accept GPL3 for the kernel (GPL3 has DRM > restrictions). It's not about religion, it's about playing fair with the open source teams. The JHDLBits SF project was registered I believe April 17, 2004, they gave public talks on open source for Xilinx for at least two major conferences in June and Sept, and a few months later got stopped dead in their tracks. Playing fair with open source is not taking all that yields wind fall profits by avoiding competitive licensing, then shutting down open source teams on NDA violations which may actually be far more minor that they appear, and having EVERY software interface to their product under NDA. The only public interfaces are an obsolete XNF specfication (and I'm not entirely sure that's public) and a vague EDIF interface with non-documented interfaces that you need to extract from ISE NDA restricted documentation. So me where there is ANY legal interface which allows you to program the full Xilinx offering of FPGA's from XC4K's (which are great hobby devices) to current XC4V products without geting encumbered in ISE license restrictions prohibiting open source software development and disclosure of interfaces? I don't see a legal one ... so show me ... > 2~Let us all be reasonable please. yep ... let's find a reasonable solution so we can write open source software to develop net lists for ISE tools without getting tied up in the ISE NDA restrictions.Article: 95834
So the question to Xilinx is, will Xilinx release the NDA restrictions on XDL, and the associated library interfaces so that open source tools can legally target ISE supported FPGAs? It's pretty clear that most of the regulars here, just assume that XDL and the associated libraries, are an open interface, and think it's ok to ignore the IP restrictions in the ISE license. The legaleze says otherwise. So how about a clear definative legal statement about what are legal ISE interfaces for open source development.Article: 95835
fpga_toys@yahoo.com wrote: > Eli Hughes wrote: > > Moral of the story: There are people that have to ship product in very > > little time. Things have to work. We don't have time to re-write code > > because we refuse to use something that doesn't have the source > > released. There are some good open source projects out there but they > > took a long while to get documented and running good. Sure I use > > thunderbird mail. Its a cool opensource app. I use open source where > > its good. But I also have serious time lines and goals to meet. At some > > point one needs to rely on chip makers. > > There is a simlar point about hardware guys being frozen in paralysis > because the project is too undefined to specify ... and the software > guys > jump in over their heads and steadily work toward a solution while the > hardware guys are still paniced that the design isn't yet complete and > signed off. I think it comes down to this: If your software doesn't work, you tell the customer, "download a patch from our web site." If your hardware doesn't work, you tell the customer, "here's your RMA number. Send the unit back (at your expense) and if it's under warrantee we'll fix it for free; otherwise, it'll cost $$$." As for why hardware guys don't like to just "jump in" when a project is poorly defined: just tell the boss: "Ooops, there was a fsck-up in the product definition so we have to dump that run of 1000 fully-assembled boards." -aArticle: 95836
GEO wrote: > My guess is that, Xilinx is more afraid of their tools being used by > other FPGA vendors. Probably they don't want ISE to support Altera > devices and the like!, if it is opensourced. That may be the biggest > risk for them - not reverse engineering. I had not thought of that - but this is the first truly plausible explanation why the programming data are kept secret I ever see. I could see it was about control, but I could not see the why. This is definitely a possibility. Thanks, Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 95837
dp wrote: > GEO wrote: > > My guess is that, Xilinx is more afraid of their tools being used by > > other FPGA vendors. Probably they don't want ISE to support Altera > > devices and the like!, if it is opensourced. That may be the biggest > > risk for them - not reverse engineering. > > I had not thought of that - but this is the first truly plausible > explanation why the programming data are kept secret I ever > see. I could see it was about control, but I could not see the > why. This is definitely a possibility. So why then block open source place, route, and bit stream gen tools that equally benefit all? That is not about using Xilinx software for Altera parts.Article: 95838
fpga_toys@yahoo.com wrote: > Those that leach off open source, while completely blocking open source > development for their products, need to be called on the carpet for > that, > and probably regularly till they get the hint that open source is a TWO > way > relationship -- they need to give as much IP as they take. I suspect that many of those entities that "leech off of open source" don't really care. See, for example, Microsoft. I realize that Xilinx makes heavy use of Cygwin, tcl and various other open-source technologies. Unfortunately (for those with certain points of view, at least), I don't see that there's any obligation on Xilinx's part (or my part, for that matter) to "give back to the community." It's perfectly all right for you to choose to give away your work, and it's equally all right for me to choose not to do so. It is NOT all right for someone to demand that others give away their work, even if that work was created using free/open-source tools. I am grateful to Stallman for creating emacs, and grateful to the subversion folks for their tools, as I use them every day. That I use these tools to create proprietary designs sold at a profit by my employer is not relevant. You said it yourself, although in a different context: I like my home and I like my house. -aArticle: 95839
Bob Perlman wrote: > On Thu, 26 Jan 2006 10:04:40 -0000, "Symon" <symon_brewer@hotmail.com> > wrote: > > >"Jim Granville" <no.spam@designtools.co.nz> wrote in message > >news:43d897a9$1@clear.net.nz... > >> Kevin Morris wrote: > >>> I'm finishing up an FPGA Journal article called "Stop. Go. Yield. - > >>> Dude! Where's my Chip?" > >> > >> Hmm.. Not a title that travels internationally very well... > >> -jg > >> > >Hi Jim, > >Not sure it even travels out of CA! But I like it. I can see Jeff Bridges > >out of "The Big Lebowski" waiting for FPGAs. > >Maude Lebowski: What do you do for recreation? > >The Dude: Oh, the usual. I bowl. Drive around. Wait for V4 MGTs. The > >occasional acid flashback. > > Or maybe John Goodman? > > Walter: I can get you a V4 by 3 o'clock this afternoon... with MGTs. > > Bob Perlman > Cambrian Design Works This thread does not abide. -aArticle: 95840
Andy Peters wrote: > It's perfectly all right for you to choose to give away your work, and > it's equally all right for me to choose not to do so. It is NOT all > right for someone to demand that others give away their work, even if > that work was created using free/open-source tools. and it's not alright for Xilinx to let an open source project proceed for many months, and then shut it down without fair compensation. I suspect Xilinx was fully aware of the projects open source nature, since the SF project which was created on 4/17/04 and the talks in June and Sept where all clear about being open source. > I am grateful to Stallman for creating emacs, and grateful to the > subversion folks for their tools, as I use them every day. That I use > these tools to create proprietary designs sold at a profit by my > employer is not relevant. You said it yourself, although in a > different context: I like my home and I like my house. The WHOLE reason behind FSF and GPL is EXACTLY the highly restrictive ISE licenses. I almost couldn't stop rolling on the floor when Xilinx was puffing behind their donations to FSF. It would make a great poster, giant Xilinx paying FSF so it's ok to NDA lock their entire poduct line ... some how I would guess that Richard wouldn't think that is politcally correct to hide behind the FSF that way. Should probably ask some day.Article: 95841
All, It is unfair to the university(ies) or school(s) involved, and also unfair to the company(ies) involved to continue with these allegations. You may be harming the student(s), professor(s) and potentially the company(ies) involved. We sponsor research, and we have many interns. We contribute to many schools and universities a substantial amount of products and software. We do not sponsor research that gives away our intellectual property. We expect our licenses, IP, and rights to be respected. Thank you, AustinArticle: 95842
fpga_toys@yahoo.com wrote: > dp wrote: > > GEO wrote: > > > My guess is that, Xilinx is more afraid of their tools being used by > > > other FPGA vendors. Probably they don't want ISE to support Altera > > > devices and the like!, if it is opensourced. That may be the biggest > > > risk for them - not reverse engineering. > > > > I had not thought of that - but this is the first truly plausible > > explanation why the programming data are kept secret I ever > > see. I could see it was about control, but I could not see the > > why. This is definitely a possibility. > > So why then block open source place, route, and bit stream gen tools > that equally benefit all? That is not about using Xilinx software for > Altera parts. I have only written tools for CPLDs, so there may be FPGA-only related details which I miss, but it appears that they are blocking as much as possible to not make reverse engineering too easy (it is always possible, the question is whether it will seem easy enough for someone to do it). And then again, the reasons may be totally different. The world is by far not the purely market driven place we are deafened about by the screaming media every day. Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 95843
Not to far away is our own PCI core that will be available free in a lite form for owners of Raggedstone1. Commercial use beyond that will require a reasonably costed license and a fairly low entry point. The Raggedstone website has just been updated with a link to Manuel's link and some stop-gap photos and pricing of modules is now there too until the new website goes live. John Adair Enterpoint Ltd. - We are on stand F48 at DATE. http://www.enterpoint.co.uk "Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:g4iht11i0tk38eijpmbrv0pg4ji1mce463@4ax.com... > On 25 Jan 2006 17:32:26 -0800, "Paul Marciano" <pm940@yahoo.com> wrote: > >> >>John Adair wrote: >>> You might want to have a look at our product Raggedstone1. It has the >>> much >>> larger XC3S400-4FG456C part fitted. Programming cable is included and >>> card >>> can be used in a PCI slot or stand-alone with the optional PCI I/O >>> Header. >>> Details here http://www.enterpoint.co.uk/moelbryn/raggedstone1.html. >> >>As a learner and experimenter I like the look of that board, but how >>much does the Xilinx PCI core for the Spartan 3 cost? > > The Xilinx core ... a lot ($1995 for a single project license) > But keep watch for an announcement from John A. in the near future... > > - BrianArticle: 95844
Manuel Bessler wrote: > A colleague and I have adapted the pci32tlite_oc core from > opencores.org to run on raggedstone1. > I've also written a Linux driver for it. > Both available here: > http://projects.varxec.net/doku.php/raggedstone1 Outstanding!Article: 95845
fpga_toys@yahoo.com wrote: > So the question to Xilinx is, will Xilinx release the NDA restrictions > on XDL, and the associated library interfaces so that open source tools > can legally target ISE supported FPGAs? > > It's pretty clear that most of the regulars here, just assume that XDL > and the associated libraries, are an open interface, and think it's ok > to ignore the IP restrictions in the ISE license. The legaleze says > otherwise. > > So how about a clear definative legal statement about what are legal > ISE interfaces for open source development. > I believe that it is established copyright law that SW interface specs are not protectable elements although there appear to be some gray areas. This seems to be a good write up from 1997 http://www.fenwick.com/docstore/publications/IP/IP_Articles/Baystate_Holding.pdf In any case here is the output of the XDL tool in ISE 8.1i unix> xdl -help Release 8.1i - xdl I.24 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Xdl is a single tool with 3 fundamental modes: * Report Device Resource Information * Convert NCD to XDL (ncd2xdl) * Convert XDL to NCD (xdl2ncd) Report generates a report of the physical resources available for a specific part. Ncd2xdl reads in an NCD file and generates an ASCII XDL file. Xdl2ncd reads in an XDL file and generates an NCD file. XDL is also a fully featured Physical Design language that provides direct read and write access to Xilinx's proprietary Native Circuit Description (NCD). This access enables all users to write tools to address their individual FPGA design needs. The XDL tool explicitly states that you are allowed to create tools that use the output of NCD2XDL or tools that create input for XDL2NCD. This use of course is restricted to use for Xilinx devices per the ISE 8.1i EULA. If you want to make a tool that writes XDL or a tool that does a read/modify/write using XDL for Xilinx devices open source go ahead. We have released application notes that explain how to use XDL to modify elements in a design. Some companies like Hier Design created and marketed their own tools using this interface. We liked the Hier Design tool so much we bought the company. I don't know what you mean by "NDA restrictions on XDL". I can't find any reference to a NDA documentation. EdArticle: 95846
We have produced a special version of our programming cable that has a narrow head called PROG2N. It is a Parallel III cable that has a 14 Pin IDC narrow end that fits most 14pin 2mm headers, the price of this is £10 and shipping is dependent on how quickly you want the cable. Visit www.enterpoint.co.uk for details or email boardsales@enterpoint.co.uk ":-)" <a@b.c> wrote in message news:XzSBf.42337$mh5.1015648@weber.videotron.net... > > > Leon wrote: > > :-) wrote: > > > >>Hi I will play around with XC95xxx and I'm wondering if someone can > >>tell me if the parallel JTAG cable schematic found in the documentation > >>is worth to build ... > > > > > > You'd be better off just buying the Digilent JTAG3 cable: > > > > http://www.digilentinc.com > > > > At $12, it's just not worth building your own. One was supplied with > > the Digilent Spartan-3 kit I've got, it works very well. > > > > The price is for the cable is good, but they will charge me $18us to > send it in Quebec Canada. They used at it seems Global Express Mail > and UPS ( it's a no go for UPS, they usually charge you $50 for every > thing passing the border...). > > Weather forecast for the week seem not good I'll maybe build a proto for > the xilinx free cable . > > > > > >>I'm also looking for supplier of PLCC to DIP socket adapter, I know > >>Aries makes somes , any others cheap supplier ? > > > > > > Why not simply use a PLCC socket like I did: > > > > http://www.geocities.com/leon_heller/pld_starter.html > > > > Yes that what I'm gonna do. > Thanks for your info :-) > > > Leon > >Article: 95847
<fpga_toys@yahoo.com> schrieb im Newsbeitrag news:1138297173.649950.136370@g14g2000cwa.googlegroups.com... > So the question to Xilinx is, will Xilinx release the NDA restrictions > on XDL, and the associated library interfaces so that open source tools > can legally target ISE supported FPGAs? > > It's pretty clear that most of the regulars here, just assume that XDL > and the associated libraries, are an open interface, and think it's ok > to ignore the IP restrictions in the ISE license. The legaleze says > otherwise. > > So how about a clear definative legal statement about what are legal > ISE interfaces for open source development. > Hi mr fpga_toys, you are constantly talking about NDA restricted XDL documents, as if you have signed an NDA with Xilinx and received special documents under that NDA agreement, in wich case its better for you that read those NDA agreements (signed by you and Xilinx) over again. If you have not signed such agreements then stop talking about NDA in this context. As of your Question to Xilinx - do not expect an reply as it totally unclear what you are actually asking as you have not defined that. In the form you asked your question it would deserve a "NO" as replay from any entity that has any understanding of legal matters. Xilinx can not say YES to your question. Well you probably know that yourself. So what are you trying to achive with your push? AnttiArticle: 95848
In article <1138258290.422606.321110@g14g2000cwa.googlegroups.com>, <fpga_toys@yahoo.com> wrote: > >fpga_toys@yahoo.com wrote: >> So, given that the JHDLBits project bit the dust at Xilinx's hands, and >> it creaps into the same technology, and that Xilinx doesn't offically >> bless >> this interface to the degree of openess you suggest, let's just say it >> would >> be prudent to go a LOT slower in addopting it as the golden technology >> you suggest. I admit I mostly skimmed the JHDLBits thesis for relevent bits, but don't you think it was because JHDLBits got too heavily into the bitstream that the legal fury of Xilinx was roused? (not to defend Xilinx in squashing the project; it does seem to be duplicitous to encourage a group and then squash them. I'm only looking for ways a similar fate can be avoided) If development project sticks to XDL only and doesn't stray into bitstream issues do you think that Xilinx would make trouble for the participants? Afterall, XDL files are clearly non-encrypted, human readable ASCII files. > >Prudent to the degree of if you are young or have any assets, stay the >hell clear of it for open source projects - as you may not be able to >work >long enough in your life to pay off a judgement against you. > Was anyone in the JDHLBits development group hit with financial penalties? PhilArticle: 95849
Austin Lesea wrote: > We do not sponsor research that gives away our intellectual property. > > We expect our licenses, IP, and rights to be respected. I agree, more than you might realize. Letting open source projects proceed which violate your IP is very poor management, both on the Xilinx side, and on the educational side. You might have noticed that I've also very clearly stated that open source should not violate Xilinx IP either. It's more than obvious from these discussion that a very large portion of your user community in this forum clearly does not understand the extent that Xilinx wishes to protect it's IP, and what is, and is not acceptable disclosure outside the very restrictive NDA that is part of the ISE (and all Xilinx) software. I believe it's quiet fair to critize Xilinx for it's heavy use of open source software, while locking all access to it's ISE tool chain with strict NDA. That violates the vary rationale behind the creation of GPL software that you benefit from. But that aside, the question remains, just what, if any, legal interfaces may open source software use to augment the IDE tool chain? The strictest reading of the license and NDA is clear ... NONE. Since Xilinx stopped that JHDLBits project from releasing, after many very public months of work, it's only fair to ask that Xilinx reconsider it's NDA boundries and consider that open source development may well greatly enhance the Xilinx product offerings over the next several years in ways that are difficult to fully describe today. If the official answer in absolutely none, as the terms of the current license require, that is fine ... and I will clearly state so in the FpgaC project and remove all Xilinx interfaces so Xilinx IP rights are not violated.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z