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Antti <Antti.Lukats@xilant.com> wrote: > the schematic of that part is removed from the schematic printouts, its > a duplicate of platform usb cable - as the platform cable pld on > starterkit board is in non-BGA package it should be fairly simply to > pull up the pins that go to on board jtag and use the starterkit as > normal platform usb cable :) However to my knowledge, the "platform usb cable" is considered as their IP by XILINX and no documents to build your own cable are available... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 98851
Ralf, I want to know how can i connect this to PCB? Laura Ralf Hildebrandt =E5=AF=AB=E9=81=93=EF=BC=9A > laura_pretty05@yahoo.com.hk wrote: > > > I mean how can I connect the sensor to the FPGA board, how to connect > > the pin on FPGA board? Thanks. > > (I am not shure, if I understand you right.) > Most UP2 Education Boards are shipped with no pins at the FLEX_EXPAN_X > connectors. You have to solder some by yourself. >=20 > RalfArticle: 98852
Peter Alfke wrote: > Throw in less testing cost, and EasyPath becomes a good business > proposition. We do not have to go "dumpster diving" to make money with > it. It's all basic statistics and some sound reasoning. I understand a lot of the testing for Virtex FPGA's is built on using the reconfigurable interfaces to load dynamic tests. I remember reading about that in the past, plus saw a 3rd party selling such tests to customers for in field verfication. As soon as the chip becomes "hard" with the routing frozen, that quickly goes away as an option, so that customer test vectors must be written based for full coverage of the design again (just as with ASICs). And good coverage BIST becomes difficult again. This seems to me that it increases testing complexity and NRE, not reduce it. That it then requires expensive testers for all testing, rather than using generic loadable BIST configurations which can be managed by less expensive test interfaces.Article: 98853
Can't you adapt the parameters of the processor DDR controller ? Rgds Andr=E9 > Hello grps, > > Can you tell me what is the basis for selecting the DDR controller? For > example i have a micron DDR SDRAM and i have to see if it compatible > with the DDR controller which is within network processor. Wht all > parameter should i check? > Please let me know that >=20 > Regards > PraveenArticle: 98854
On a sunny day (Thu, 16 Mar 2006 17:37:03 -0800) it happened austin <austin@xilinx.com> wrote in <dvd3p2$p6714@xco-news.xilinx.com>: >Jim, > >OK, here is the problem: > >If you buy Froto's uP, they make a new one every year, and you have no >choice but to switch to the new unit, or stock enough of the old units >to serve your entire replacement need. > >So, the car company goes to Froto, and say "Froto: attention! We want >the same uP guaranteed for a long time." mmmm a new 8052 comes out every year. We had 'clockless' 8052 here discussed not so long ago. Not agianst FPGA in cars, just generally scared of electronics in essential parts in cars ..connector corrosion, no brakes, engine control responding to local cell-phone tower... you read the news. Lost if discussion on that in for example sci.electronics.design. the funniest thing I did read was the Japanese (think it was) police will get a device (transmitter) that can remotely stop a getaway car..... I was sort of thinking how long it would take before the bad gusy controlled the police car... Now we have viruses and worms in RFID tags already, http://www.rfidvirus.org/index.html Now viruses and worms in the CPU embedded in the cars.... But OK nothing beats FPGA for speed and versatility.Article: 98855
Jhon has added another dimension to fpga.You once again proved that Birds of a feather flock together.This is the characteristic to hide your ignorance and prooving what you know about. Sneezing unnecessarily is not going to help you man.And as you and your fellow partners showed that what a big fuss a bunch of fools can make to a FPGA problem.Forthcoming friends will always remember your contribution to this post.Article: 98856
Hi there, currently I am trying to instantiate addsub components and comparators for resource sharing, because XST seems to be unable share reources even with "resource sharing" enabled (I get the same number of adders instiantiated for each + sign that I use). I am coding in VHDL. My question is, is there a list of the library of components for Xilinx that I can instantiate and where can I find it? Currently I have only discovered I can use "addsub" component for adding and subtracting, but I'm unable to find the key names for comparators, or bitwise operations.Article: 98857
Hi all, the ppc in edk has two interrupt inputs critical and exteranl.. if I choose to connect my peripheral_a interrupt to the external intr input and my peripheral_b interrupt to the critical input do i need an interrupt controller ? Thanks in advance, Mordehay.Article: 98858
fpga_toys@yahoo.com wrote: > As soon as the chip becomes "hard" with the routing frozen, that > quickly goes away as an option, so that customer test vectors must be > written based for full coverage of the design again (just as with > ASICs). And good coverage BIST becomes difficult again. Still pondering this question after reading a bit more from the Xilinx site. Two issues are still nagging at me. Since the full fpga isn't tested, that presumably means that sections of any particular device purchased under the easypath program may have serious problems that are not screened for, which would prevent the customer from using generic 3rd party reconfigurable self tests for that FPGA device which use resources outside of the two qualified "hard" bitstreams, since the generic tests may fail in unpredicable ways. This means that the customer still has an application specific test development expense, similar to that for an ASIC, but with limited ability to design for test as they would with an ASIC. This seams to complicate the post board attach and RMA board level testing, rather than make it easier than an ASIC. Ditto for field diagnostics. The Xilinx statements are that easypath devices are identically the same fpga. Then what stops a large customer from purchasing only easypath qualified devices in very large quanties and use those that pass a full device test as replacements for applications that need full reconfigurable FPGA features, and those that don't, in the application that they were originally screened for? With up to 80% discounts this seems an attractive way to play the yield odds for very discounted full function devices, with customer testing/binning of the rejects to the applications they submitted the bitstreams for. Assuming Xilinx's yields are not totally tanked, it seems that if they are willing to sell minimally tested devices for the best possible prices, then there is a market for 3rd parties to do the testing and screening, leveraging the volumes and margins over several products/customers. I'm thinking here that many reconfigurable computing applications could be designed around qualified device section failures with mimimal effort using dynamic linking (Place and route). I would not have a problem at all building large systems that included dynamic defect sparing, much we do with drive arrays, to get the best possible price for high end systems, as well as consumer grade home/hobby systems. If Xilinx is offering 80% discounts for minimally tested devices, what discounts can I get for ones which are mostly functional, but with a few known failures to map out? Maybe up to 20-30% of the device? These would be rejected and scrapped as failures if I understand the firm no-binning/selection of failures statements. So it seems they could also have even better discounts as they are "free" profits from scrap materials.Article: 98859
gosh! just take a buzzer enabled multimeter and sit down for one evning, there are some wires between the cypressFX2 and coolrunner, that is it basically. the usb cable does not contain any preprogrammed firmware (except usb vid/pid,,) so you just duplicate it, then force impact to perform PLD update and ready you are ! sure xilinx doesnt document how to do this, but it really isnt that complicated. AnttiArticle: 98860
xilinx rocketio is not fully SATA compliant so the SATA sockets on ML300 and XUPV2P are just someones "wishfull thinking.." ! on the ML300 I did someting useful with the SATA connector, namly I did take a SATA cable cut it half, soldered a buzzer onto it, then plugged into SATA connector on ML300 and programmed the rocketIO on the ML300 to make an audiable BEEP BEEEEP BEEP pretty expesive way of making BEEP (4600 USD !!) you can do the same on your board, for less money :) ok, jokes beside I have implemented a SATA OOB circuitry with NO external circuitry with V2Pro rocketio it worked with some Silicon image SATA bridge, eg i monitored the link to come up eg the in band signalling started and MGT got locked but--- for you best advice just forget those SATA sockets!!! (unless you want to make a BEEP) AnttiArticle: 98861
There is an external reset that feeds to the reset block in the EDK project. The reset block will wait for a lock signal from the DCM. The reset block is a Xilinx block which has work for most of my design. The custom peripheral contains a PRBS test carried out to a DDR fifo interface. The software polls the register to read the results from the test The DDR interface has work for a FPGA design without the PowerPC on the same chip. Anyway I have decided not to use the custom peripheral as it seem to be the culprit within my PowerPC design for that particular chip. Paul Mike Treseler wrote: > eziggurat@gmail.com wrote: > > > I have added a ChipScope core and > > the waveform seems to indicate the reset seem to be flunctuating and > > this seem to indicate the DCM is maybe not locked properly or reset is > > actually flunctuating. The strange thing is that I have a signal which > > is the inverse of reset but the waveform does not seem to show it. > > Try an external reset. > > -- Mike TreselerArticle: 98862
Do you recommend the Digilent board? I want to practice my skills on high speed comms using this board and also want a flexibility to work on some algorithms like MPEG etc.. Cheers PaulArticle: 98863
me_2003@walla.co.il wrote: > Hi all, > the ppc in edk has two interrupt inputs critical and exteranl.. > if I choose to connect my peripheral_a interrupt to the external intr > input and my peripheral_b interrupt to the critical input do i need an > interrupt controller ? > Thanks in advance, Mordehay. > No. This was the first thing I got to work! I had my own hardware generate an interrupt signal and I used the Xilinx BSP for the Power PC to hook the interrupts in software. I have noticed though that the interrupt latency is quite high on the Power PC (10uS! @ 100Mhz clock). Not sure where the weak link was in the software chain. I was using the Xilinx provide functions for hooking my own interrupt function. I had a project tha continuously held the critical interrupt high. In the ISR, I toggled the LED. At a 100Mhz clock, the pulse with was 10uS! -EliArticle: 98864
Peter Alfke wrote: > Mr Toy, I have never claimed 80% saving from reducing the testing cost. > > But I have shown, by a hypothetical example, that we can double the > yield, and thus cut the EasyPath basic manufacturing cost in half. We > can thus sell these parts for half price, while maintaining our usual > margins. Only if you consider margin as a percentage of sales. That may be standard practice, but the implication may not immediately be clear. Under your above explanation, you would be making only about half as much money per chip with easypath devices as with regular devices, and it seems that your willingness to do that is a source of a fair chunk of the savings.Article: 98865
the V2VP30 board for the uni price? sure !! that price is below component self cost !!! just done excpect find nice and easy workin SATA solution for that board (or in that matter any V2P board) anttiArticle: 98866
Hi, Please do the following way: LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; signal A : unsigned(4 downto 0); -- example signal B : unsigned(4 downto 0); -- example In the code area, -- they can be in process or between process area. A <= A + 5; B <= B - 7; No need to instantiate any module. In numeric.vhd liberary, all arithmatic operations are functions. WengArticle: 98867
Eli Hughes wrote: > > I have noticed though that the interrupt latency is quite high on the > Power PC (10uS! @ 100Mhz clock). Not sure where the weak link was in > the software chain. I was using the Xilinx provide functions for > hooking my own interrupt function. I had a project tha continuously > held the critical interrupt high. In the ISR, I toggled the LED. At a > 100Mhz clock, the pulse with was 10uS! > > -Eli That means each ISR took ~1000 wallclock cycles. Were you executing out of internal BRAM or external DRAM? Were the caches enabled? PaulArticle: 98868
The SATA connectors are useful for Board-to-Board communication using the Aurora protocol. The "Using High Speed Serial MGTs with the Aurora IP" Quickstart at http://www.xilinx.com/univ/xupv2p.html is a good place to start. Paul Antti wrote: > > xilinx rocketio is not fully SATA compliant so the SATA sockets on > ML300 and XUPV2P are just someones > > "wishfull thinking.." ! > > on the ML300 I did someting useful with the SATA connector, namly I did > take a SATA cable cut it half, soldered a buzzer onto it, then plugged > into SATA connector on ML300 and programmed the rocketIO on the ML300 > to make an audiable > > BEEP BEEEEP BEEP > > pretty expesive way of making BEEP (4600 USD !!) > > you can do the same on your board, for less money :) > > ok, jokes beside I have implemented a SATA OOB circuitry with NO > external circuitry with V2Pro rocketio > it worked with some Silicon image SATA bridge, eg i monitored the link > to come up > eg the in band signalling started and MGT got locked > > but--- for you best advice > > just forget those SATA sockets!!! (unless you want to make a BEEP) > > AnttiArticle: 98869
Paul Hartke wrote: > Eli Hughes wrote: > >>I have noticed though that the interrupt latency is quite high on the >>Power PC (10uS! @ 100Mhz clock). Not sure where the weak link was in >>the software chain. I was using the Xilinx provide functions for >>hooking my own interrupt function. I had a project tha continuously >>held the critical interrupt high. In the ISR, I toggled the LED. At a >>100Mhz clock, the pulse with was 10uS! >> >>-Eli > > > That means each ISR took ~1000 wallclock cycles. Were you executing out > of internal BRAM or external DRAM? Were the caches enabled? > > Paul Everything was out of BRAM. Can't remember if caches were enable. I have to check the project (Was about 6 months ago). The only thing else I could figure was that my bit I was toggling was a GPIO on the OPB. I know that OPB is very slow and may be hanging things up. Either that or the Xilinx BSP interrupt functions are very bloated. Never got that figured out. My resolution was to make my own DMA controller on the PLB to transfer data over the bus. I never hooked anything system critical to an interrupt, I always used hardware. Only things like the serial port, etc. were tied to an interrupt. -EliArticle: 98870
laura_pretty05@yahoo.com.hk wrote: > I want to know how can i connect this to PCB? I again do not understand you well. If you just write one unclear sentence there are a lot of possible alternatives. Do you mean pin assignments from the FPGA to the I/O pins at FLEX_EXPAN_X? Use your synthesis tool. There must be an option, that is called "pin assignments" (or similar). MaxPlus+ generates an acf-file, where you may edit the pin assignments with a text editor. Or otherwise search the menu. There is always a manual for the synthesis tool. RalfArticle: 98871
Metal, Pessimists always claim they are just observing reality. You must be working for one of those companies "circling the drain?" Really hard to be positive about anything. I see (our) business increasing (a lot), and I see margins that are good, and getting better, and I see new opportunities popping up all over the place. And I see the financials that support it. You have told all of us how we will need food, shelter, and a few sticks to burn here in the not so distant future. AustinArticle: 98872
sure they can be used for any non-SATA protocol you can imagine, be it Aurora or something else. but having SATA connectors on board is very misleading as people will think the SATA connectos could be used for SATA !!! AnttiArticle: 98873
coolsaroj@gmail.com wrote: > Here is another kind of breed like Jeremy which is scared of > exclamation marks...unbelievable... You got two technical answers and one formal hint. Extract the information you need and think about the hint ... and let me give you another hint: It might be not a good idea to shit on the boots of a regular. RalfArticle: 98874
Isn't that obvious? If the product costs us half as much to make (higher yield), then we can sell it for half the price, and make the same perent margin. Margin is always expressed as a percentage. There is no other way. I really thought that everybody would understand that... Peter Alfke
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Compare FPGA features and resources
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