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We´re planning to implement a PCI-target as a Bridge between the PCI-Bus and an ASIC that controls a peripheral bus in our applications. Redesigning the ASIC probably would be far more expensive the an intelligent bridge. The complexity should be around 6k so I´m thinking of using an EPF8820A. How are Youre experiences concearning PCI-Compliance? What about ACTEL? I´ve never heard the word PCI out of their mouth!? Would an A1280XL serve the same purpose or is this a unfair comparison between ACTEL and ALTERA? Any Input is wellcome. Thanks ========================== Thomas St.Pierre SIEMENS AG GermanyArticle: 1776
Looking for verilog models for XC4000 CLB and IOB, can anyone help me out? Thanx.. Jatan Shah jshah@vlsi1.ee.iastate.eduArticle: 1777
Seccond hand altera software wnted . write to : Yl_model@netvision.net.il best wishes . Eliaho cahana.Article: 1778
Does anyone know of any VHDL savy editing applications under UNIX? I've been using CodeRight under Win 3.1 and am moving to UNIX and would like a decent editor. I have Emacs and Vi. Kent -- /* "There is no king who has not had a slave among his ancestors and */ /* no slave that has not had a king among his." ---- Helen Keller */ /* Kent L. Shephard ----- K. L. Shephard Consulting */Article: 1779
msojones@cix.compulink.co.uk ("Michael Jones") writes:
>> get the amd package from ftp://ftp.ix.de/pub/elrad/060
>> there is palasm and mach-xl
>I tried to get it but anon ftp permission denied!
>Is there anywhere else I can get these from?
Yes, of course. The elrad FTP-Server is mirrored by some
universities here in Germany, a complete list is
published in the magazine elrad.
One mirror is
ftp://ftp.uni-paderborn.de/elrad/Area-60
-----------
Karl-Heinz Wietzke sp_kw@physik.uni-paderborn.de
Article: 1780Altera has a PCI Design Kit,which includes an application note as well as a diskette containing templates and macrofunctions for Altera's different families for PCI design. Kiran Vittal Serial System, S'pore Lynn West (lynnwest@netcom.com) wrote: : I have been told that Actel has produced an app note describing a : method for implementing a PCI interface using their FPGAs, but cannot : confirm the report, and my calls to Actel are so far unanswered. : Anyone know of such an app note? : Lynn WestArticle: 1781
I have the xilinx place & route software (for DOS) which works for parts up
to xc3030, and I would like to upgrade to software which covers all of their
chips. Last time I tried, they wanted $2500.00 for the full package and
gave no discount for the $1000.00 I already spent. I have heard of people
getting good deals in the past, and am wondering where or who I should talk
to get this software at a more reasonable price.
Are there any good retail or mail-order places that offer the software for
less? Any particular xilinx rep. who I should talk to to get a good
discount? Any third party software for less than $2000.00?
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 1782
Does anybody know the system requirements for programming the Flex10k
ie Can Max+Plus II version 5.0 be used or modified to do the job, or
is an updated version required?
If so, will this also require a new physical programmer, or just
another socket?
Is 32Mb of RAM still the minimum required for the programming PC?
Finally what would be the price range of the EPF10K100
Regards
Michael
Article: 1783There is an emacs extension that implements VHDL specific editor features. It does keyword completion and capitalization. it also does dynamic prompting for filling in parts of statements. For example if you type entity and hit the proper key sequence, it will prompt you for the name and fill in the rest for you. so you will end up with ENTITY my name is END ENTITY This seems more useful for people who are not real familiar with the syntax. It also does highlighting, and it has some special key bindings. For instance, typing .. gives you =>. It also has a special commenting mode. you can comment out blocks, single lines, or add comment headers. to get the files, try emailing ken wood ken@eda.com.au.If you don't get a response from him, I will post it to the net. Ken is managing the whole thing, and has the most current version. My version is a bit older. scott -- __________________________________________________ | | | homebrew is the elixir of the gods | | | --------------------------------------------------Article: 1784
There is an emacs "vhdl mode" out there; I use it on unix, for the most part it consists of keymap shortcuts for major design elements and comments. ---------------- James Bock, Engineer e-mail: jim@EnTechnology.com En Technology, Inc. 78 Elm St., POB 657 TEL: 603/863-1904 Newport, NH 03773-0657 FAX: 603/863-9310 --Entropy isn't what it used to be.Article: 1785
If you want to blow off this headhunter and deal with the company directly,
it's AT&T in their Microelectronics Division. I even have the e-mail address
somewhere for these people. Remember: Headhunters are only interested in
getting *somebody* in this job so they can collect a fee -- they don't give
a damn if it's you or anyone else. As long as they collect their fee,
they're happy.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3443 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
eddie amara <amaraju@onramp.net> wrote:
> FORTUNE 100
>
>Technical Marketing Engineering position in the FPGA product family in the
>areas of strategic marketing and product development. Will participate in
>FPGA activities including the identification of target applications in
>response to customer input. Perform the FPGA implementation and
>corresponding documentation for the target applications.
>Publish/participate in application notes,product briefs,data sheets and
>other documentation.
>
>Job Requirements-Solid understanding of system logic design using
>programmable logic,FPGAs,schematic capture tools, FPGA place/route
>tools,and logic synthesis. Good interpersonal communication and writing
>skills.
>
>At least 3 years of system and/or logic design experience. 3 years
>experience with popular FPGA products such as Xilinx,Altera,Actel or
>Quicklogic devices.
>
>Education-BSEE or BSCS
>
>Salary-50 to 70K + 12% Bonus
>
>Location-Allentown,Pa.
>
>--
>Eddie Amara
>SpencerSearch,Inc.
>Voice 214-931-3060
>Fax 214-931-8471
>amaraju@onramp.net
Article: 1786
If you want to blow off this headhunter and deal with the company directly,
it's AT&T in their Microelectronics Division. I even have the e-mail address
somewhere for these people. Remember: Headhunters are only interested in
getting *somebody* in this job so they can collect a fee -- they don't give
a damn if it's you or anyone else. As long as they collect their fee,
they're happy.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3443 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
eddie amara <amaraju@onramp.net> wrote:
> Prestigious Research Labs!!!!
>
>Join one of the fastest growing divisions of this Fortune 50 Corp. FPGA !!!!!
>
>FPGA Applications Engineer-Owns the complete implementation of the
>design.Supports the FAE and ultimately responsible for having the design
>work in the customers system.
>
>Other resposibilities-Customer design win support.
> Support customers and FAE with problem designs
> Contribute to regional tag teams
> Periodically visit customer base
> Act as a Hardware or CAD platform champion
> Customer and FAE training
> Apps notes
> Documentation
>
>Skills/Exp-System logic design
> Programmable logic
> FPGAs
> Schematic capture tools
> FPGA place and route tools
> Good communication and writing skills
>
>Education-BS or MS in EE or CS and 5 years of system and or logic design
>will be considered.
>
>Salary-$50 to $70 +12% bonus
>
>Location--Allentown,Pa.
>
>
>no new grads or those withonly university work,thanks.
>
>--
>Eddie Amara
>SpencerSearch,Inc.
>Voice 214-931-3060
>Fax 214-931-8471
>amaraju@onramp.net
Article: 1787
If you want to blow off this headhunter and deal with the company directly,
it's AT&T in their Microelectronics Division. I even have the e-mail address
somewhere for these people. Remember: Headhunters are only interested in
getting *somebody* in this job so they can collect a fee -- they don't give
a damn if it's you or anyone else. As long as they collect their fee,
they're happy.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3443 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
In article <amaraju-2108950932480001@dal11.onramp.net>,
eddie amara <amaraju@onramp.net> wrote:
> Fortune 100
>
>Technical Engineering position in FPGA product family in the Systems
>Integration Group supporting the FPGA product family and its CAE design
>kits.
>
>Responsibilities include the integration and testing of 3rd party CAe
>design kits,including the development of test cases, verification of
>libraries and design flows.
>
>Must be experienced in synthesis and schematic capture,functional and
>timing simulation using popular 3rd party CAE tools (Synopsys, Verilog,
>Mentor,VHDL) and in logic verification methods.FPGA design experience
>strongly desirable. FPGA architecture knowledge or programming skills a
>plus. Strong technical,interpersonal communication, and writing skills.
>
>At least 3 years experience.
>
>Education-BS or MS in EE or CS.
>
>Location-Allentown,Pa.
>
>Salary- 50 to 70K + 12% Bonus
>
>--
>Eddie Amara
>SpencerSearch,Inc.
>Voice 214-931-3060
>Fax 214-931-8471
>amaraju@onramp.net
Article: 1788
If you want to blow off this headhunter and deal with the company directly,
it's AT&T in their Microelectronics Division. I even have the e-mail address
somewhere for these people. Remember: Headhunters are only interested in
getting *somebody* in this job so they can collect a fee -- they don't give
a damn if it's you or anyone else. As long as they collect their fee,
they're happy.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3443 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
In article <amaraju-2108950935150001@dal11.onramp.net>,
eddie amara <amaraju@onramp.net> wrote:
> FORTUNE 100
>
>Product Engineering position in FPGA product family supporting 3rd party
>CAE design kits.
>
>Responsibilities include development, integration, testing, delivery,
>documentation, and support of FPGA Product family. Opening are in Synopsys
>and Cadence/Verilog.
>
>Experience in schematic capture,functional and timing simulation, and
>synthesis. Knowledge of netlist formats,simulation modeling, and awk/perl.
>FPGA design experience desirable. Strong technical,interpersonal
>communication, and writing skills. At least 3 years experience.
>
>Education-BS or MSEE or CS
>
>Salary-50 to 70K + 12% Bonus
>
>Location-Allentown,Pa.
>
>--
>Eddie Amara
>SpencerSearch,Inc.
>Voice 214-931-3060
>Fax 214-931-8471
>amaraju@onramp.net
Article: 1789
If you want to blow off this headhunter and deal with the company directly,
it's AT&T in their Microelectronics Division. I even have the e-mail address
somewhere for these people. Remember: Headhunters are only interested in
getting *somebody* in this job so they can collect a fee -- they don't give
a damn if it's you or anyone else. As long as they collect their fee,
they're happy.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3443 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
In article <amaraju-2808951009470001@dal15.onramp.net>,
eddie amara <amaraju@onramp.net> wrote:
>
>
>FPGA Development Engineer
>
>Responsibilities:Development of FPGA architecture and of the integrated
>circuits that implement the architecture.Specific resposibilities include
>working with FPGA software developers to ensure that the architecture can
>be effectively exploited by the software and working with the marketing
>organization to understand the needs of the customers.
>
>Skills/Exp.:Understand the FPGA architecture trade-off.Good understanding
>of full custom circuit design,System knowledge and logic design.
>
>Education:PhD/MS in EE/CS/Physics and at least 3 years exp.
>
>Location:Allentown,PA.
>
>Salary:$50 to $80K + 12% bonus
>
>NO NEW GRADS OR THOSE WITH ONLY UNIVERSITY WORK EXPERIENCE,THANKS.
>
>--
>Eddie Amara
>SpencerSearch,Inc.
>Voice 214-931-3060
>Fax 214-931-8471
>amaraju@onramp.net
Article: 1790Michael <michael@ee.latrobe.edu.au> writes: >Does anybody know the system requirements for programming the Flex10k >ie Can Max+Plus II version 5.0 be used or modified to do the job, or >is an updated version required? The latest version of Max+Plus II (5.4) does not appear to support FLEX 10K, though it should be included in future versions (probably at extra cost). You probably will want to upgrade anyway. 5.0 is nearly a year old, and there have been many improvements in the software since then. >If so, will this also require a new physical programmer, or just >another socket? It looks like Altera has a new serial configuration EPROM (the EPC1) to go along with the 10K family, so I wouldn't be surprised if it needed a new socket. I doubt you would need a new programming base unit, though. You can also program it via the JTAG ports, or through a BitBlaster download cable. >Is 32Mb of RAM still the minimum required for the programming PC? I don't know, but certainly the larger the part, the more memory and CPU power you will need. The 10K100 you mentioned is a _big_ part (4,992 logic cells and 406 I/Os). I wouldn't be surprised if it chokes a 32MB machine. For more information, I strongly suggest you check out Altera's new web page at http://www.altera.com. They just added on-line data sheets and appnotes. They have a 50-page data sheet there on FLEX 10K. It will answer most of your questions. -Paul -- Paul Secinaro (pss1@christa.unh.edu) Synthetic Vision and Pattern Analysis Laboratory UNH Dept. of Electrical and Computer EngineeringArticle: 1791
Jatan: I take it you need the model for simulation in which case you can use Exemplar tools to output a structral verilog model and simulate that. The way I do simulation for FPGAs is through Logic Modeling( now Synopsis) models that can read in JEDEC/XNF/EDIF files. Regards, Kayvon Irani Lear Astronics, Los AngelesArticle: 1792
hi
does anybody know how I enter constraints to a design
targeted to Xilinx 4000. I do not have schematics but a vhdl
code.
thank you
Maya Reuveni Tel: 972-9-986973 ext. 9
Manager of Hardware Department Fax: 972-9-986980
HaTaasiya 9, Raanana 43100, Israel. E-mail: maya@asp.co.il
--
Maya Reuveni Tel: 972-9-986976
Manager of Hardware Department Fax: 972-9-986980
HaTaasiya 9, Raanana 43100, Israel. E-mail: maya@asp.co.il
Article: 1793A technical report with our collected experience about synthesis for FPGAs is now available via WWW at URL http://www.vlsivie.tuwien.ac.at/mike/vhdl4fpga We hope this will be useful to other users... m. -- Michael Gschwind, Institut f. Technische Informatik, TU Wien snail: Treitlstrasse 3-182-2 || A-1040 Wien || Austria email: mike@vlsivie.tuwien.ac.at PGP key available via www (or email) www : URL:http://www.vlsivie.tuwien.ac.at/mike/mike.html phone: +(43)(1)58801 8156 fax: +(43)(1)586 9697 Boycott Whaling!!! Boycott Norway!!! Boycott Norwegian Products!!!Article: 1794
Maya Reuveni (maya@asp.co.il) wrote: : hi : does anybody know how I enter constraints to a design : targeted to Xilinx 4000. I do not have schematics but a vhdl : code. : thank you Some compilers (e.g. EXEMPLAR) support user-defined attributes and you can use those attributes to add the constraints to your design (I think this is mentioned in EXEMPLAR manual or application notes). If you are less lucky and your compiler does not support this feature (e.g. ViewLogic) you will have to put yor constraints in a separate file (or files). If your platform is PC this file(s) will usually have extention ".cst". If you use XACT 5.0 be careful : the parser for the cst files has a lot of bugs. ( I hope they fixed it in the last revision of XACT software).Article: 1795
unsubscribeArticle: 1796
The VHDL output file of Altera's Max+PlusII conatins timing parameters, therefore, I'd like to simulate my design with Viewlogic's Powerview VHDL simulator, which is IEEE-compliant. Though the VHDL file passed the Vhdl analyzer, it could not be simulated. The reason is that in the file there are configuration statements missing. Those instantiated components are unbounded!!! To think I use Exemplar's core to synthesize my VHDL into *.tdf. With VHDL in and VHDL out, I could have the familiar tools, without having to generate redundant schematic files, netlist files. etc. Now it seems that the interface between Max+Plus II and Powerview is much worse than Altera advertises. Ask for help! Felix K.C. CHENArticle: 1797
3rd Workshop on Designing Correct Circuits
==========================================
The third workshop on Designing Correct Circuits will be held
on Monday 2 September to Wednesday 4 September 1996 at Baastad in Southern
Sweden. (The HUG'96 meeting will take place during the previous
week in Finland.) The two previous workshops DCC workshops have been held
in Oxford and Lyngby.
Relevant topics include but are not limited to:
> formal hardware design languages,
> hardware design by transformation,
> computing-aided design and verification of hardware,
> high level synthesis and silicon compilation,
> techniques for the design of FPGA circuits,
> methods of designing testable circuits,
> analysis of circuit descriptions,
> novel VLSI algorithms and architectures,
> asynchronous circuit design.
The workshop will be of interest to researchers in the area of formal
methods for hardware design, and to engineers in industry wishing to
keep abreast of this fast-moving and exciting field.
The program committee for this workshop will include:
> Kees van Berkel (Philips, The Netherlands)
> Graham Birtwistle (University of Leeds, UK)
> Albert Camilleri (Hewlett-Packard, USA)
> Geraint Jones (University of Oxford, UK)
> Wayne Luk (Imperial College, UK)
> Tom Melham (University of Glasgow, UK)
> Robin Sharp (Technical University of Denmark, Denmark)
> Mary Sheeran (Chalmers Technical University, Sweden)
> Satnam Singh (University of Glasgow, UK)
> Richard Taylor (Hewlett-Packard, UK)
Call for Papers
===============
You are invited to submit a draft full paper (four copies if
convenient) on a relevant subject by Wednesday 31 January 1996. Notification
of acceptance will be posted by mid April, and revised papers will be
due about six weeks later.
The email address for submissions and more information is:
dcc-workshop@comlab.ox.ac.uk
The most up-to-date information about this workshop can be found at the URL:
http://www.dcs.gla.ac.uk/~satnam/dcc.html
Papers can be sent by post to:
DCC'96 Workshop
Satnam Singh
Dept. Computing Science
University of Glasgow
Scotland, G12 8QQ
United Kingdom
Tel: +44 141 330 4454
Email: satnam@dcs.gla.ac.uk
______________________________________________________________________________
Dr. Satnam Singh Phone: +44 141-330-4454
Dept. Computing Science, Fax: +44 141-330-4913
The University of Glasgow, E-Mail: satnam@dcs.glasgow.ac.uk
Scotland G12 8QQ, United Kingdom. Talk: satnam@copinsay.dcs.gla.ac.uk
E-Mail (X.400): "/S=satnam/OU=DCS/O=GLASGOW/PRMD=UK.AC/ADMD= /C=GB/"
URL: http://www.dcs.gla.ac.uk/~satnam
______________________________________________________________________________
"You should be glad that bridge fell down - I was planning to build thirteen
more to that same design" - I.K. Brunel
Article: 1798Mind your own business pal, I have a job to do and yours is not to get into my business. Yes, we do look for somebody for a position and that position is usually better than what they have now, have a problem with that? You wish you can make the money us headhunters make. In article <DE8nrM.py@world.std.com>, jcooley@world.std.com (John Cooley) wrote: :If you want to blow off this headhunter and deal with the company directly, :it's AT&T in their Microelectronics Division. I even have the e-mail address :somewhere for these people. Remember: Headhunters are only interested in :getting *somebody* in this job so they can collect a fee -- they don't give :a damn if it's you or anyone else. As long as they collect their fee, :they're happy. : - John Cooley : Part Time EDA Consumer Advocate : Full Time ASIC, FPGA & EDA Design Consultant : :=========================================================================== : Trapped trying to figure out a Synopsys bug? Want to hear how 3443 other : users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)! : : !!! "It's not a BUG, jcooley@world.std.com : /o o\ / it's a FEATURE!" (508) 429-4357 : ( > ) : \ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys, : _] [_ Verilog, VHDL and numerous Design Methodologies. : : Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222 : Legal Disclaimer: "As always, anything said here is only opinion." : :eddie amara <amaraju@onramp.net> wrote: :> Prestigious Research Labs!!!! :> :>Join one of the fastest growing divisions of this Fortune 50 Corp. FPGA !!!!! :> :>FPGA Applications Engineer-Owns the complete implementation of the :>design.Supports the FAE and ultimately responsible for having the design :>work in the customers system. :> :>Other resposibilities-Customer design win support. :> Support customers and FAE with problem designs :> Contribute to regional tag teams :> Periodically visit customer base :> Act as a Hardware or CAD platform champion :> Customer and FAE training :> Apps notes :> Documentation :> :>Skills/Exp-System logic design :> Programmable logic :> FPGAs :> Schematic capture tools :> FPGA place and route tools :> Good communication and writing skills :> :>Education-BS or MS in EE or CS and 5 years of system and or logic design :>will be considered. :> :>Salary-$50 to $70 +12% bonus :> :>Location--Allentown,Pa. :> :> :>no new grads or those withonly university work,thanks. :> :>-- :>Eddie Amara :>SpencerSearch,Inc. :>Voice 214-931-3060 :>Fax 214-931-8471 :>amaraju@onramp.net -- Eddie Amara SpencerSearch,Inc. Voice 214-931-3060 Fax 214-931-8471 amaraju@onramp.netArticle: 1799
synopsis: Eddie post an in-appropriate article to the group
John warms up a flame thrower, and sets it to medium
Eddie shows total lack of understanding of why he is being toasted
Philip jumps in to defend poor John (got to protect these farmers)
>:eddie amara <amaraju@onramp.net> wrote:
>:> Prestigious Research Labs!!!!
>:>
>:>Join one of the fastest growing divisions of this Fortune 50 Corp. FPGA !!!!!
>:> (a phone company that argues that the reason you should use their
>:> services over MCI or SPRINT is because they are ATT. i.e. just the name)
>:>FPGA Applications Engineer-Owns the complete implementation of the
>:>design.Supports the FAE and ultimately responsible for having the design
....... etc....etc...etc
>In article <DE8nrM.py@world.std.com>, jcooley@world.std.com (John Cooley) wrote:
>:If you want to blow off this headhunter and deal with the company directly,
>:it's AT&T in their Microelectronics Division. I even have the e-mail address
>:somewhere for these people. Remember: Headhunters are only interested in
>:getting *somebody* in this job so they can collect a fee -- they don't give
>:a damn if it's you or anyone else. As long as they collect their fee,
>:they're happy.
>: - John Cooley
..... etc....etc... followed by a rather excessively long .sig
In article <amaraju-0409951515320001@dal17.onramp.net> amaraju@onramp.net (eddie amara) writes:
>Mind your own business pal, I have a job to do and yours is not to get
>into my business. Yes, we do look for somebody for a position and that
>position is usually better than what they have now, have a problem with
>that? You wish you can make the money us headhunters make.
Dear Eddie,
Please get a clue, ( and while your at it, learn some grammar too).
This group is for TECHNICAL discussion on FPGA based computers. There are
more than sufficient groups out there for job postings, and this ISN'T one
of them. Your total lack of good manners by posting multiple job postings
to this group easilly wins the prize of stupiddest poster since this group
was formed. If people are looking for jobs, they know where to look, and if
they are looking for technical discussion, they look here. Your crass-ness
of thinking that John flamed you because of the fees you charge your clients
demonstrates what a poor headhunter you are. You clearly do not understand
what motivates most engineers to do what they do (clue: it aint the $$),
and so I would expect that your ability to match employers with employees
would be marginal at best.
Philip Freidin
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