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Messages from 2275

Article: 2275
Subject: Any user experiences with Exemplar VHDL synthesis for FPGA
From: ramesh@montero.wh.att.com (-N.RAMESH)
Date: Thu, 16 Nov 1995 15:05:32 GMT
Links: << >>  << T >>  << A >>
Hello:

I would like to hear from anyone who has used the Exemplar tools to
design FPGAs (especially the AT&T ORCA 2C devices).  We are trying to
make a decision on the right tools for ORCA and any input would be
appreciated.

Thanks

N. Ramesh (ramesh@fuwutai.wh.att.com)




Article: 2276
Subject: Re: [Q] FPGA Software for Linux
From: wirthlim@timp.ee.byu.edu (Michael J. Wirthlin)
Date: 16 Nov 1995 08:22:18 -0700
Links: << >>  << T >>  << A >>

In article <48eu90$gc8@rs18.hrz.th-darmstadt.de>, bon@elektron.ikp.physik.th-darmstadt.de (Uwe Bonnes) writes:
|> Hallo,
|> 
|> is there any software to design FPGAs available for the Linux Operating
|> system or planned to be available in the next future?
|> 

There is a schematic capture program called chipmunk available in Linux.
Somebody mentioned that they would port the Xilinx libraries into chipmunk
a few months ago, but I don't know the status of their work. As far as I
am aware, the manufacturer place and route tools are only available on 
standard operating system platforms.

-- 
Michael J. Wirthlin
Brigham Young University - Electrical Engineering Department
Reconfigurable Logic Laboratory (801) 378-7206


Article: 2277
Subject: request for synthesizable Verilog/VHDL
From: tessier@roebling.lcs.mit.edu (Russ Tessier)
Date: 16 Nov 1995 16:02:58 GMT
Links: << >>  << T >>  << A >>


I am in need of RTL Verilog or VHDL designs that may be synthesized
with Synopsys. These designs will be used in a study of partitioning and
mapping to large FPGAs. Any designs that you could forward to me for 
use in this study would be greatly appreciated. 

Thank you

Russ Tessier
MIT Lab for Computer Science


Article: 2278
Subject: Tape
From: srivasta@cobaf.unt.edu
Date: 16 Nov 1995 16:29:44 GMT
Links: << >>  << T >>  << A >>
WHat is the diff between "CAROUSEL" and "DRUM"?




Trey



Article: 2279
Subject: Re: Tape
From: fliptron@netcom.com (Philip Freidin)
Date: Thu, 16 Nov 1995 19:24:24 GMT
Links: << >>  << T >>  << A >>
In article <48foto$ru9@hermes.acs.unt.edu>,  <srivasta@cobaf.unt.edu> wrote:
>WHat is the diff between "CAROUSEL" and "DRUM"?
>Trey


A CAROUSEL is also sometimes called a merry-go-round. it is typically
20 to 100 feet in diameter, has mock-horses and mock-unicorns and bench
seats on it, and it rotates in a horizontal plane around its center
point. On upmarket versions, the mock animals are translated verticaly
in a reciprocating manner, while the platform they are on is rotating.
The rotation is usually accompanied with some loud bad music.
People sometimes sit on the mock animals and benches while the whole
thing is rotating. go figure.

A DRUM is a "musical" instrument. It is sometimes played in conjunction
with other instruments, and sometimes by its self. For an example of
the "by-its-self", there are several good examples on various Led Zeplin
albums.

Hope this helps, and thanks for posting to comp.arch.fpga

	Philip.



Article: 2280
Subject: 2nd Global Clocks in ALTERA MAX7000E ? Help !!!
From: ido@scorpio.com (Ido Nir)
Date: Thu, 16 Nov 1995 20:41:31 GMT
Links: << >>  << T >>  << A >>
Good peoples :

I'm working with ALTERA MAX7000E device and i want to use two different clocks in my design.

How can I make the MAX+2 (version 5.3) compiler to use the two clocks as a globals clocks ?

> I tried the the global option in the logic synthesis style , but it doesn't help.
> I also try to assign the 2nd clock to the gclk2 pin, but it doesn't help.

Thanks

ido@scorpio.com




Article: 2281
Subject: Viewlogic problem
From: skk@CONSYL.cpe.ku.ac.th (Supaket Katchmart)
Date: 17 Nov 1995 00:14:31 GMT
Links: << >>  << T >>  << A >>
* In <comp.arch.fpga:AT&T VS. Xilinx>  
* Baskaran Kasimani (jothi@singnet.com.sg) wrote:

: This is the first time people find major bugs with the Viewlogic!
: Tell me more and is very interesting.

	We also found some serious  problem  with VHDLDES in Workview
Plus for Windows. It's always crash  (segmentation fault) every times 
when I use it (We used it for a year and never found the problem like 
this.  It  just happend for a month.).   I'm asking  for  a help from 
viewlogic and they are trying to find the solution now. 

	If you want more information mail me I'll send you more detail.

						Supaket K.
 


--

+--------------------------------------------
| Supaket Katchmart.
| Computer And Network System Research Lab.
| Dept. Computer Engineering. 
| Kasetsart University.
+--------------------------------------------
| E-Mail : b36skk@nontri.ku.ac.th
+--------------------------------------------


Article: 2282
Subject: Re: Industry Trends
From: ejessen@ix.netcom.com (Erik Jessen)
Date: Fri, 17 Nov 95 01:38:07 GMT
Links: << >>  << T >>  << A >>
Erich,

Here are my thoughts; they are somewhat strong...

I've used Xilinx and Altera; looking at ORCA & Altera.
We use FPGAs for prototyping; production in gate-arrays/std-cell.

- in-circuit programmability
	- a must; ZIF sockets are expensive/not available.
	- we often have multiple boards around the planet, in use by beta     
      		customers.  Emailing a new download file is much
		faster/easier than fed-exing a part.
- SRAM devices
	- doesn't matter the technology; I need:
		- fine-grained architecture (for good synthesis, and easy
		  retargetting to ASIC)
		- sea of gates (none of this "no global routing resources 
			remaining" stuff)
		- ability to create a large number (4-10) of register-files,
			FIFOs, etc. that are 4-128 words of 8-32 bits.
		- in-circuit reprogrammability
		- FAST prop. delays, at least to input latches
		- several global clocks, for power-down & multiple
		  clock domains
		- one independent tristate-control pin per output cell, so I
			 can interface to multiple different busses
- mixed voltages
	- I would like to have the IO power busses on a chip broken into 4
	sections, so that I can have 4 independent regions running at either
		 3V or 5V.  Don't forget, 2V will be here in a couple years,
		so at least start thinking about it.
- tools:
	- industrial-strength floorplanner, to shorten iteration times.
		It must be able to map HDL block names through synthesizer and 
		onto silicon layout.
	- support for LPM, so I can speed synthesis time & get optimized 
		layouts
	- back-annotated timing in HDL of your choice (VHDL/VITAL or Verilog)
- EDA vendor attitudes:
	- FPGAs are ASICs that have fast rev. ability; they require all the
		 tools that an ASIC requires.
	- turnaround time is the only reason to use an FPGA; The tools need to
		give this to the customer.  This requires the ability to
		change one block & only resynthesize it, reusing the old
		layout.  This implies upgrades to synthesizer, P&R, floor-
		planner, etc.  If an FPGA company gets their tools in
		order, they'll kill the competition, because they'll finally
		be delivering what the customer wanted.  Why do you think
		Chip Expess makes money?  Because FPGA vendors don't deliver
		in their EDA tools.

Anyway, those are my 2 cents.

Erik Jessen
Com-Solutions, Inc.
(619) 942-9790
The views expressed here are purely my own.


Article: 2283
Subject: Re: Industry Trends
From: fsoehnge@ix.netcom.com (Frank Soehnge)
Date: 17 Nov 1995 02:00:09 GMT
Links: << >>  << T >>  << A >>
In <48eb0b$muu@caesar.ultra.net> geneb@entropy.ultranet.com writes: 

>I realize you're seeking information about the direction of
>devices, but some of my major concerns regard device 
>programmers.
>Every time a new device is announced, the real questions are
>whose programmer will support it, how many iterations until
>they get the bugs out (of both the device AND the programmer),
>and how much the next "upgrade" to the so-called universal
>programmer will be.
>(This is not specific to one programmer manufacturer; it applies
>to most of them).
>Why does there seem to be a general antipathy between the device
>and programmer manufacturers?  Why so much finger-pointing when
>things go wrong?
>I'd like to see new device announcements carry the logos of the 
>programmers that are ready to handle the new parts.
>Obviously, some of the device manufacturers hate to lose the
>income from the sales of their proprietary programmers; are they
>making more on the programmers than on the parts themselves?
>
>In-circuit programming is a nice feature; just keep it simple, and the
>voltages normal. 
>SRAM-based parts can lead to chicken-egg problems in small systems
>(how do you boot the part when it's responsible for accessing the
>memory where the boot code resides?).
>
>--Gene
>

For the most part, our relationship with the device manufacturers is
pretty good. Most of them have various models of our programmers in
house and will verify that new devices that we support work like they
expect them to. Thats not to say that things don't go wrong from time
to time. I have had reports from customers that something wasn't
working correctly only to find that there was some subtle item in the
specs that I overlooked. We perform internal testing before we release
software to try and catch any bugs that may get out with new devices
but every now and then something will get overlooked. When a device can
get supported depends entirely on when we can get specs and samples of
the new device. Most of the new devices that we support come from
requests from customers who have the devices or are ready to purchase
them. When this happens, we contact the manufacturer for samples and
specs and try to get support for the device by our next release
(usually within 6 weeks). Lately I have been receiving pre-release
specs from a number of manufactures which is nice because, as you
pointed out, it's helpful to know who can program a device when the
device is made public. I don't think income from programmer sales is
really an issue for device manufacturers. It makes more sense for them
to make sure their products are supported on as many device programmers
as possible. Thanks for your response.

Erich Wagner
erich@bpmicro.com


Article: 2284
Subject: Re: BP Micro and CUPL -- a good start?
From: ddecker@usa.pipeline.com(mush)
Date: 17 Nov 1995 04:32:53 GMT
Links: << >>  << T >>  << A >>
Alan Writes .  .  .  . 
>Everyone has to start somewhere, and we're just getting into the fpga/pla 
>field as an upward migration from our usual 'pile of chips' designs.  I've

>checked out the entry level software/programmer field, and would like to
have 
>your thoughts.  I'm seriously considering a BP1148 or BP1200, and CUPL
Total 
>Designer (normally $2500, now on a 'Wescon special' for $1500).  Anyone
using 
>these or others that'd like to help me feel good about this decision, or
better 
>with another? 
 
>Cheers, 
>Alan  
 
I would emphatically recommend against CUPL for FPGAs! I've fought  
     CUPL problems through generations of the program. I finally gave up  
     and switched to Xilinx's version of ABEL. 
      
     Most of my complaints of CUPL are concerning its attempt to synthesize
 
     One-Hot state machines for Xilinx. 
     1. CUPL ties the outputs of its state machine to the package pins of  
     Xilinx, which is never what you want. There is no choice. What you  
     want is a symbol on your schematic with pins on the symbol. You use  
     these signals to control registers etc. on the schematic. If you do  
     get CUPL and want to do Xilinx state machines, I have a filter program
 
     I had to write to change all the pins to internal rather than external
 
     pins. Ask me for it. 
      
     2. One hot state machines must start with one state bit true. CUPL's  
     answer to this is to AND the not of all the state bits, and then OR  
     this into the equation for one of the state bits. For a 25 state  
     machine in 3000 series this waists 6 CLBs. I hand edit to save logic  
     when necessary. 
      
     The correct way to do this is to invert the input and output equations
 
     for one of the state flops so that one is true low. Then when Xilinx  
     sets all the flops low you are in your initial state. 
      
     3. CUPL's equations for One-Hot state machines are very wasteful. The 

     equation Q3, for instance, may have 4 or 5 ORed product terms. Each  
     one of these will include a !Q3. They want to make sure they are not  
     in Q3 before going to Q3. When resources are tight I hand edit these  
     equations to delete the unnecessary terms. 
      
     4. Any large or medium size design kills Their simulator. 
      
     5. Outputs can be persistent or transient, but all the outputs of a  
     state machine must be the same in this respect. 
      
     6. You can choose one hot or binary encoding, but all state machines  
     in the same module must be the same. 
      
     7. They have no load control. I've seen it hook 50 loads to the same  
     output. If I'm worried about speed I use ViewLogic's ViewGen to  
     generate a schematic from the state machine and then by hand split  
     these long lines using redundant logic to drive the new smaller lines.

      
     8. There's not much control of the fast vrs small trade off. I use an 

     old Exemplar program that used to ship with Xilinx's software to  
     reoptimize when necessary. 
      
     Xilinx's XABEL, a modified ABEL from DataIO, is better in many ways. 
     1. Xilinx's outputs also have no choice of internal vrs external, but 

     they give you internal which is what is most useful. 
      
     2. Xilinx's XABEL inverts one inputs and outputs of one bit to start a
 
     one hot state machine. 
      
     3. Xilinx's equations are not obviously wasteful of routing resources 

     and CLBs. 
      
     4. Xilinx has no simulator, just the old 'Give me a guess and I'll  
     tell you if you guessed right' checker. They expect you to use  
     functional and timing simulation at a higher level, which is really  
     what you want anyway. 
      
     5. Outputs can be persistent or transient on an output by output  
     basis, although the syntax is obnoxious, like CUPL's. If you declare  
     an output to be 'reg d' then its output will go true on the clock  
     leaving the state that sets it, but it will return low on the state  
     following that unless you keep setting it high. For this you use the  
     out A := 1 syntax.  
     If you want your output to be persistent and stay high until told to  
     go low many states later, then you declare the output to be type  
     reg_jk. Ah but you can't say A := 1. If you do, it will go high and  
     never go low because this sets up an equation for the J input to the  
     JK and none for the K. To make it work you have to say A.j = 1 to set 

     the out put high, and A.k = 1 to set it low. Why can't someone do this
 
     right??????? 
      
     6. With Xilinx you can choose binary, one hot, or standard coding  
     which is an attempt to find a mixture of both that is optimum. You may
 
     choose on a state machine by state machine basis. That is, if you have
 
     two state machines in the same module talking to each other, one may  
     be one hot and the other binary. 
      
     7. Xilinx with your permission will attempt to optimize the speed of  
     its outputs by using extra logic. 
      
     8. Xilinx gives you a log of choice about speed vrs size. You can  
     optimize for speed, area, or a compromise. You can also say give me  
     the best size for a maximum of N levels of logic. 
      
     I suppose CUPL is good at PALs, I don't know, but not at state  
     machines for FPGAs. For years they have been promising fixes, but  
     nothing yet. 
      
     Well, I hope this helps. There are others products. I would be very  
     interested in someone's response to these points with respect to the  
     other products. 
      
      
     Dave Decker 
     ddecker@diablores.com 
      
-- 
mush 



Article: 2285
Subject: Re: request for RTL netlists
From: jcooley@world.std.com (John Cooley)
Date: Fri, 17 Nov 1995 07:42:04 GMT
Links: << >>  << T >>  << A >>
Russ Tessier <tessier@curry.lcs.mit.edu> wrote:
>I am in need of RTL circuit descriptions in Verilog or VHDL that may be 
>synthesized by Synopsys for use in a multi-FPGA synthesis study.
>Any datapath circuits or FPGA compute applications would be especially 
>welcome. The larger the circuit the better.
>
>I have several RTL Verilog circuit descriptions to offer in trade.

Good luck, Russ, in trying to get someone else's significantly sized Verilog
or VHDL source code.  (I get asked for source code like this about once a
month.  What I've found is that engineers [or their managers] are VERY
leary about "lending" out something like this -- even if it's for academic
purposes -- because they fear that either their competitors will eventually
get it or they're losing $$$ on something they could sell.)

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3713 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 2286
Subject: NeoCAD and AT&T vs. Xilinx
From: jcooley@world.std.com (John Cooley)
Date: Fri, 17 Nov 1995 07:53:36 GMT
Links: << >>  << T >>  << A >>
Stan Hodge wrote:
> Hi.  I am currently evualuating a new FPGA technologies for our 
> next generation product.  I have looked at Xilinx and AT&T.  The
> new Xilinx software seem a bit more polished and easer to use 
> than the AT&T neo stuff.

It's no surprize.  NeoCAD was embarrassing the hell out of Xilinx in their
own P&R process so Xilinx bought NeoCAD for something like $33 or $35
million.  The great side effect of this deal is that it effectively kicked
both AT&T and Motorola in the balls because they both relied rather
heavily on NeoCAD.  AT&T was savvy enough to gets rights to NeoCAD's
source code before they signed up with them so they've had a good start
at developing their own NeoCAD-based P&R tool -- but they're still
playing catch-up.

Overall, quite a few users were rather pissed about Xilinx buying NeoCAD
because NeoCAD was the *only* general FPGA P&R tool around -- making
it purely Xilinx specific means that if users what to use Actel or Altera
or QuickLogic or Lattice or AT&T FPGA's they'd *have* to learn each
specific FPGA vendor's P&R tools.

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3713 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 2287
Subject: Re: [q][Reverse Engineering Protection]
From: jcooley@world.std.com (John Cooley)
Date: Fri, 17 Nov 1995 08:04:45 GMT
Links: << >>  << T >>  << A >>
Jyri Hamalainen <jyrih@cat.co.za> wrote:
>Does anyone here know anything about protecting ASIC's from reverse 
>engineering? OR logic camourflaging? With modern technologies such as 
>electron beam induced current imaging and Charge induced voltage 
>alteration (Scania Labs), I suppose there are no more solutions to 
>protecting ones investment?

Jyri, one clever idea for protecting designs in chips I heard of was
using Xilinx FPGA's that were programmed once at the factory with a
small battery attached after programing.  (That is, the power-up
program for the Xilinx part was NOT included in the PCB.)  What this
did was make the circuit unreversable but still functional.

I'm interested in hearing about any other ideas like this....

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3713 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 2288
Subject: Vendors For Verilog On The PC
From: jcooley@world.std.com (John Cooley)
Date: Fri, 17 Nov 1995 08:25:20 GMT
Links: << >>  << T >>  << A >>
<msgid@msg.ti.com> wrote:
>Can any one reccomend Verilog for a PC platform? (Pentium)

interHDL Inc <eli@netcom.com> wrote:
>Viper from interHDL. Contact info@interhdl.com or call (415) 428-4200


Other than Eli promoting his own company for Verilog (I can't blame a guy
for trying!) you may also want to check out:  Model Tech at (503) 641-1340;
Chronologic/ViewLogic at (800) VERILOG; Simucad at (415) 487-9700; and
Wellspring Solutions at "elliot@wellspring.com".  (These are the names
that quickly come to mind; you may want to call the Open Verilog
International office at (408) 353-8899 or e-mail "georgia@netcom.com"
for a complete list of PC and UNIX Verilog vending companies.)

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3713 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 2289
Subject: Re: Xilinx Configuration Memory Hacking
From: gratz@ite.inf.tu-dresden.de (Achim Gratz)
Date: 17 Nov 1995 12:32:03 +0100
Links: << >>  << T >>  << A >>
>>>>> "David" == David R Brooks <daveb@iinet.net.au> writes:

    >> In article <DHFC7I.9Dy@zoo.toronto.edu> henry@zoo.toronto.edu
    >> "Henry Spencer" writes:

[...]

    >> But would it not be relatively straightforward for Xilinx to
    >> add a few bytes of non-volatile public key memory (read/write)
    >> plus private key memory (write only) and implement a small
    >> decryption engine.  The configuration data rates are so low
    >> that a serial arithmetic scheme should be possible.

[...]

    David>   I seem to recall that Xilinx' whole strategy is to use a
    David> "plain vanilla" chip technology, and have their wafers made
    David> by several different subcontractors. (I understand Xilinx
    David> do not run a wafer-fab themselves). Most EPROM and similar
    David> technology is proprietary to each fab; Xilinx would then
    David> need a new design for each sub-contractor.

That might have been their strategy in the past, I really don't know.
What I know for sure is that Xilinx is currently developing a
non-volatile memory technology.




--
Achim Gratz
-+==##{([***Murphy is always right***])}##==+-
E-Mail: gratz@ite.inf.tu-dresden.de
Phone:  +49 351 4575 - 325


Article: 2290
Subject: FYI: Flash memory data recording
From: eps@apk.net (Gary Moneysmith)
Date: 17 Nov 1995 16:08:35 GMT
Links: << >>  << T >>  << A >>
Hello Everyone,

There is a new website which contains information on solid-state Flash 
memory data recording.  It's located at: http://www.apk.net/eps

Thanks...hope you find it useful.

Gary 



Article: 2291
Subject: Wanted-limited Verilog or VHDL synthesis
From: rxjf20@email.sps.mot.com (Doug Shade)
Date: 17 Nov 1995 16:46:46 GMT
Links: << >>  << T >>  << A >>
Wanted-limited Verilog or VHDL synthesis and simulation 

Are you a company or know of a company that provides an inexpensive
and/or limited Verilog or VHDL synthesis and simulation package?

The package needs to write EDIF.
 
Please contact the e-mail below.  Thanks.
Doug Shade
rxjf20@email.sps.mot.com


Article: 2292
Subject: Re: Thesis available: multi-FPGA systems
From: hauck@eecs.nwu.edu (Scott Alan Hauck)
Date: 17 Nov 1995 18:27:17 GMT
Links: << >>  << T >>  << A >>
For those who tried and failed to access my thesis with Netscape on a
Mac (or possibly a PC), the archive has been fixed.  Unfortunately,
some versions of Netscape cannot automatically uncompress and then
display a file (if anyone knows how to fix this, please let me know).
To deal with this, I've moved my archive to uncompressed files only.

Again, the URL for my thesis is http://www.eecs.nwu/edu/~hauck/thesis.

Scott

+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
|               Scott A. Hauck, Assistant Professor                         |
|  Dept. of EECS                       Voice: (708) 467-1849                |
|  Northwestern University             FAX: (708) 467-4144                  |
|  2145 Sheridan Road                  Email: hauck@eecs.nwu.edu            |
|  Evanston, IL  60208                 WWW: http://www.eecs.nwu.edu/~hauck  |
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+




Article: 2293
Subject: Re: NeoCAD and AT&T vs. Xilinx
From: peb@trsvr.tr.unisys.com (Pete Becker)
Date: Fri, 17 Nov 1995 18:54:31 GMT
Links: << >>  << T >>  << A >>
Is there any good software available for general FPGA development
as opposed to manufacturer-specific tools?

In article <DI6GLC.2wE@world.std.com>,
   jcooley@world.std.com (John Cooley) wrote:
>Stan Hodge wrote:
>> Hi.  I am currently evualuating a new FPGA technologies for our 
>> next generation product.  I have looked at Xilinx and AT&T.  The
>> new Xilinx software seem a bit more polished and easer to use 
>> than the AT&T neo stuff.
>
>It's no surprize.  NeoCAD was embarrassing the hell out of Xilinx in their
>own P&R process so Xilinx bought NeoCAD for something like $33 or $35
>million.  The great side effect of this deal is that it effectively kicked
>both AT&T and Motorola in the balls because they both relied rather
>heavily on NeoCAD.  AT&T was savvy enough to gets rights to NeoCAD's
>source code before they signed up with them so they've had a good start
>at developing their own NeoCAD-based P&R tool -- but they're still
>playing catch-up.
>
>Overall, quite a few users were rather pissed about Xilinx buying NeoCAD
>because NeoCAD was the *only* general FPGA P&R tool around -- making
>it purely Xilinx specific means that if users what to use Actel or Altera
>or QuickLogic or Lattice or AT&T FPGA's they'd *have* to learn each
>specific FPGA vendor's P&R tools.
>
>                           - John Cooley
>                             Part Time EDA Consumer Advocate
>                             Full Time ASIC, FPGA & EDA Design Consultant
>
>===========================================================================
> Trapped trying to figure out a Synopsys bug?  Want to hear how 3713 other
> users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
> 
>      !!!     "It's not a BUG,               jcooley@world.std.com
>     /o o\  /  it's a FEATURE!"                 (508) 429-4357
>    (  >  )
>     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
>     _] [_         Verilog, VHDL and numerous Design Methodologies.
>
>     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
>   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 2294
Subject: Re: 2nd Global Clocks in ALTERA MAX7000E ? Help !!!
From: pss1@hopper.unh.edu (Paul S Secinaro)
Date: 17 Nov 1995 19:02:54 GMT
Links: << >>  << T >>  << A >>
ido@scorpio.com (Ido Nir) writes:

>Good peoples :

>I'm working with ALTERA MAX7000E device and i want to use two different clocks in my design.

>How can I make the MAX+2 (version 5.3) compiler to use the two clocks as a globals clocks ?

Are you working in AHDL, VHDL, or schematic capture?  If AHDL, then
just use the GLOBAL primitive in all your clock assignments.  I'm not
sure how to do it with the other design entry methods.  Assuming your
two clock inputs are named gclk1 and gclk2, this would look like, for
example:

MyFlipFlop1.clk = GLOBAL(gclk1);
MyFlipFlop2.clk = GLOBAL(gclk2);

etc.




-- 
Paul Secinaro (pss1@christa.unh.edu)
Synthetic Vision and Pattern Analysis Laboratory
UNH Dept. of Electrical and Computer Engineering


Article: 2295
Subject: Re: Any user experiences with Exemplar VHDL synthesis for FPGA
From: ejessen@ix.netcom.com (Erik Jessen)
Date: Fri, 17 Nov 95 19:22:49 GMT
Links: << >>  << T >>  << A >>
In article <DI55xA.15x@nntpa.cb.att.com>,
   ramesh@montero.wh.att.com (-N.RAMESH) wrote:
>Hello:
>
>I would like to hear from anyone who has used the Exemplar tools to
>design FPGAs (especially the AT&T ORCA 2C devices).  We are trying to
>make a decision on the right tools for ORCA and any input would be
>appreciated.

Ramesh,

We used Exemplar for several Xilinx and Altera designs, and were quite
happy with it.  We didn't do any Orca designs, but the Orca and Xilinx
are pretty similar, so the synthesizer should give good results.

At one time, Exemplar didn't output FAN files, but that was solved a number
of months ago, so it shouldn't be an issue.

If you're doing large designs, something that I would look into is the
ability to floorplan the FPGA, using the logical hierarchy.  This will
make it easy later, to modify a single block, resynthesize just that block,
and then do only an incremental P&R.

Hope this helps,

Erik Jessen
Com-Solutions, Inc.
(619) 942-9790
The views expressed here are purely my own.


Article: 2296
Subject: Re: NeoCAD and AT&T vs. Xilinx
From: ejessen@ix.netcom.com (Erik Jessen)
Date: Fri, 17 Nov 95 19:28:53 GMT
Links: << >>  << T >>  << A >>
Stan,

As a followup message: regardless of whose tools you pick, I would be very
careful with Xilinx silicon.  The larger devices can only have 30-40% of their
total gatecount used, before they run out of routing resources.  This number
is based on talking to a number of users.  I haven't heard any such complaint
about ORCA.  All the designers I've talked to, seem to say that it (or Altera)
are definitely the hot ticket.

Also: From what I could tell, the reason Xilinx got hammered by NeoCAD was
twofold:
	a) They wrote very buggy software
	b) They never rewrote their software and made it clean; they just
		tried to hack at it.

Both of the above indicate a management that doesn't fundamentally understand
software management.  I would have a concern that, however good the ex-NeoCAD 
programmers are, they will be pushed into shipping stuff that isn't up to 
snuff.

Also, ATT has hired away a number of ex-NeoCAD programmers, so I would expect 
the software to come up to speed.  ATT has lots of experience managing 
software, and has a complete set of internal EDA tools (which aren't too bad, 
by the way).

Summary: in the long run, I think ATT will be better; the Silicon is 
definitely better now, and I think the software will be equal/better.

Just my opinions, as usual.


Erik Jessen
Com-Solutions, Inc.
(619) 942-9790
The views expressed here are purely my own.


Article: 2297
Subject: Re: request for RTL netlists
From: ejessen@ix.netcom.com (Erik Jessen)
Date: Fri, 17 Nov 95 19:30:50 GMT
Links: << >>  << T >>  << A >>
Russ,

I would like to recommend that you check out the various VHDL source-code 
repositories (in Germany, UCI, U-Va, etc.)  There should be something pretty 
good there.

Also, since we keep seeing universities have this problem, I've suggested to a 
few people I know, that one university set up a program to implement some 
large devices (CPUs, DSP-type functions) as test-cases for everyone.

Regards,

Erik Jessen
Com-Solutions, Inc.
(619) 942-9790
The views expressed here are purely my own.


Article: 2298
Subject: Re: Wanted-limited Verilog or VHDL synthesis
From: ejessen@ix.netcom.com (Erik Jessen)
Date: Fri, 17 Nov 95 19:31:52 GMT
Links: << >>  << T >>  << A >>
You might try buying a subset of the Altera tools; they have a synthesizer, 
and they write EDIF 300 (though it will be in their cell library, obviously).

Regards,

Erik Jessen
Com-Solutions, Inc.
(619) 942-9790
The views expressed here are purely my own.


Article: 2299
Subject: Re: [Q] FPGA Software for Linux
From: jackg@downhaul.crc.ricoh.com (Jack Greenbaum)
Date: 17 Nov 1995 19:35:16 GMT
Links: << >>  << T >>  << A >>
In article <1995Nov16.081949@timp.ee.byu.edu> wirthlim@timp.ee.byu.edu (Michael J. Wirthlin) writes:
   As far as I
   am aware, the manufacturer place and route tools are only available on 
   standard operating system platforms.

Linux is a POSIX.1 compliant operating system. X11R6 is provided with
most Linux distributions. Linux IS a standard operating system.


--
Jack Greenbaum -- Research Engineer, Ricoh California Research Center
---------------------------------------------------------------------
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---------------------------------------------------------------------
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         (415) 854-8740 fax    |  Menlo Park, CA 94025-7002
---------------------------------------------------------------------
-- 
Jack Greenbaum -- Research Engineer, Ricoh California Research Center
---------------------------------------------------------------------
Digital: jackg@crc.ricoh.com   |  http://www.crc.ricoh.com/~jackg
---------------------------------------------------------------------




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