Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 1750

Article: 1750
Subject: Quicklogic/Cypress/Warp3
From: kirani@cinenet.net (kayvon irani)
Date: 25 Aug 1995 01:40:38 GMT
Links: << >>  << T >>  << A >>
	Hi Mark:

	The p-ASIC parts from Cypress and Quicklogic are the same; actually,

	since quicklogic is fabless they are all manufactured at Cypress. 

	The parts were originally designed at Quicklogic. As far as the tools

	you can buy the tool either through Cypress or Quicklogic. Each one

	will sell you a different tool; the place and route is the same tool

	but synthesis is different; Cypress has its developped its own 

	synthesis tool but Quicklogic uses Synplicity synthesis engine. The

	prices will vary from $1000-4000. Hope this answered your question.

	Regards
	Kayvon Irani
	H/W Design Engineer
	kirani@hollywood.cinenet.net
	


Article: 1751
Subject: For Sale: Chronology Package...
From: jfmaher@aol.com (JFMAHER)
Date: 24 Aug 1995 23:15:08 -0400
Links: << >>  << T >>  << A >>
I have a personal copy of Chronology Docutime for sale.  My company
finally bought Timing Designer Professional so I no longer need it.  I
have version 1.5.  Maintenance can be renewed for $99.  I paid $450 for
the package.  I would like to get $250 for it.  I have all manuals, disks,
etc.

John maher
jfmaher@aol.com


Article: 1752
Subject: Re: Quicklogic/Cypress/Warp3
From: msojones@cix.compulink.co.uk ("Michael Jones")
Date: Fri, 25 Aug 1995 14:36:13 GMT
Links: << >>  << T >>  << A >>
We are using the Quicklogic/Cypress FPGAS

They are compatible.
We have the Quicklogic 75UKP Eval Kit wich imports Verilog 
So you could use Verilog instead.
This is what we are doing;and we debuged our
design using the Veriwell Verilog simulator which is
free for up to 1000 lines.

We also have the WARP Eval S/W from Pronto.
This imports a reasonable subset of VHDL,but it will
only do PALs.

The full Warp3 package is about 3K because they
include all of the Viewlogic 'graphical stuff'
-- which we dont realy want!

If you want to save money The Warp2 Plus is 650UKP 
It includes the fitter for the FPGAS but you
do not get a simulator! 

The 'Impulse' programmer is 1-2K I think!
Abacus or Pronto may loan you a programmer.(with strings)
Abacus will program devices for you on a quick turn-round.

We are sticking with the Quicklogic tool for now.
BTW Cypress chips are cheaper,but have longer lead times.


Mike Jones, Digital Dexterity Ltd.


Article: 1753
Subject: Re: Synario/OrCad/Viewlogic
From: mikelot@ix.netcom.com (mike lottridge)
Date: Fri, 25 Aug 1995 15:44:33 GMT
Links: << >>  << T >>  << A >>
Any users of SusieCad/ActiveCad out there? They seem to have an
interesting product that supports schematic capture + VHDL synthesis,
but I'd like to hear from someone who actually has experience in
dealing with this product before making any committments...




Article: 1754
Subject: Re: Synario/OrCad/Viewlogic
From: brenes@c2t.com (Erasmo Brenes)
Date: Fri, 25 Aug 1995 18:36:35 GMT
Links: << >>  << T >>  << A >>
In article <41i726$efv@ixnews6.ix.netcom.com> mikelot@ix.netcom.com (mike lottridge) writes:
>
>
>rxjf20@email.sps.mot.com (Doug Shade) wrote:
>
>>In article <41debk$86c@ixnews5.ix.netcom.com>
>>mikelot@ix.netcom.com (mike lottridge) writes:
>
>>> if you've used any of the above three tools, I'd appreciate some pro's
>>> and con's on what you found...
>
>>Depends on what you want to do.  Perhaps you can let us know the type
>>of things you want to do....
>
>sorry -- that was a bit vague! i'm looking for tools for cpld/fpga
>design that support a mix of schematic entry + vhdl
>

I don't know about OrCad, but I evaluated the Synario tools vs the Viewlogic,
and ended up picking Synario. In terms of the schematic entry, both have
their pros and cons, with Viewlogic having the bigger support for PCB
systems. In our case, we needed to interface with Allegro and the Viewlogic
system already had it, while with Synario we needed to use a third party
filter (with additional $$ ).

In spite of that, I selected Synario due to its far better performance
in terms of synthesizing VHDL code into ALTERA FPGAs. With Viewlogic, I
would have to modify my Synopsys-based VHDL code significantly, and then
get a synthesized part which was considerably slower than with Synario.
As for Synario, only adding the DATAIO library header was the usual
changes to the source code.

The main difference in the synthesis results arose from their approach,
that is, Synario tools generate a file which is TDF format, ie. ALTERA
AHDL format, and thus allows ALTERA tools to fully optimize the placement
and routing of the part, while with Viewlogic, the result is an EDIF
file format which ALTERA doesn't optimize, only places. Thus you rely
on Viewlogic's optimization with regard to the ALTERA parts. It is obvious
that ALTERA ought to know how to do this job better than Viewlogic. The
same applies for the Lattice parts.

As for AMD MACH parts, Synario needs to be constrained otherwise it likes
to pick a part which is bigger than needed. Overall, the AMD MACH synthesis
was not what I would've liked, but then it wasn't either from Viewlogic.

I haven't tried the Xilinx parts with either tools, so I couldn't comment
on either tool synthesis capabilities. In regard to the generic pals, the
Synario VHDL wants you to add special attributes forcing the pinout, etc.
which makes the code non-portable (our simulation is done in VSS) without
modifications. Then again, I rarely use the small parts any more, so the
pain is tolerable (at least so far :-)).

Hope this gives you some insight into these tools

Erasmo.



Article: 1755
Subject: AMD MACH eval package ?
From: moby@kcbbs.gen.nz (Mike Diack)
Date: 26 Aug 95 01:04:23 GMT
Links: << >>  << T >>  << A >>
I beleive AMD do a limited device list compiler for their
MACH devices for a reasonable price (i think it only does
MACH210 variants). Does anyone know the order code for
this package ?
cheers
Mike


Article: 1756
Subject: Re: AMD MACH eval package ?
From: kugel@mp-sun6informatik.uni-mannheim.de (Andreas Kugel)
Date: 28 Aug 1995 07:41:04 GMT
Links: << >>  << T >>  << A >>
get the amd package from ftp://ftp.ix.de/pub/elrad/060
there is palasm and mach-xl



--------------------------------------------------------
Andreas Kugel                
Chair of Computer Science V       Phone:(49)621-292-5755
University of Mannheim            Fax:(49)621-292-5756
A5
D-68131 Mannheim
Germany
e-mail:kugel@mp-sun1.informatik.uni-mannheim.de
--------------------------------------------------------


Article: 1757
Subject: Help On Fujitsu Gate Arrays
From: mkh@sn2.ee.umist.ac.uk (VLSI)
Date: 28 Aug 1995 09:36:32 GMT
Links: << >>  << T >>  << A >>
Please could somenone give me some information on Fujitsu Gate array technology
with reference to its programming as well as tools that are used synthesise
designs from VHDL/Verilog to Layout.

Thank you in advance.


Article: 1758
Subject: Help Needed-Technical Marketing Eng.FPGA-Allantown,Pa.-Recruiter
From: amaraju@onramp.net (eddie amara)
Date: Mon, 28 Aug 1995 10:01:27 -0500
Links: << >>  << T >>  << A >>
                                 FORTUNE 100

Technical Marketing Engineering position in the FPGA product family in the
areas of strategic marketing and product development.  Will participate in
FPGA activities  including the identification of target applications in
response to customer input. Perform the FPGA implementation and
corresponding documentation for the target applications.
Publish/participate in application notes,product briefs,data sheets and
other documentation.

Job Requirements-Solid understanding of system logic design using
programmable logic,FPGAs,schematic capture tools, FPGA place/route
tools,and logic synthesis. Good interpersonal communication and writing
skills. 

At least 3 years of system and/or logic design experience. 3 years
experience with popular FPGA products such as Xilinx,Altera,Actel or
Quicklogic devices.

Education-BSEE or BSCS 

Salary-50 to 70K + 12% Bonus

Location-Allentown,Pa.

-- 
Eddie Amara
SpencerSearch,Inc.
Voice 214-931-3060
Fax   214-931-8471
amaraju@onramp.net


Article: 1759
Subject: Help Needed-FPGA Product Engineer-Allentown,Pa.-Recruiter
From: amaraju@onramp.net (eddie amara)
Date: Mon, 28 Aug 1995 10:01:41 -0500
Links: << >>  << T >>  << A >>
                              FORTUNE 100

Product Engineering position in FPGA product family supporting 3rd party
CAE design kits.

Responsibilities include development, integration, testing, delivery,
documentation, and support of FPGA Product family. Opening are in Synopsys
and Cadence/Verilog.

Experience in schematic capture,functional and timing simulation, and
synthesis. Knowledge of netlist formats,simulation modeling, and awk/perl.
FPGA design experience desirable.  Strong technical,interpersonal
communication, and writing skills. At least 3 years experience.

Education-BS or MSEE or CS

Salary-50 to 70K + 12% Bonus

Location-Allentown,Pa.

-- 
Eddie Amara
SpencerSearch,Inc.
Voice 214-931-3060
Fax   214-931-8471
amaraju@onramp.net


Article: 1760
Subject: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
From: amaraju@onramp.net (eddie amara)
Date: Mon, 28 Aug 1995 10:08:52 -0500
Links: << >>  << T >>  << A >>
                        Prestigious Research Labs!!!!

Join one of the fastest growing divisions of this Fortune 50 Corp. FPGA !!!!!

FPGA Applications Engineer-Owns the complete implementation of the
design.Supports the FAE and ultimately responsible for having the design
work in the customers system.

Other resposibilities-Customer design win support.
                      Support customers and FAE with problem designs
                      Contribute to regional tag teams
                      Periodically visit customer base
                      Act as a Hardware or CAD platform champion
                      Customer and FAE training   
                      Apps notes  
                      Documentation

Skills/Exp-System logic design 
           Programmable logic
           FPGAs
           Schematic capture tools
           FPGA place and route tools
           Good communication and writing skills

Education-BS or MS in EE or CS and 5 years of system and or logic design
will be considered.      

Salary-$50 to $70 +12% bonus

Location--Allentown,Pa.


no new grads or those withonly university work,thanks.

-- 
Eddie Amara
SpencerSearch,Inc.
Voice 214-931-3060
Fax   214-931-8471
amaraju@onramp.net


Article: 1761
Subject: Need Help-FPGA Dev/Des.Eng.
From: amaraju@onramp.net (eddie amara)
Date: Mon, 28 Aug 1995 10:09:47 -0500
Links: << >>  << T >>  << A >>
      

FPGA Development Engineer

Responsibilities:Development of FPGA architecture and of the integrated
circuits that implement the architecture.Specific resposibilities include
working with FPGA software developers to ensure that the architecture can
be effectively exploited by the software and working with the marketing
organization to understand the needs of the customers.

Skills/Exp.:Understand the FPGA architecture trade-off.Good understanding
of full custom circuit design,System knowledge and logic design.

Education:PhD/MS in EE/CS/Physics and at least 3 years exp.

Location:Allentown,PA.

Salary:$50 to $80K + 12% bonus

NO NEW GRADS OR THOSE WITH ONLY UNIVERSITY WORK EXPERIENCE,THANKS.

-- 
Eddie Amara
SpencerSearch,Inc.
Voice 214-931-3060
Fax   214-931-8471
amaraju@onramp.net


Article: 1762
Subject: Help Needed-Technical Marketing Eng.FPGA-Allantown,Pa.-Recruiter
From: amaraju@onramp.net (eddie amara)
Date: Mon, 28 Aug 1995 10:11:49 -0500
Links: << >>  << T >>  << A >>
                                 FORTUNE 100

Technical Marketing Engineering position in the FPGA product family in the
areas of strategic marketing and product development.  Will participate in
FPGA activities  including the identification of target applications in
response to customer input. Perform the FPGA implementation and
corresponding documentation for the target applications.
Publish/participate in application notes,product briefs,data sheets and
other documentation.

Job Requirements-Solid understanding of system logic design using
programmable logic,FPGAs,schematic capture tools, FPGA place/route
tools,and logic synthesis. Good interpersonal communication and writing
skills. 

At least 3 years of system and/or logic design experience. 3 years
experience with popular FPGA products such as Xilinx,Altera,Actel or
Quicklogic devices.

Education-BSEE or BSCS 

Salary-50 to 70K + 12% Bonus

Location-Allentown,Pa.

-- 
Eddie Amara
SpencerSearch,Inc.
Voice 214-931-3060
Fax   214-931-8471
amaraju@onramp.net


Article: 1763
Subject: Additional Customer Support
From: support@viewlogic.de (Support Viewlogic Systems GmbH)
Date: 28 Aug 1995 15:46:20 GMT
Links: << >>  << T >>  << A >>
Hello all,

Viewlogic Systems GmbH in Germany is looking for a german/english speaking
customer support engineer located in Munich.
E. Engineering degree is required as well as excellent communication skills.
The product range will be of all thinkable tools in the frontend range from Viewlogic
including :
Schematic entry, statechart entry, VHDL/Verilog entry,
Simulation, Timing verification, Test generation, 
Analog design, Analog simulation, 
Synthesis, PCB-Interfacing, FPGA/ASIC Designing.

This interesting wide range will be paid accordingly to knowledge.

For inquiries please email to:  support@viewlogic.de








Article: 1764
Subject: Actel PCI App Note
From: lynnwest@netcom.com (Lynn West)
Date: Mon, 28 Aug 1995 22:58:20 GMT
Links: << >>  << T >>  << A >>
I have been told that Actel has produced an app note describing a
method for implementing a PCI interface using their FPGAs, but cannot
confirm the report, and my calls to Actel are so far unanswered.
Anyone know of such an app note?

Lynn West


Article: 1765
Subject: Re: Actel PCI App Note
From: scott@momus.gordian.com (Scott Murphy)
Date: Mon, 28 Aug 1995 23:59:42 GMT
Links: << >>  << T >>  << A >>
check out the following:

PCI to Generic Memory Bus Bridge.

It starts on page 9-37 of the 1995 FPGA data 
book and design guide.

--
__________________________________________________
|                                                |
|	homebrew is the elixir of the gods       |
|                                                |
--------------------------------------------------


Article: 1766
Subject: Re: Actel PCI App Note
From: Rainer Malzbender <rainer@displaytech.com>
Date: 29 Aug 1995 04:05:19 GMT
Links: << >>  << T >>  << A >>

lynnwest@netcom.com (Lynn West) wrote:
>I have been told that Actel has produced an app note describing a
>method for implementing a PCI interface using their FPGAs, but cannot
>confirm the report, and my calls to Actel are so far unanswered.
>Anyone know of such an app note?
>
>Lynn West

No, but Xilinx has one :-)

http://www.xilinx.com

--
Rainer M. Malzbender                                  Senior Research Physicist
rainer@displaytech.com                                        Displaytech, Inc.
303.449.8933                                2200 Central Ave. Boulder, CO 80301




Article: 1767
Subject: Re: AMD MACH eval package ?
From: msojones@cix.compulink.co.uk ("Michael Jones")
Date: Tue, 29 Aug 1995 13:19:16 GMT
Links: << >>  << T >>  << A >>
What limits are there on this MACH-XL EVAL?


Mike Jones, Digital Dexterity.
 


Article: 1768
Subject: Research positions available: parallel architectures
From: eugen@research.nj.nec.com@research.nj.nec.com (Eugen Schenfeld)
Date: 29 Aug 1995 10:30:55 -0400
Links: << >>  << T >>  << A >>

\documentstyle[fullpage]{letter}

\begin{document}

\centerline{\large \bf RESEARCH POSITION AVAILABLE}

\centerline{\bf August 9, 1995}

The NEC Research Institute of Princeton, NJ is seeking candidates for
research positions in the area of Parallel Processing Architectures. Of 
particular interest are candidates who have a broad architecture view, who 
have a new vision for future original architectures and who are able to 
purse an independent research program, including the establishing of a lab 
and prototype construction to demonstrate new ideas. Original proposals for 
parallel architectures, addressing some of the following issues, are 
required:

\begin{itemize}

\item CPU architectures for parallel processing.
\item Parallel interconnection networks and switching elements.
\item Aspects of routing VLSI implementation for parallel processing networks,
\item Trends of future technologies (optical interconnections, VLSI, memory) 
and their impact on new parallel architectures.
\item Parallel programming environments (e.g., PCN, PVM).
\item Parallel programming languages (e.g., HPF).
\item Parallel applications and their match with architectures.
\item Parallel OS (e.g., Micro-Kernels, Nano-Kernels).

\end{itemize}

The emphasis is on a broad view, not on a narrow, limited research program.
The successful candidate should have a working experience in hardware
(building prototypes, VLSI design, high speed electronics), and not only
deal with the theoretical aspects of parallel processing (e.g. simulations,
theorem proving).


The NEC Research Institute, founded in 1988, conducts long-term basic
research in the sciences underlining future technologies of computers
and communications (C\&C). The goal of the Institute is to make
fundamental contributions to the computing and physical sciences basic
to the processing and interpretation of information. The Institute's
parent company is NEC Corporation, a global leader in computers,
communications, electronics and information services. On May 2, 1990,
the NEC Research Institute dedicated its \$ 30 million new facilities on
a twenty-one acre site in the Princeton area. This region was selected
because of its tradition of basic research and invention.
The Institute supports the belief that research results should be
available in the open literature and therefore emulates the liberal
publication policies of universities. Scientists at the NEC Research
Institute seek to expand the base of scientific knowledge and enhance
mutual understanding among the people of all nations. 


Candidates should have a {\bf recent research activity} demonstrating their
role in the above topics and have a {\bf lab. working experience} with 
instrumentation and measurement equipment. A Ph.D. degree (or a very near 
completion of one) in Computer Science, Computer Engineering or Electrical 
Engineering is needed for this position.   


NEC Research Institute is an equal opportunity employer.
Applicants must show documentation of eligibility for employment. 
Interested applicants are kindly invited to send their resumes, few recent
papers and arrange for three letters of refferences to be sent {\bf directlly} to:

\centerline{Dr. Eugen Schenfeld}
\centerline{NEC Research Institute}
\centerline{4 Independence Way}
\centerline{Princeton, NJ 08540}
\centerline{Phone: 609-951-2742}
\centerline{fax: 609-951-2482}
\centerline{email: eugen@research.nj.nec.com}



\end{document}





Article: 1769
Subject: ATLANTA, DIGITAL DESIGN ENGINEER
From: psiinc@mcs.com (psiinc)
Date: 29 Aug 1995 17:55:21 GMT
Links: << >>  << T >>  << A >>
ATLANTA, DIGITAL DESIGN ENGINEER

Our client is a world leader in satellite-based communication networks.  They are 
developing state-of the-art Modulators and Receivers for the digital video 
revolution.

As an experienced Digital Design Engineer, in a group lead position, you will be 
responsible for design specification, conceptualization and implementation.  To 
qualify, you must have a BSEE and a minimum 5 years and/or MEE and a minimum of 3 
years directly relates experience with the following skills set:  High frequency 
CMOS and ECL designs over 50 MHz , hardware development with PLDs and FPGAs.
MPEG video and DVB spec familiarity is a definite plus.

Please send resume with compensation history to email psiinc@mcs.com or fax 708 
679-8092.
Attn: Trey.



Article: 1770
Subject: Any FPGA FAQ?
From: mikeh@ssd.fsi.com (Michael Hann)
Date: Tue, 29 Aug 1995 19:25:19 GMT
Links: << >>  << T >>  << A >>

Is there a FAQ or other overview source on FPGA stuff?

-- 
-----------------------------------------------------------------------
"There are no misfortunes from which the adroit cannot take some
profit and no boon from which the imprudent cannot take some harm."
	- LaRochefoucauld

	mikeh@ssd.fsi.com
-----------------------------------------------------------------------


Article: 1771
Subject: Re: Any FPGA FAQ?
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 29 Aug 1995 20:55:56 GMT
Links: << >>  << T >>  << A >>
mikeh@ssd.fsi.com (Michael Hann) writes:
>
>Is there a FAQ or other overview source on FPGA stuff?

http://www.super.org:8000/FPGA/caf.html


---
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's




Article: 1772
Subject: Re: AMD MACH eval package ?
From: msojones@cix.compulink.co.uk ("Michael Jones")
Date: Tue, 29 Aug 1995 23:42:37 GMT
Links: << >>  << T >>  << A >>
> get the amd package from ftp://ftp.ix.de/pub/elrad/060
> there is palasm and mach-xl
I tried to get it but anon ftp permission denied!
Is there anywhere else I can get these from?



Article: 1773
Subject: Re: AMD MACH eval package ?
From: bon@elektron.ikp.physik.th-darmstadt.de (Uwe Bonnes)
Date: 30 Aug 1995 07:27:48 GMT
Links: << >>  << T >>  << A >>
Michael Jones (msojones@cix.compulink.co.uk) wrote:
: > get the amd package from ftp://ftp.ix.de/pub/elrad/060
: > there is palasm and mach-xl
: I tried to get it but anon ftp permission denied!
: Is there anywhere else I can get these from?
: 
Try it again, they have an access limmit during business-hours of 3 or 5
sessions. 
-- 
Uwe Bonnes                bon@elektron.ikp.physik.th-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------


Article: 1774
Subject: Re: AMD MACH eval package ?
From: Andreas Kugel <kugel>
Date: 30 Aug 1995 07:28:33 GMT
Links: << >>  << T >>  << A >>
msojones@cix.compulink.co.uk ("Michael Jones") wrote:
>> get the amd package from ftp://ftp.ix.de/pub/elrad/060
>> there is palasm and mach-xl
>I tried to get it but anon ftp permission denied!
>Is there anywhere else I can get these from?
>

I just tried it again and the files are available.
There might be access restrictions during some
hours of day/night.
Maybe try with manual login as anonymous and
password


-- 


--------------------------------------------------------
Andreas Kugel                
Chair of Computer Science V       Phone:(49)621-292-5755
University of Mannheim            Fax:(49)621-292-5756
A5
D-68131 Mannheim
Germany
e-mail:kugel@mp-sun1.informatik.uni-mannheim.de
--------------------------------------------------------





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search