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Messages from 1925

Article: 1925
Subject: Re: Anyone using Altera 8820A ?
From: Ralph Watson <rwwatson@ti.com>
Date: 20 Sep 1995 15:18:22 GMT
Links: << >>  << T >>  << A >>
Howdy, I am using a Altera 81188 in one of my designs. I was able to acheive 
downloading of the data via a serial interface to a microprocessor. 

There were several things that I found out. 

1) The pullup resistors are critical for proper operation. They are listed
   in the Altera FLEX 8000 guide. I kept forgetting these pullups.

2) Approx. 11 extra clock cycles were needed after the data was loaded 
   into the FPGA before the device became functional. One would think that
   the Bit Blaster does this for you. 

3). you can look at the validity of your data to the FPGA by examining 
    the nSTATUS signal. Originally I had the data in the wrong format 
    so it was being downloaded wrong into the FPGA. This signal gave me 
    a clue as to what was wrong. 

Hope this helps 

   Ralph Watson 
   rwwatson@ti.com



Article: 1926
Subject: Re: Fast FPGA's?
From: randraka@ids.net
Date: Wed, 20 Sep 95 20:28:50 +500
Links: << >>  << T >>  << A >>
In Article <michaelk.1161931222A@news.mcgill.ca>

lines deleted

>Could someone refer me to some references or sites where I can get info
>on what LFSR counters are?  I'm building a system using the Xilinx 4000
>series that requires fast FSM's and this would help a lot.  Also, would
>there be any sites that contain VHDL code for these counters?  Thanks
>in advance.
>
LFSR counters are Linear Feedback Shift Register COunters, also known as psuedo
random number generators because of the apparently random sequence they
generate.  The sequence is really predictable and repeatable.  The counters are
constructed by either XOR or XNOR combining selected taps off the shift
register and feeding the result back to the input.  The sequence goes through
(2^n)-1 states before repeating where n is the number of registers in the shift
register.  The result is a physically small counter with very little 
combinatorial logic that can run close to the ff toggle rate if laid out right.

Xilinx has an app note for these counters on page 9-24 of the 1994 third
edition data book. I think there are additional app notes on their web page.
The data book app note includes a table showing the correct taps for
counters up to 40 bits.  You must use the correct taps to get a maximal length
sequence.  Counts other than the maximal length are easiest to obtain by 
decoding the desired state(s).  Since the count sequence is a little fruity,
you will need to determine the state for a particular count.  That's easy to do
by hand for the smaller counters.  A simple program can be used to generate the
longer sequences or even the state at a particular count.  The four and five
bit counters are particularly useful in combination with state machines, as
they can be decoded in one level in a xilinx 3K.  System speed can be
maintained by pipelining the decode.  

See, you learn something new everyday!  Best of luck.
 
-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930    FAX 401/884-7950
email randraka@ids.net
 
The Andraka Consulting Group is a digital hardware design firm specializing in
obtaining the maximum performance from FPGAs.  Services include complete
design, development, simulation, and integration of these devices and the
surrounding circuits.  We also evaluate, troubleshoot, and improve existing
designs.  Please call or write for a free brochure.




Article: 1927
Subject: Re: Fast FPGA's?
From: Rainer Malzbender <rainer@displaytech.com>
Date: 20 Sep 1995 18:15:44 GMT
Links: << >>  << T >>  << A >>
I implemented a simple VRAM control signal state machine in a 4003-6 the
other day, and just for grins started swapping crystals to see how fast
it would run. It ran up to 107 Mhz, at which point I ran out of crystals.
Verifying operation consisted of looking at signals with a logic analyzer.
The "state machine" is a shift register with decoded outputs, but as a
relative FPGA newbie I was very surprised.

--
Rainer M. Malzbender                                  Senior Research Physicist
rainer@displaytech.com                                        Displaytech, Inc.
303.449.8933                                2200 Central Ave. Boulder, CO 80301




Article: 1928
Subject: Re: ATMEL WWW site?
From: dsmith@thor.ece.uc.edu (Doug Smith)
Date: 20 Sep 1995 18:36:43 GMT
Links: << >>  << T >>  << A >>
Take a look at "http://memec.com/DataSheets/Atmel/Prodg/prodg.toc.html".


Scott Evans (chan_isd@ix.netcom.com) wrote:
: In article <dimitris-1109951303030001@thor.engn.uwindsor.ca>,
:    dimitris@engn.uwindsor.ca (Dimitris Phoukas) wrote:
: >Does anybody if ATMEL has a WWW server?
: >Thanks in advance
: >
: There is not one yet (it's in the works).
: Meanwhile they can be contacted at
: e-mail: fpga@atmel.com
: phone: 408 436 4119
: Scott Evans

--
---
Doug Smith			University of Cincinnati
dsmith@ece.uc.edu		Electrical & Computer Engineering

"Fear God, and keep his commandments: for this is the whole duty of man."
  		-King Solomon
---


Article: 1929
Subject: Custom Integrated Circuits Conference -- Call for Papers
From: brian@uivlsist.csl.uiuc.edu (Brian Antao)
Date: 20 Sep 1995 22:18:49 GMT
Links: << >>  << T >>  << A >>
The web site for CICC for more info is:

	http://uivlsi.csl.uiuc.edu/~brian/cicc.html


=======================================================================
			   CALL FOR PAPERS

            IEEE Custom Integrated Circuits Conference

				      .... the leading edge of ICs


		     San Diego, CA
                    May 5 - 8 ,1996
==========================================================================

CICC is the premier conference devoted to IC development.  It provides a
forum for circuit designers, CAD developers, manufacturers and ASIC users 
to present and discuss exciting new developments, future trends and innovative 
ideas. It provides an unique platform and an opportunity for the CAD
developers and the designers to interact and exchange ideas for developing
leading edge CAD solutions to the many design problems.
CICC is sponsored by the IEEE Electron Devices Society in cooperation with
the IEEE Solid State Circuits Council.

CONFERENCE HIGHLIGHTS                                                      

Technical Papers:  The focal point of CICC: approximately 140 papers addressing 
a broad range of leading-edge circuits, applications, design techniques and 
tools will be presented.  Instructions for potential contributors are given 
below.

Panels:  Discussions and debates by industry leaders on key issues, problems,
solutions and potentials of the IC industry.

Educational Sessions: A full day of extended tutorials offer a unique and 
valuable opportunity for practicing professionals to get acquainted with 
aspects of ASIC development outside of their specialties.

Exhibits/Exhibit or Sessions: CICC includes extensive exhibits by ASIC, EDA and
test/measurement vendors.  Exhibitors are also invited to give presentations on 
new products and capabilities in special exhibitor sessions.  

Contact the Exhibits Chairman for details.

SUBMISSION OF PAPERS                                                       

Deadline December 6, 1995 Prospective authors must submit CAMERA-READY papers, 
up to four pages in length inclusive of all illustrations, charts and tables.  
Those interested in submitting papers should contact the Conference Manager as 
early as possible to obtain an author's kit and detailed instructions.  

The address is:
Melissa Widerkehr, 
CICC, 101 Lakeforest Boulevard, 
Suite 270, Gaithersburg,
MD, 20877, 
Telephone: (301)-527-0902, 
Fax: (301)-527-0994.
Email: Widerkehr@aol.com

ACCEPTED PAPERS WILL BE PRINTED IN THE PROCEEDINGS WITHOUT OPPORTUNITY FOR
FURTHER CHANGE.  
The paper should report original and previously unpublished work, including 
specific results.  Circuit oriented work must include measured experimental 
results.  

Deadline for RECEIPT of technical papers is December 6, 1995.  

Appropriate company and government clearances MUST be obtained prior to 
submission.  After receipt of the author kit, the completed original and 25 
copies should be sent to the Conference Manager at the address above.  
Authors of accepted papers will be notified by mail by January 31, 1996.

PAPERS IN THE FOLLOWING AREAS ARE REQUESTED:                               

Analog and Mixed-Signal Circuits and Systems: 
    Data convertors, modulators, filters, high speed analog, low voltage 
    techniques. Mixed analog-digital IC applications, disk read/write channels, 
    RAMDACS.

Digital Signal Processing: Image compression, recognition, and enhancement 
    particularly for digital video.  Voice coding and recognition.  Specialized 
    processing function architectures.  Digital filtering, encryption, HDTV, video 
    conferencing, multimedia, graphics controllers, video drivers.

Communications: Data, voice and image transmission.  Digital, analog modulation, 
    equalization, error correction, coding, switching. SONET/SDH, ISDN, LAN/WAN/ATM 
    and broadband applications.  Wireless and RF submissions are encouraged.

Custom Application Specific Circuits: Innovative designs for cell-based circuits, 
    full custom ICs and ASIC memories.  Novel design concepts, low power low voltage 
    circuits, high-performance circuits, architectures or system applications
    (automotive, bio-medical, etc.) are of particular interest.  Gate Arrays and

Programmable Devices: GA, EPLD, FPGA, PAL, PLA devices, circuits and architectures, 
    as well as the CAD tools targeting these devices. Device applications are 
    encouraged.

Design Automation - Design Capture:Logic and high-level synthesis and optimization, 
    innovative design capture techniques, frameworks, user interfaces.

Design Automation - Physical Design: Silicon compilation, module generation, symbolic 
    layout, automatic place and routing techniques, circuit parameter extraction and 
    circuit verification.  
    
Simulation and Modeling:Device or process modeling, circuit, functional, timing or 
    logic simulation with emphasis on analog modeling, multi-chip modules and 
    mixed-signal simulation. Submissions are encouraged in the power estimation and
    analysis areas for low-power design, RF modeling and simulation; and interconnect
    and packaging issues for simulationa and modeling.

Fabrication and Assembly: Developments in process integration, quick-turn 
    manufacturing, MOS, bipolar, BiCMOS, smart power and GaAs, multichip modules, 
    package modeling, ESD protection, fiber optic tranceivers.

Testing and Reliability: Advances in design-for-testability (DFT), fault modeling 
    and grading, IDDQ measurements, parametric characterization, high speed or high 
    frequency measurement techniques and failure analysis.

Library Development and Design Methodology: Cell library generation and 
    characterization, reusable and customizable megacells, Algorithim to Silicon 
    design flows.

FURTHER INFORMATION                                                        

For complete author kit instructions, registration information and general
inquiries contact the Conference Manager:  

Melissa Widerkehr, 
Custom Integrated Circuits Conference, 
101 Lakeforest Boulevard,
Suite 270, Gaithersburg, 
MD, 20877, 
Telephone: (301)-527-0902, 
Fax: (301)-527-0994.
Email: Widerkehr@aol.com

Further information can also be obtained from: 

Bob Cordell, Technical Program Chair, 
Bellcore, 
331 Newman Springs Road, Room 3Z-307, 
Redbank, NJ  07701, 
telephone: (908)-758-2963 
email: rrc@nyquist.bellcore.com

OR

Jake Buurma, Conference Chair, 
7115 Raich Drive, 
San Jose, CA, 95120,
telephone: (408)-268-2576. 
email: jake.buurma@taec.com

Potential Exhibitors should contact the Exhibits Chair: 
Brian Fitzgerald, 
IBM Corporation, 
404 Wyman Street, 
Waltham, MA, 02254, 
telephone: (617)-895-1338.
email: fitzgerald@vnet.ibm.com


See the CICC'96 WWW site for more information at :

	http://uivlsi.csl.uiuc.edu/~brian/cicc.html

==========================================================================



Article: 1930
Subject: DMA design needed for Xilinx FPGA
From: dsmith@thor.ece.uc.edu (Doug Smith)
Date: 20 Sep 1995 22:31:07 GMT
Links: << >>  << T >>  << A >>
Does anyone know where I can find a SBus DMA (or DVMA) controller for a
XC4003A? In fact, I'm not sure whether I need a DMA controller on my SBus
slave card or whether the Sparc motherboard's DMA controller can perform all
of the DMA transfers.  Does anyone know about SBus DMA controllers or where
I can find more information on them?  Thanks.

---
Doug Smith			University of Cincinnati
dsmith@ece.uc.edu		Electrical & Computer Engineering

"Fear God, and keep his commandments: for this is the whole duty of man."
  		-King Solomon
---


Article: 1931
Subject: Re: Fast FPGA's?
From: "Steven K. Knapp" <stevek>
Date: 20 Sep 1995 23:11:38 GMT
Links: << >>  << T >>  << A >>
michaelk@macs.ee.mcgill.ca (Michael C. Kim) wrote:
>In Article <43d28f$ij8@paperboy.ids.net>, randraka@ids.net wrote:
>
>lines deleted
>
>>The trick is to pay attention to the device architecture when you do the
>>design.  Keep the combinatorial logic to one level whenever at all possible
>>(yes this is possible more than is obvious...pipeline your decodes and state
>>machines).  Use OHE statemachines, and LFSR counters for timers.  Without doing
>                                        ^^^^^^^^^^^^^^^^^^^^^^^^
>
>Could someone refer me to some references or sites where I can get info
>on what LFSR counters are?  I'm building a system using the Xilinx 4000
>series that requires fast FSM's and this would help a lot.  Also, would
>there be any sites that contain VHDL code for these counters?  Thanks
>in advance.
>
>Michael
>
>
LFSR stands for linear-feedback shift register.  Essentially, an LFSR
counter is a shift register with an XOR-style feedback path.  

Generally, LFSRs count to 2^n - 1 possible states instead of the 2^n
for binary counters.  By decoding a specific counter state and feeding
it back into the XOR feedback, you can make an LFSR cycle through a
predetermined series.  LFSRs are a bit more trouble to design, but they are
fast and very silicon efficient.

If you would like additional information, check out the application
note on LFSRs located on the Xilinx webLINX site at

http://www.xilinx.com/products/appsweb.htm#FPGA

Or, if you would prefer an encoded, compressed PostScript file,
just send an E-mail to 'xdocs@xilinx.com' with 'send 80015' in
the Subject header.

-- Steven K. Knapp
   Corporate Applications Engineer
   Xilinx, Inc.



Article: 1932
Subject: Re: Simulation using XC3000 libraries
From: Yuce Beser <yuce@sh.bel.alcatel.be>
Date: 21 Sep 1995 08:01:24 GMT
Links: << >>  << T >>  << A >>
Evagelia Diamantakou <evd@sn2.ee.umist.ac.uk> wrote:
>Hello ,
>      Does  anyone  know  if  I can  simulate  a  sheet  which  
>consists  of  both symbols  taken  from  Xilinx XC3000  library
>and  symbols  based  on VHDL description.If  you  think  I  can ,
>do  you  know  which  sequence  of  steps  I  sould  follow  to
>simulate the sheet in  Mentor Graphics QuickSimII ?
>Please  e-mail  me  any  replies .
>Thanks ,
>  Evagelia  Diamantakou .
>


By using the synthesis tool, generate the xnf file for the block described in
VHDL, and then assign the FILE attribute to that block in your schematics. Once
you have generated an xnf file for that block, I think you can simulate your
design without any additional step.


Good luck,

Yuce Beser
"speaking for myself"



Article: 1933
Subject: Re: Editors that understand VHDL under UNIX
From: "Jörgen Gade" <jgade@hw.seisy.abb.se>
Date: 21 Sep 1995 08:28:20 GMT
Links: << >>  << T >>  << A >>
Hi,

Could you tell where I can get this VHDL-sensitive editor ?

JG
-- 
**********************************************************

                      Jorgen Gade
                      
               ABB Industrial Systems AB
               
                 jgade@hw.seisy.abb.se
                 
**********************************************************



Article: 1934
Subject: Functional simulation of XC3000 libraries
From: Evagelia Diamantakou <evd@sn2.ee.umist.ac.uk>
Date: 21 Sep 1995 16:02:04 GMT
Links: << >>  << T >>  << A >>
Hello ,
 I  sent  a question  with  the  title  "Simulation using XC3000 libraries" .
What  I  forgot  to  mention  is  that  I  would like  to do  only  FUNCTIONAL  
simulation  to  a  sheet . I  know  that  to  do  timing  simulation  , first
I  need  to  do  place  and  route  which  means  that VHDL  has  to  be
translated  to  XNF . Is  it  the  same  for  functional  simulation ? 
Please  e-mail any  replies .
Thanks ,
 Evagelia Diamantakou .



Article: 1935
Subject: Re: Is there a reprogramable XC17256D available?
From: bartram@esmsun.gtri.gatech.edu (Dan Bartram)
Date: 22 Sep 1995 00:03:24 GMT
Links: << >>  << T >>  << A >>
In article <43k049$549@moe.tas.drs.com>, djg@tas.com (David Gesswein) wrote:
>In article <43js68$o01@merlion.singnet.com.sg>,  <jothi@singnet.com.sg> 
wrote:

>We tried the 128 but it is still pre-production and has several bugs in it 
>which prevent using it with the XC52xx and possibly all Xilinx chips.
>

The 17c128 version works fine with XC40xx parts - it does seem to be a bit
slower than the OTP version from Xilinx.

>We also have used the AT&T reprogramable which did work but does not
>reliably load.  I think it is power ramp up sensitive, on one chases it
>almost always loaded and in another it never would load.  The Xilinx EPROM
>part always loaded.  I don't think they have a 256 out yet either.
>

Atmel said the 256 version should be out by December.


Article: 1936
Subject: Altera FLEX 10K Seminars: 100,000 gates???
From: twcoll@aol.com (TWColl)
Date: 22 Sep 1995 00:34:38 -0400
Links: << >>  << T >>  << A >>
Just in case you are interested, Altera is having some sort of seminar on
their new FLEX 10K family. Altera claims this family has 100,000 usable
gates with BIG ram blocks. You can check it out on their WWW site.

T


Article: 1937
Subject: Reminder on Async96 Symposium
From: taubin@u-aizu.ac.jp (Alexander B. Taubin)
Date: 22 Sep 1995 05:29:40 GMT
Links: << >>  << T >>  << A >>



                         SECOND INTERNATIONAL SYMPOSIUM ON 
      ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS

                                         Sponsored by: 
           The IEEE Computer Society  Technical Committee on VLSI 
                The IEICE Technical Group on VLSI Design 
                                    in cooperation with: 
                                       IFIP WG 10.5
                            The University of Aizu, Japan

                  AIZU-WAKAMATSU, FUKUSHIMA, JAPAN
                                 MARCH 18 - 21, 1996

                             ***********************
                             *   CALL FOR PAPERS   *
                             ***********************
The Second International Symposium on Advanced Research in Asynchronous
Circuits and Systems is being organized as a forum for disseminating
advanced research results on asynchronous circuit and system design. 
Asynchronous systems design is currently enjoying a strong revival, and
many clear directions for further research have begun to emerge.  A major
goal of this symposium is to articulate emerging focal areas through
invited papers, and thereby foster research growth.  Special emphasis will
be given to industrial applications and mature CAD tools. To this end,
papers are being sought on all aspects of asynchronous circuit and system
design, as well as in the following focal areas (in no specific order of
priority):
 --- Industrial Applications of Asynchronous Design
 --- Hybrid Synchro-Asynchronous Systems
 --- CAD Tools for Asynchronous Design
 --- Testing/Design-for-Testability of Asynchronous Circuits
 --- Noise Immunity in Asynchronous Digital Circuits
 --- Low-Power Techniques
 --- High Performance Asynchronous Circuits
 --- Hazard-Free Logic Synthesis and Optimization
 --- Design of Asynchronous State Machines
 --- Metastability and Related Issues
 --- Formal Methods for Asynchronous Design
 --- Petri-Nets, Trace Theory and Related Formalisms
 --- High-Level Synthesis of Asynchronous Circuits and Systems
 --- Asynchronous Design in Commercial HDL Environment
 --- Verification of Asynchronous Circuits and Systems
 --- Asynchronous Datapath and Processor Design
 --- Practical Design Examples
 --- Future Trends (Optical Computing, Neural Networks, Nanotechnology, etc.)


Submissions:
- -----------
Submitted papers should be no more than 15 pages in 11-point font (or
equivalent) with a 60-word abstract, and should include a cover page with
authors' physical and e-mail addresses, phone and FAX numbers.  Prospective
authors should submit papers in one of the following
forms: 
(1) Send six single-sided copies of the manuscript with a cover-page to:
          Alexander Taubin (Async96)
          THE UNIVERSITY OF AIZU   
          Tsuruga, Ikki-machi, Aizu-Wakamatsu City
          Fukushima, 965-80 Japan 

(2) Email compressed Postscript(tm) files to "async96@u-aizu.ac.jp".
Accepted papers will appear in a published proceedings. 

Important Dates:
- ---------------
Papers due:                    October 10, 1995
Notification of acceptance by : December 1, 1995
Final Version by:              January 10, 1995
       

Symposium Officers
- ------------------
General  Chair 
       Tosiyasu Kunii (The University of Aizu, Japan, kunii@u-aizu.ac.jp)
Conference Co-Chairs:
       Takashi Nanya (Tokyo Institute of Technology, Japan, 
                              nanya@cs.titech.ac.jp, tel. +81-3-5734-3041,
fax: +81-3-5734-2817)
       Alex Kondratyev (The University of Aizu, Japan, 
                                  kondraty@u-aizu.ac.jp, tel.
+81-242-37-2557, fax: +81-242-37-2744)
Program  Co-Chairs:
       Luciano Lavagno (Politecnico di Torino, Italy, Cadence Berkeley, USA, 
                                  lavagno@polv2k.polito.it, tel.
+39-11-5644150, fax: +39-11-5644099)
      Alexander Taubin (The University of Aizu, Japan, 
                                    taubin@u-aizu.ac.jp, tel.
+81-242-37-2572, fax: +81-242-37-2744))
Publication Chair:
       Takeshi Yoshimura (NEC, Japan, yoshi@swl.cl.nec.co.jp)
Publicity Chair: 
       Fumiyasu Hirose ( Fujitsu Laboratories Ltd, Japan,
hirose@flab.fujitsu.co.jp)
Finance/Registration Chair : 
      Kazuaki Yamauchi (The University of Aizu, Japan, yamauchi@u-aizu.ac.jp)

Local Arrangement Chair: 
      Yuko Kesen (The University of Aizu, Japan, kesen@u-aizu.ac.jp).
Tutorial/CAD booth Chair:
      Michael Kishinevsky (The University of Aizu,Japan, kishinev@u-aizu.ac.jp)
Industry relations:
      Tsuneo Ikedo (The University of Aizu, Japan, ikedo@u-aizu.ac.jp)
      Masatoshi Sekine (Toshiba, Japan, sekine@srd.ull.rdc.toshiba.co.jp)
US industry representative/chair:
       Alan Davis (University of Utah, USA, ald@endo.cs.utah.edu)
US academy representative/chair:
       Erik Brunvand  (University of Utah, USA, elb@telemark.cs.utah.edu)
European representative/chair :
      Steve Furber  (University of Manchester,UK, sfurber@cs.man.ac.uk)

Program Committee:
 Kunihiro Asada (Japan), Graham Birtwistle (UK), Steven Burns (USA)
Tam-Anh Chu (USA), Jordi Cortadella (Spain), David Dill (USA)
Jo Ebergen (Canada), Ran Ginossar (Israel),  Ganesh Gopalakrishnan (USA)
Mark Greenstreet (Canada),  Mark Josephs (UK), Sadatoshi Kumagai(Japan)
Bill Lin (Belgium),  Alain Martin (USA),  Viacheslav Marakhovski (Japan)
Charles Molnar (USA), Steven Nowick (USA), Takuji Okamoto (Japan)
Martin Rem (Netherlands),  Jens Sparso (Denmark),  Robert Sproull (USA)
Pasupathy Subrahmanyam (USA), Jan Tijmen Udding (Netherlands), Stephen
Unger (USA) Peter Vanbekbergen (USA),  Kees van Berkel (Netherland), 
Victor Varshavsky (Japan) Alex Yakovlev (UK),  Tomohiro Yoneda (Japan)

-- 
Kind regards

Alexander Taubin

THE UNIVERSITY OF AIZU                   phone   +81-242-37-2572 (office)        
Tsuruga, Ikki-machi, Aizu-Wakamatsu City fax     +81-242-37-2744         
Fukushima, 965-80 Japan                  e-mail  taubin@u-aizu.ac.jp     
---- <A HREF="http://www.u-aizu.ac.jp/~taubin/">------------------------


Article: 1938
Subject: Re: Functional simulation of XC3000 libraries
From: Yuce Beser <yuce@sh.bel.alcatel.be>
Date: 22 Sep 1995 06:49:14 GMT
Links: << >>  << T >>  << A >>
Evagelia Diamantakou <evd@sn2.ee.umist.ac.uk> wrote:
>Hello ,
> I  sent  a question  with  the  title  "Simulation using XC3000 libraries" .
>What  I  forgot  to  mention  is  that  I  would like  to do  only  FUNCTIONAL  
>simulation  to  a  sheet . I  know  that  to  do  timing  simulation  , first
>I  need  to  do  place  and  route  which  means  that VHDL  has  to  be
>translated  to  XNF . Is  it  the  same  for  functional  simulation ? 
>Please  e-mail any  replies .
>Thanks ,
> Evagelia Diamantakou .
>

You do not need to do placement&routing in order to have an xnf file for the
block that is described in VHDL. After synthesis, and before placement&routing,
you will have an xnf file (generated by the synthesis tool) which you can use
for functional simulation.

Good luck,

Yuce Beser
"speaking for myself"



Article: 1939
Subject: Re: Help needed-how to instantiate Xbloc component with synopsys
From: mike@vlsivie.tuwien.ac.at (Michael Gschwind)
Date: 22 Sep 1995 11:23:56 GMT
Links: << >>  << T >>  << A >>
In article <43lu7d$2oc@btmpjg.god.bel.alcatel.be> Yuce Beser <yuce@sh.bel.alcatel.be> writes:
>There is a program called "xbloxgen" from Xilinx which is used to instantiate
>xblox modules in the vhdl/verilog code. You input which xblox module you want
>to instantiate in your code, and it generates the xnf file and the vhdl/verilog
>code (component definition, and instantiation lines) for that xblox module. You
>can use this tool to instantiate the xblox modules: clk_div, shift, inc_dec,
>accum, add_sub, compare, counter, decode, data_reg.

Where would I get that program from?  Does anybody have pointers?

m.

-- 

Michael Gschwind, Institut f. Technische Informatik, TU Wien
snail: Treitlstrasse 3-182-2 || A-1040 Wien || Austria
email: mike@vlsivie.tuwien.ac.at   PGP key available via www (or email)
www  : URL:http://www.vlsivie.tuwien.ac.at/mike/mike.html
phone: +(43)(1)58801 8156	   fax: +(43)(1)586 9697
Boycott Whaling!!! Boycott Norway!!! Boycott Norwegian Products!!!


Article: 1940
Subject: Re: Altera and Synopsys Interface
From: mike@vlsivie.tuwien.ac.at (Michael Gschwind)
Date: 22 Sep 1995 11:30:43 GMT
Links: << >>  << T >>  << A >>
In article <43mj0t$bb8@bcarh8ab.bnr.ca> qzhang@bnr.ca (Qian Zhang) writes:
>I had slack time in the range of -30 ns, but the design worked after
>fitting.
>
>Synopsys can still be used as an optimizer to do some common sense
>optimization.
>
>I read that for Xilinx parts, Synopsys maps logic to CLBs, and the
>timing reports are more accurate.

Yup, FPGA compiler (used for the 4k series) maps to LUTs... I dunno
for the 3k series though, which uses the Design Compiler (you can also
use DC for the 4k series, not idea on that either...)

I have no idea how Synopsys decide which chips are supported by FPGA
compiler, and which ones get the DC treatment...

As for the accuracy of timing reports:  Synopsys seriously
underestimates routing delay, so you always seem to end up with slower
chips after routing :-( I'd rather have a speedup from routing, as
experienced with Altera ;-)

m.

PS: Hi Qian!

-- 

Michael Gschwind, Institut f. Technische Informatik, TU Wien
snail: Treitlstrasse 3-182-2 || A-1040 Wien || Austria
email: mike@vlsivie.tuwien.ac.at   PGP key available via www (or email)
www  : URL:http://www.vlsivie.tuwien.ac.at/mike/mike.html
phone: +(43)(1)58801 8156	   fax: +(43)(1)586 9697
Boycott Whaling!!! Boycott Norway!!! Boycott Norwegian Products!!!


Article: 1941
Subject: LFSR's solution
From: flxchen@smtp.dlink.com.tw (Felix K.C. CHEN)
Date: Fri, 22 Sep 1995 15:31:57 +400
Links: << >>  << T >>  << A >>
Dear Friends,

I have read many posts about LFSR (linear feedback shift register)
on this net.  I myself by chance had read the Actel's FPGA Design Guide II,
December 1992, in which a nice decription of LFSR's application
in non-linear counter and random number generator is discussed.

I'd like to outline the details:

For a linear 4-bit counter, it counts in the following sequence

0000
0001
0010
 .
 .
 .
1110
1111
0000

But with LFSR, one can get the following sequence:
(you can start from any value excepting 0000)

1111
0111
0011
0001
1000
0100
0010
1001
1100
0110
1011
0101
1010
1101
1110
1111

The skill is to feedback the XOR(MSB + bit[n1] + bit[n2]...) to
LSB at every cycle.

Depending on the size of the register, different n1, n2 ... are 
needed.

Here is a summary: (M=regster size, K=possible value)

m=2 k=3 n=1
m=3 k=7 n=2
m=4 k=16 n=3
m=5 k=31 n=3
m=6 k=63 n=5
m=7 k=127 n=6
m=8 k=255 n=3,4,5,7
m=9 k=511 n=5
m=10 k=1023 n=7
m=11 k=2047 n=9
m=12 k=4095 n=1,9,10,11
m=13 k=8191 n=6,10,11,12
m=14 k=16383 n=1,11,12,13
m=15 k=32767 n=14
m=16 k=65535 n=10,12,13,15

Regards,

Felix K.C. CHEN




Article: 1942
Subject: Re: palce16v8hd obsolescence
From: granville@decus.org.nz
Date: 22 Sep 95 23:36:26 +1200
Links: << >>  << T >>  << A >>
In article <43jihk$6k0@server.cpr.it>, Maurizio Lippi <lippi> writes:
> We have been informed by the manuf. AMD that the production of this device will
> be stopped in the coming weeks. does anyone know a second source of this pld?
> or a similar device? 
> the major features of this pal are:
> - High output current drive capability (64ma Iol)
> - Programmable Totem-Pole or Open Drain Outputs
> - 200 mV Histeresis
> - Programmable Direct or latched Inputs.
> 
> regards, Maurizio Lippi  
> 
> +------------------------------------------------------------------------+
> +  Maurizio Lippi                   R&D Division                         + 
> +                                                                        +
> +  CAEN SpA                                                              +
> +  Via Vetraia, 11                  50049 VIAREGGIO (ITALY)              + 
> +  Tel. +39 584 388 398             Fax +39 584 388 959                  +
> +  E-Mail: lippi@caen.it            URL: http://www.caen.it              +
> +------------------------------------------------------------------------+
> 
 When we looked for a part with Hystersis, this was the only one we found.
YOu post explains why we never got a straight reply from AMD on it.
This part has a strange pin-out, so the odds of a drop in are almost zilch.
 Let me know if you find anything, as we would like a part with Hysteresis.

Few PLD suppliers seem to understand Hystersis, or even low power in their
rush for ever faster parts....
 We are working on this problem -
If anyone else could really use a PLD with Hystersis, please email details
of PLD Size / Speed / Power / Other features.
        jim granville



Article: 1943
Subject: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
From: ekatjr@eua.ericsson.se (Robert Tjarnstrom)
Date: 22 Sep 1995 14:13:59 GMT
Links: << >>  << T >>  << A >>
In article <43fgn7$45f@news.Belgium.EU.net>, Jan Decaluwe <jand> writes:
>jcooley@world.std.com (John Cooley) wrote:
>
>
>>I personally tend to see hardware when I design hardware, 
>
>This argument is widely used against design methodologies that rely
>on higher levels of abstration. I believe it is misleading. It is the
>same argument that schematic entry addicts use(d) against RTL synthesis. 
>However, I feel safe to assert, John, that you're a convicted synthesis user!!
>

Am I correct if I understand that you indicate that the designer should not tend
to see HW while designing, but rather focus on modeling the functionality at as
high abstraction level as possible? If so, I could not disagree more.

I would say that it is necessary to see hardware architecture when you design. 
Otherwise, you are incapable of making acceptable design solutions. Performance and
product properties are determined by choise of algorithm, architecture (at many 
levels) and technology. Power dissipation/consumption is a physical activity, and 
in order to fulfil power requirements I would say it is necessary to see HW while 
designing.

Prediction on power dissipation must be made for all architectural decisions and in 
order to make such prediction you must see hardware. If not you may end up with drastic
violation on important properties. (A cellular telephone with a talk time of 5 min
would probably be hopless to sell even for Microsoft :-).

Robert Tjarnstrom





Article: 1944
Subject: Re: LFSR's solution
From: michaelk@macs.ee.mcgill.ca (Michael C. Kim)
Date: Fri, 22 Sep 95 14:22:55 GMT
Links: << >>  << T >>  << A >>

I just wanted to thank everyone who helped answer my question
regarding what LFSR's were.  This will prove helpful for me
since my design will have to be fast (approx 20 MHz) and I
need to eke out all the speed I can get from my smaller
modules.  Also, the postings on one-hot encoding for FSM's
was also helpful.

Mike



Article: 1945
Subject: Re: Why does MAX5000 is getting hot?
From: Roger Campana <76734.3304@compuserve.com>
Date: 22 Sep 1995 15:22:33 GMT
Links: << >>  << T >>  << A >>
twtmail@twt.co.il wrote:
>
> 
> I'm using an EPM5016 in a small project.
> I'm using 4 i/o pins for 2 NOT gates osc.
> 
> The component is getting very very hot (after about 5 min.)
> 
> Does anybody knows why?
> 
> Thanks in advance.
> 
> R.H
> 
I've used the 5032'2 and they run hot also. This is due to the quiescent current
requirements. Also depends on how fast you system clock is running. Check 
the graph in the data book "Current vs. Frequency", the amount of current
times Vcc is approx. the dissapated heat. I've never burned myself on one yet
although using the ceramic package, I have got them fast/hot enough to be uncomfortable.

Rog


Article: 1946
Subject: Re: Is there a reprogramable XC17256D available?
From: jothi@singnet.com.sg
Date: Fri, 22 Sep 95 09:44:02 PDT
Links: << >>  << T >>  << A >>

> >We tried the 128 but it is still pre-production and has several bugs in it 
> >which prevent using it with the XC52xx and possibly all Xilinx chips.
> >
> 
> The 17c128 version works fine with XC40xx parts - it does seem to be a bit
> slower than the OTP version from Xilinx.
> 
> >We also have used the AT&T reprogramable which did work but does not
> >reliably load.  I think it is power ramp up sensitive, on one chases it
> >almost always loaded and in another it never would load.  The Xilinx EPROM
> >part always loaded.  I don't think they have a 256 out yet either.
> >
> 
> Atmel said the 256 version should be out by December.

You mean ATMEL & AT&T sell parts which does not work reliably??

I feel you should have a look at the data sheets and design it rather than just 

replace an IC with pin for pin replacements. 

































Article: 1947
Subject: Re: Altera and Synopsys Interface
From: ricks@aruba.wv.tek.com (Richard A Springer)
Date: 22 Sep 1995 10:18:10 -0700
Links: << >>  << T >>  << A >>
>I run into a problem when designing an Altera flex8452-3 with VHDL.  After
[...]
>I was wondering if anyone else run into the same problem.  Your comments will
>be much appreciated.
>
>Regards,
>
>Louis
>c

Same problem here.  We now ignore the Synopsys timing violations and
depend on the timing report from maxplus2.  And yes, I worry that
someday Synopsys will change the design in a very unproductive way
(because it imagines a time violation) and maxplus2 can not straighten
it out.

========================================================================
 Richard A. Springer             UUCP/USENET: ricks@aruba.WV.TEK.COM
 Tektronix, Inc.                     US Mail: P.O. Box 1000,  MS 63-356
 Color Printing & Imaging Div.              : Wilsonville, OR 97070, USA
 (503) 685-3535                          FAX: (503) 685-4901
========================================================================


Article: 1948
Subject: Reprogrammable 17CXXX devices.
From: Martin Mason <martin@atmel.com>
Date: Fri, 22 Sep 1995 23:12:07 GMT
Links: << >>  << T >>  << A >>
Folks,

I would like to clarify Atmel's Serial EEPROM offering. Atmel offers an 
EEPROM version of the 17Cxxx series FPGA support serial programming proms.
The AT17C65 and the AT17C128 are currently shipping in production volume 
and the AT17C256 will be sampling late Q4 early Q1.  The Atmel EEPROM 
serials are pin compatable with the OTP EPROM versions currently offered 
in the market-place and have the added feature that they can be in-system 
(re)programmed (5V) via an industry standard 2-wire interface (24CXXX 
like).  The parts differ very slightly from the OTP EPROM parts as follows :

Cascade mode is not supported on the AT17C65 parts.

Cascade mode will be support from End Nov. '95 on the AT17C128 parts.

Clock must be low during Reset active.

Pin 7/17 is used as the 2-wire interface enable pin (active low) as it is 
not required for a 12V programming voltage (Vpp). When this pin is high 
the parts work as a 17CXXX part.

	The serial parts do support programmable Reset/OE polarity.
	The parts are supported by (most) industry standard programmers.

	The AT17CXXX serial parts are design to have the same fundumental 
performance capability as the OTP EPROM parts.

	If you would like more information on these parts, please send an 
e-mail with your SNAIL MAIL ADDRESS to martin@atmel.com and a databook 
will be yours by return.

Martin.

-------------------------------------------------------------------------
|       Martin Mason            | Snr. FPGA Applications Engineer       |
|       Atmel Corp.             | (Work)         martin@atmel.com       |
|       2125 O'Nel Drive        | (Work2)          fpga@atmel.com       |
|       San Jose                | (Fax)         + (408) 436 4300        |
|       CA 95131                | (Tele)        + (408) 436 4178        |
-------------------------------------------------------------------------


Article: 1949
Subject: Re: Anyone using Altera 8820A ?
From: Matthew Miller <mattm>
Date: 23 Sep 1995 00:26:54 GMT
Links: << >>  << T >>  << A >>
We've used 8820As with both download (bitblaster) and serial eproms. It is 
important that the download cable header be close to the part and traces run
directly. More than an inch separation and we could not get reliable
bitblaster down loads. Serial eprom downloading seems to be more robust.

Good luck!





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