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news@tumlis.lis.e-technik.tu-muenchen.de wrote:
: Hi all,
: is there anyone, who has tried to hack the internal configuration memory
: structure of Xilinx FPGA's?
You may have already looked at this, but check out page 2-26 of the 1994
Xilinx data book(I have 2nd edition). There is some info on the configuration
data stream and how it is organized. Anything more detailed is beyond me.
--
Chad Lord
gt7522b@prism.gatech.edu
Article: 2126
Dimitris Phoukas (dimitris@engn.uwindsor.ca) wrote:
: Can someone give me a pointer to a location describing the Library of
: Parametrized Modules format
: and design style? I am familiar with Xilinx XBLOX only.
LPM was developed by a consortium including Actel, Altera, Exemplar Logic,
Mentor Graphics, Minc, NeoCAD, Synopsys,ViewLogic and Xilinx.
But also Atmel uses macro generators for their FPGAs that are (somehow)
compatibel to LPM.
LPM is now a technical subcommittee of EDIF (Electronic Design Interchange
Format). EDIF is a division of the Electronic Industries Association (EIA).
You can find more informations, the adress of EDI and the phone number
of the LPM contact person at this document:
file://edif.cs.man.ac.uk/pub/edif/inf_and_docs/LPMPressRelease
I hope this will help you.
Markus Wannemacher
----------------------------------------------------------------------------------
@@ @@ Markus Wannemacher
@@@ @@@ @@@@@@ @ @ FernUniversit"at Hagen
@@@@ @@@@ @ @@@ @ @ LG Informationstechnik
@@@@ @@@@ @@@@ @@@@ @ @ @ @ LGZ, Profilstr. 10b
@@@ @@@@ @@@ @ @@@@@ @ @ D-58084 Hagen, Germany
@@@@@@@@@@@@ @ @ @ @ phone +49 2331 987 4547
@@@@@@@@@@ @ @@@ @@@@ fax: +49 2331 987 375
Internet: E-Mail: Markus.Wannemacher@FernUni-Hagen.De
WWW: html://www.fernuni-hagen.de/www2bonsai/IT/team/wm.html
----------------------------------------------------------------------------------
Article: 2127Well, I did some experimenting and found that I could get it to oscillate with the following values (pg. 2-118 of "The Programmable Logic Data Book", 1994): R1 - 1M R2 - 2K C1,C2 - 220pF See ya, -ingo In article <1995Oct18.000308.21958@news.cs.indiana.edu>, Ingo Cyliax <cyliax@cs.indiana.edu> wrote: > >Hi > >I'm trying to get a 480Khz ceramic resonator to work with the >internal oscillator module of an xc3030APC44. I have gotten >crystals to work (i.e. I know about the -S1 flag to makebits). >Is 480Khz too low ? The module is spec'ed for 1-20Mhz. What >values of R1 (1Mohm), R2 (0), C1/C2 (220pF) should I be using ? > >Any ideas ? > >Thanks, -ingo >-- >/* Ingo Cyliax, cyliax@cs.indiana.edu, +1 812 333 4854, +1 812 855 6984 (day) */ -- /* Ingo Cyliax, cyliax@cs.indiana.edu, +1 812 333 4854, +1 812 855 6984 (day) */Article: 2128
In article <461ajs$3sf@mordred.gatech.edu>, bartram@esmsun.gtri.gatech.edu (Dan Bartram) wrote: >In article <460a2b$vrg@melimelo.enst-bretagne.fr>, > Guy LEONHARD <leonhard> wrote: >>I need to programm "one" AMD MACH-435 and I would like to know if somebody >have >>perform this task with a self build programmer. If so or if you know the >>algorithm which must be applied, please e-mail me. > >AMDs MachXL Software and Downloading cable are free, just call them >and ask for it - Toll Free number in France is 0590-8621 (listed on back of >AMDs MachXL data book. > > >**************************************************************************** >Dan Bartram, Jr. Work: (404) 894-7107 >Research Engineer FAX: (404) 894-7080 > To my knowledge, MACH435 is one that doesn't have a JTAG-port to program it, so one DOES NEED a programmer in addition to MachXL. What I would do, is drop MACH435, and use MACH445 instead with the free cable and MACHXL, or if one makes a programmer, it would be nice to be able to program also Altera and Xilinx small EPLD's, which have same capacity easily as MACH's and LEX780's at a lot smaller price, unfortunately still requiring a 300 buck programmer, but in bigger amounts using EPLD's will be cheaper. I am going to compliment my AMD MACH's with a programmer hat does it, and of course it wold be nice to be able to find the programming data so that one could do it onefels, as making these programmers isn't normally very complicated for anyone almost ... I'd be interested to participate in a joint-effort to make a programmer for Xilinx and Altera small EPLD-parts starting from 7032 etc sizes ... Ray S.Article: 2129
May I offer the suggestion as to the apparent difference in performance between
state of the art processors, and your average asic (in terms of clock speed) is
most likely to do with the amount of effort put into a processor design?
IE if you spend anywhere near the amount of time/effort/money to produce your
next asic as Intel did for the pentium, I beleive you would see a very fast
asic.
The old argument from software still applies: sure you "could" code a better
design in raw gates, (or in the case of processors in terms of raw
transistors?)
but it will take you a lot more time/manpower to do it, compared to coding
in RTL and synthesizing it.
To be typically Canadian, I'll argue for the other side as well:
Eventually, processors are supposed to run into a brick wall of physics,
or cost of development, so at that point, the fatware programs will have to
start slimming down to maintain market growth. IE High level (software)
languages benefit by the insane speed increases in processors to date.
--
Gord Wait S-MOS Systems Vancouver Design Centre
(B.C. Canada eh!)
gord@vdc.smos.com
---------------
This sig is under constru
Article: 2130news@tumlis.lis.e-technik.tu-muenchen.de wrote: : Hi all, : : is there anyone, who has tried to hack the internal configuration memory : structure of Xilinx FPGA's? Yes. The real challenge is to do it without using any of the Xilinx software. I built a test fixture with an XC3030 and downloaded it with various bit patterns to isolate which bits affect the behavior of the device. It is interesting from the standpoint of understanding how the device works, but I don't see how you could use this approach for a real design. Figuring out the connectivity will only get you so far. You still need to be able to estimate routing delays. In addition, I believe the Xilinx software avoids leaving internal nodes floating to reduce power consumption. Speaking of power consumption, if you download an invalid bitstream into a XC3000 series device it is possible to blow up the chip due to heat generated from excessive power consumption. Be careful. Ewan ---------------------------------------------------------------- Ewan D. Milne / Computervision Corporation (milne@petra.cv.com) "Talk is cheap." -- Adler On-Line (a TV call-in talk show program)Article: 2131
I am getting ready to produce a quick turn ASIC by translating an fpga XNF netlist to ASIC. One of the vendors we are considering to perform this task is Chip Express; therefore, I was wondering if anyone has had any experiences they could relay to me about Chip Express's translation process. Specifically: * How much time was spent translating your design? * How many problems did you run into? * Did you participate in the translation process or did Chip Express do all the work? * What did they require of from you to perform the translation? Since I have personally gone through a translation process, I know that it is riddled with many pitfalls. This fact makes me wonder if Chip Express's (as well as other quickturn vendors--like Orbit) brochures oversimplify the issue. Any information would be greatly appreciated. Thanks :) +-------------------------------------------------------------------------+ / TED L. BOYDSTON IV \ + Harris Corporation, GASD * PO Box 94000 * MS 102-4823 * Melbourne, FL 32902 + \ Email: tboydsto@harris.com * Fax: (407) 729-2782 * Voice: (407) 729-7999 / +-------------------------------------------------------------------------+Article: 2132
In your recent posting you asked about LPM:
> From: dimitris@engn.uwindsor.ca (Dimitris Phoukas)
> [1] Library of Parametrized Modules info
> X-Nntp-Posting-Host: thor.engn.uwindsor.ca
> Organization: University of Windsor, EE
> Date: Tue Oct 17 11:56:26 MDT 1995
>
> Can someone give me a pointer to a location describing the Library of
> Parametrized Modules format
"LPM was accepted as an EIA Interim standard in April 1993 as an
adjunct standard to EDIF 2 0 0 (EIA-548-A) and was given Interim
Standard number IS-103. LPM is document EIA/IS-103 of May 1993 and is
available from:
Electronic Industries Association
Engineering Department
2001 Pennsylvania Avenue, N.W.
Washington, D.C. 20006
> and design style? I am familiar with Xilinx XBLOX only.
I was one of the people who wrote the original X-BLOX(tm), and I've
been working with LPM since it's inception. The basic idea behind the
two is similar with the major difference being the DataType
Propagation in X-BLOX. Both are highly parameterized and both require
a mapping engine. In the case of X-BLOX, Xilinx provides the mapping
to XC4000 and XC3100 parts. In the case of LPM, the mapping is
provided by the silicon vendor (Altera, QuickLogic) or a third party
(NeoCAD - before they were acquired by Xilinx).
> Also, is it possible to instantiate/generate new LPMs from within VHDL?
LPM is an EDIF standard, so technically, the only valid format for LPM
is EDIF. At the latest LPM meeting (Oct 5, 1995) a working group was
formed to look at VHDL and Verilog issues. I'm a member of that
working group if you have specific items you'd like to have addressed.
> Which vendors support LPMs in their P&R tools?
Altera has supported LPM for some time now. QuickLogic recently
announced support. There are others who will be supporting LPM in the
near future, but it's not my place to make their announcements for
them 8-)
BRIEF AD: Intergraph provides a complete LPM solution including
schematic entry, Verilog and VHDL simulation, and synthesis of LPM to
standard ASICs as part of their VeriBest tools.
> Thanks in advance,
>
> Dimitris Phoukas
> VLSI Research Group, University of Windsor
The latest version of LPM is LPM 2.1.0 which was approved at the LPM
Technical Committee meeting on October 5, 1995. I have several
example schematics (including the infamous "cooley contest") in LPM.
The examples are available as postscript schematics, LPM 2.0.1
compilant EDIF, and Verilog. Intergraph may also provide an updated
chapter 4 of the LPM manual by ftp if an agreement can be worked out
with EIA.
I hope this helps. If you have any other questions, feel free to
e-mail or call me.
--
****************************************
Jorge Seidel **** INTERGRAPH ELECTRONICS
jpseidel@edaco.ingr.com **** Boulder, CO
** Senior Technical Marketing Consultant
** (303) 581-2363 **** FAX: 581-9972 **
****************************************
Article: 2133
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Can you explain why it's necessary to do that in the QEMM definition line?.
I've read the QEMM help files and they say tha Extender programs needn't
special atention. Why does the extender that XACT+Viewlogic uses need this
atention?
Thanks for your help.
Cha.
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Article: 2134
A few weeks ago there was a discussion on how using one-hot
encoding could speed up fsm's. I followed these discussions
closely and I downloaded Xilinx's manuals for info on how to
write the VHDL code. For a 14 state fsm I added the
following code in order to use one-hot encoding:
TYPE STATE_TYPE IS (S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11,
S12, S13, S14);
ATTRIBUTE ENUM_ENCODING : STRING;
ATTRIBUTE ENUM_ENCODING OF STATE_TYPE : TYPE IS "00000000000001 00000000000010 0
0000000000100 00000000001000 00000000010000 00000000100000 00000001000000 000000
10000000 00000100000000 00001000000000 00010000000000 00100000000000 01000000000
000 10000000000000 ";
I took it on faith that using one-hot encoding would speed up my fsm's.
However, just for fun I tried to use the minimum number of bits to
encode my fsm. For instance, in the above example I wrote:
TYPE STATE_TYPE IS (S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11,
S12, S13, S14);
ATTRIBUTE ENUM_ENCODING : STRING;
ATTRIBUTE ENUM_ENCODING OF STATE_TYPE : TYPE IS "0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 ";
I compiled several fsm's that I had designed using Synopsys 3.0b and
XACT 5.1 and I compared the estimated clocking speed using xdelay
for fsm's that use one-hot encoding and just regular encoding (fewest
number of bits). Here are my results:
FSM with 16 states, 32 transitions, 3 inputs, and 19 outputs:
one-hot regular encoding
4010PG191-6 11.0 MHz 13.8 MHz
4010PG191-4 15.0 MHz 18.9 MHz
FSM with 22 states, 51 transitions, 13 inputs, and 37 outputs:
one-hot regular encoding
4010PG191-6 7.7 MHz 10.8 MHz
4010PG191-4 10.5 MHz 14.8 MHz
FSM with 14 states, 30 transitions, 16 inputs, and 16 outputs:
one-hot regular encoding
4010PG191-6 10.6 MHz 13.6 MHz
4010PG191-4 14.5 MHz 18.6 MHz
I also tried compiling one of the fsm's using Synopsys 3.3b:
FSM with 14 states, 30 transitions, 16 inputs, and 16 outputs:
one-hot regular encoding
4010PG191-6 10.0 MHz 10.0 MHz
4010PG191-4 13.3 MHz 13.9 MHz
All of the above results are puzzling. When I use Synopsys 3.0b,
I get the exact opposite results when I use one-hot encoding -
it slows the fsm down! The findings are not as marked when I
use Synopsys 3.3b but for the -4 speed grade I still find the
same result. Am I doing something wrong? Has anyone else
noticed this?
Mike
--
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
_/ Michael C. Kim, Master's Candidate _/
_/ Microelectronics and Computer Systems Lab _/
_/ McGill University, Montreal, Canada _/
_/ Email: michaelk@macs.ee.mcgill.ca _/
_/ Phone: (514) 398-3937 Fax: (514) 398-4470 _/
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Article: 2135EVALUATING DESIGN TOOLS TO: all the lurkers out there on comp.arch.fpga How good are your design tools? Are they well suited for your work? Are they worth what you pay for them? PREP Corp. (the programmable logic benchmarking outfit) has been working to provide standard means for you and your vendors to evaluate design tools -- like how efficient are they in producing good performance or small size in your designs. But we now need your evaluations of what we have been doing. The PREP Working Group 4 has determined (largely at the suggestion of the EDA tool vendors) that the best means of evaluating tools is by using "Test Benches." of "Real Designs" Test Benches are much different than Benchmarks, which PREP is already famous (infamous?) for. So don't let your mind jump down that branch. We're talking about something a lot different here. The objective is to provide Standard PREP Test Benches to the industry. We think that designers can use them to compare design methodologies and design tools as well as devices (even devices that aren't programmable). PREP Test Benches are circuit functions described in an HDL but specified to meet certain rigorous test requirements. The Test Bench describes the stimulus/response of an accompanying HDL design. We are looking for "Real Designs" from users. The purpose is to save time for both designers and vendors. Having Standard Test Benches will allow designers to compare the results of designs by different tools and know the comparison is orange-to-orange. Vendors can have designs done and ready for designers to look at. However, to achieve these noble objectives the standard functions must be similar to the functions designers are working with. They must be common and important. And all of the. little details of specifying and employing a standard must be done in the most user friendly way, or it won't be used. These needs mean we need your inputs, donations of functions and evaluations of candidate circuit functions -- from you, the designer. To get your inputs PREP has worked for months to get our homepage up and working on the Web. We now have the means to communicate easily, inexpensively and quickly with the EDA user community. You will find information about this work at "www.prep.org." Look in the "Synthesis Corner." There you will find a history of the Test Benches developments, a specification on reporting results, Test Benches for the nine (9) PREP Benchmarks and a RISC processor, and more. PREP is also establishing a discussion group (list server system) for those that want to comment, analyze the proposals or simply read all the comments. You are invited to jump into www.prep.org and check out this important project. Join it or just criticize it, but please give us your opinions. John Birkner Chairman, PREP Working Group 4 synth@prep.orgArticle: 2136
(Apologies that this is not particularly FPGA related.) In <463kmb$n26@diable.upc.es> <cha> writes: >I've read the QEMM help files and they say tha Extender programs needn't >special atention. Why does the extender that XACT+Viewlogic uses need this >atention? DEVICE=C:\QEMM\QEMM386.SYS x=a000-dfff frame=e000 In the first 1 MB of address space on a typical PC, RAM occupies addresses 00000 through 9FFFF. Adresses A0000 through FFFFF are used for ROM BIOS and for memory mapped I/O, such as the frame buffer memory of a video card. QEMM and other memory manager detect unused I/O address space and map RAM into it, in order to load TSRs, drivers, and the EMS frame, above the usual RAM address space. I assume QEMM 6.x, a fairly old memory manager, does not correctly detect some new, modern devices between addresses A0000 and DFFFF. Therefore I direct QEMM to assume there is no available address space there using the x=... directive. The frame= directive explicitly places my EMS frame at E0000. If I load QEMM without these directives, it maps EMS onto some address range which conflicts with one of my cards (my SCSI controller, I think). Then when I run Workview, its DOS extender allocates EMS memory and writes to it. This unfortunately overwrites the registers or buffers of one of my cards and crashes my PC. You may be experiencing the same problem. Jan.Article: 2137
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / "PANIC! Need Help On USE/DA Report Card on Mentor Graphics"
_] [_
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
HELP! As the president of the Users Society for Electronic Design Automation
(USE/DA) I also foolishly signed up to do a detailed report card on Mentor
Graphics next week. (I'm the same guy who did the survey on Cadence for their
user's group meeting. I got some interesting results but don't want to
release it until this Mentor survey is done so they don't influence each
other.) What I need from you, as a Mentor user, is to tell me exactly how
you feel about various aspects of doing business with Mentor. ALL CUSTOMER
INPUT WILL BE USED ANONYMOUSLY. (That is, I'll report *what* customers
think but not exactly *who* said it.)
My goal is to provide a balanced report card that contains not only where
Mentor has messed up, but also where they're doing a good job. I'm an ASIC
designer so I'd like to ask that you be as specific as possible in what you
say. If you love/hate specific things Mentor does/offers, I want to hear
the specifics. Feel free to respond on anything, but to get you in an
evaluation frame of mind, I'll ask:
Please Report Your Primary Interest In Mentor Tools (ASIC design, PCB
design, Analog IC design, RTL simulation, Full Custom Design, etc):_________
1.) What tools do you specifically use (by name)?:
2.) What does your company make/sell?
3.) Where are you? (City, State, Country)?
-----------------------------------------------------------------------------
1.) What do you think of Mentor's on-line & hard copy documentation? Is it
usually very helpful & complete, out-to-lunch, or what?
2.) What do you think of Mentor's hotline? What's the typical turnaround
you get for your questions? Do you feel that you get access to
knowlegable experts or new college graduates most of the time? What do
you think of their "We'll call you back" way of running the hotline?
How many times have you had to use it in a typical month?
3.) What do you think of Mentor's local support in your area? Are they
around after your company bought the tool? Are they helpful?
4.) What do you think of Mentor's electronic connectivity? How about their
WWW page? "comp.sys.mentor" ?
5.) What do you think about Mentor Professional Services? Has your company
lost employees to this? Have they solved your problems? Do you like
Mentor offering such services that might mean doing design for your
company?
6.) What do you think about Mentor training? Have you used there classes?
Were they very helpful, a complete waste of time or somewhere in
between? Please be specific.
7.) How do you feel about the Mentor sales force? Do they talk to you or
are they only interested in your VP of Engineering? Do they help you
through business problems year round or only when there a potential
sale in the works? Going from GREAT to HORRIBLE please rank them
equal to (choose one)
- "Ghandi has serious competition compared to my Mentor saleman!" (or)
- "I want to base my whole life philosophy around you." friends (or)
- "Please!, Marry my daughter!" good friends (or)
- Helpful friends (or)
- Helpful business acqaintances (or)
- Helpful Deparment store cashiers (or)
- Indifferent Department store cashiers (or)
- New Car salesmen (or)
- Door-to-Door vacuum cleaner salesmen (or)
- Used Car salesmen (or)
- Con artists just a few steps ahead of the law (or)
- Congressmen and/or convicted con-artists
8.) What's the most POSTIVE Mentor related experience you've had? If you
were made "Wally-Rhines-for-a-day," what would you NOT change about Mentor?
9.) What's the most NEGATIVE Mentor related experience you've had? If you
were made "Wally-Rhines-for-a-day," what would you change about Mentor?
10.) What specifically do you techinally like about their tools? What's their
best tool? What's their worst tool? Why? (Give details.)
11.) Do Mentor's point tools play nice with other Mentor point tools? Do
Mentor point tools play nice with non-Mentor tools? (Give specifics.)
12.) Overall, how you rank Mentor compared to other EDA companies you've
dealt with? Far better, far worst, about average?
Again, my asking these questions is to get you to tell me what you think
about Mentor as a whole and concerning specific products & services they
offer. No names nor sources will be used in reporting the general user
views of Mentor. Thank you for your time! :^)
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3713 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 2138I have a Chronology docutime (entry level timing designer) for sale. My employer finally purchased the professional version so I have no need for it. I have org disks, key, and all doc. Maintenance can be renewed for $99. The package cost $495; I would like to get $250. Thanks, John Maher jomah@aol.comArticle: 2139
Michael Kim (michaelk@macs.ee.mcgill.ca) wrote:
: A few weeks ago there was a discussion on how using one-hot
: encoding could speed up fsm's. I followed these discussions
: closely and I downloaded Xilinx's manuals for info on how to
: write the VHDL code. For a 14 state fsm I added the
: following code in order to use one-hot encoding:
: TYPE STATE_TYPE IS (S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11,
: S12, S13, S14);
: ATTRIBUTE ENUM_ENCODING : STRING;
: ATTRIBUTE ENUM_ENCODING OF STATE_TYPE : TYPE IS "00000000000001 00000000000010 0
: 0000000000100 00000000001000 00000000010000 00000000100000 00000001000000 000000
: 10000000 00000100000000 00001000000000 00010000000000 00100000000000 01000000000
: 000 10000000000000 ";
: I took it on faith that using one-hot encoding would speed up my fsm's.
: However, just for fun I tried to use the minimum number of bits to
: encode my fsm. For instance, in the above example I wrote:
: TYPE STATE_TYPE IS (S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11,
: S12, S13, S14);
: ATTRIBUTE ENUM_ENCODING : STRING;
: ATTRIBUTE ENUM_ENCODING OF STATE_TYPE : TYPE IS "0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 ";
: I compiled several fsm's that I had designed using Synopsys 3.0b and
: XACT 5.1 and I compared the estimated clocking speed using xdelay
: for fsm's that use one-hot encoding and just regular encoding (fewest
: number of bits). Here are my results:
: FSM with 16 states, 32 transitions, 3 inputs, and 19 outputs:
: one-hot regular encoding
: 4010PG191-6 11.0 MHz 13.8 MHz
: 4010PG191-4 15.0 MHz 18.9 MHz
: FSM with 22 states, 51 transitions, 13 inputs, and 37 outputs:
: one-hot regular encoding
: 4010PG191-6 7.7 MHz 10.8 MHz
: 4010PG191-4 10.5 MHz 14.8 MHz
: FSM with 14 states, 30 transitions, 16 inputs, and 16 outputs:
: one-hot regular encoding
: 4010PG191-6 10.6 MHz 13.6 MHz
: 4010PG191-4 14.5 MHz 18.6 MHz
: I also tried compiling one of the fsm's using Synopsys 3.3b:
: FSM with 14 states, 30 transitions, 16 inputs, and 16 outputs:
: one-hot regular encoding
: 4010PG191-6 10.0 MHz 10.0 MHz
: 4010PG191-4 13.3 MHz 13.9 MHz
: All of the above results are puzzling. When I use Synopsys 3.0b,
: I get the exact opposite results when I use one-hot encoding -
: it slows the fsm down! The findings are not as marked when I
: use Synopsys 3.3b but for the -4 speed grade I still find the
: same result. Am I doing something wrong? Has anyone else
: noticed this?
: Mike
: --
: _/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
: _/ Michael C. Kim, Master's Candidate _/
: _/ Microelectronics and Computer Systems Lab _/
: _/ McGill University, Montreal, Canada _/
: _/ Email: michaelk@macs.ee.mcgill.ca _/
: _/ Phone: (514) 398-3937 Fax: (514) 398-4470 _/
: _/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
--
I don't know a lot about SYNOPSYS tools but I suspect that your
definition of the states is not quite correct. With 1-hot encoding
you are defining only 1 bit to have significance at any given time.
Therefore, your state encoding should imply that if a bit is set the
synthesizer does not need to ensure that all the other bits are not set.
In EXEMPLAR you can do this by defining a ONEHOT attribute or in a similar manner
to what you detailed except that the state definition can contain a '-' to
make sure that decoding of the state is limited to the single bit.
What you have done with your encoding has probably led to a widening of the
input terms in front of the FF's of the state machine and this leads to
multiple LUT levels and larger fanout of the signals.
||||
Morgan Smail ||||\ |||| tel:
Newbridge Networks Corporation ||||\\|||| 613-599-3600
600 March Road P.O Box 13600 ||||\\\||| ext:
Kanata, Ontario, Canada ||||\\\\|| 6481
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Article: 2140I am using PC/Silos that runs with the DOS/16M extender. DOS/16M will not start when I have 40MB of RAM in my machine. It complains that there is not enough memory to start up LOADER. If I take out 8MB, leaving 32MB, it is happy. My theory is that DOS/16M uses a signed, 16-bit integer variable for the memory size if K-bytes. So if there is over 32 MB it sees the memory size as negative or, at best, N - 32 MB. Does anyone know of a more modern version of DOS/16M? I know there is a newer version version of Silos but it requires Windows. -- * * * * * * * * * * * * * * * * * * * * * * * * * * Floyd Miller floyd@wmi.com * * Woodward McCoach, Inc. West Chester, PA USA * * * * * * * * * * * * * * * * * * * * * * * * * *Article: 2141
In article <463qj1$b6o@sifon.cc.mcgill.ca>, Michael Kim <michaelk@macs.ee.mcgill.ca> wrote: >A few weeks ago there was a discussion on how using one-hot >encoding could speed up fsm's. I followed these discussions >closely and I downloaded Xilinx's manuals for info on how to >write the VHDL code. For a 14 state fsm I added the >following code in order to use one-hot encoding: > <Much deleted showing state assignments and benchmarks> <Many words trying to explain what I have found out with Viewlogic and Xilinx added> I have done some testing with the Viewlogic tools and Xilinx parts. You only save with one hot if you tell the synthesis tool that only one bit in the state vector needs to be checked for when we are in a state. If you have (pseudocode, not VHDL) S0 = "0000000001" IF (or CASE) state = S0 this will generate a 10 bit wide AND which is very slow (specially with Viewlogic which daisy chains the function when synthesizing it, supposed to be fixed in next release). If you tool supports don't cares such as S0 = "XXXXXXXXX1" Then the IF becomes a test of one bit. I would be interested in knowing if other tools support don't care on assignments. Viewlogic doesn't, they are treated as 0. Email me (djg@tas.com) if you know. You get the same problem on assigning the new state assignment. If you have other functions which recover from entering bad states so you don't care what happens when more than one bit is set you have to write somewhat strange VHDL to do this since their is no way in VHDL to say that only one bit should be set so extra logic reductions can be done. Some tools have a option to say that one hot encoding is being done so they will do this (Viewlogic says this will be in their next release). If S0x is the don't care version and S0 is the normal version this is most efficient version (smallest # of terms in each equation generated) I could find with the Viewlogic tool is. new_state = "0000000000" IF state = S0x new_state = new_state OR S1 END IF IF state = S1x new_state = new_state OR S2 END IF Other forms like case have additional logic saying the equivalent of IF not state 0 and not state 1 and not state 2 and state 3 then... Without tool support for one hot I could not figure any way in the VHDL language to specify things so that if you have a test in most of your states that caused it to go to one state it could do the following optimization. Example if signal test caused transition to S0 in all states except 2 it would generate an equation like new bit 0 = (state bit 0 & test) | (state bit 1 & test) | (state bit 3 & test) with one hot encoding you can rewrite this (because only one bit is allowed to be set) as new bit 0 = test and not (state bit 2) Try this and let me know what the results are David Gesswein djg@tas.comArticle: 2142
In my current project I need to design a PCI interface using FPGA. I have the official PCI spec book, but I need more information on the actual implementations that are out there. For example, what is the maximum "cache line size" that people actually use in their machine. It will have an effect on how complicated the FPGA code will be. Do I need a cache line size computation circuit on the whole 8 bits for the write line and invalide operation? Also what is the maximum DMA throughput between device and memory I can expect on a real system under each transfer type. Any info or pointers to info will be appreciated. Thanks. Wen-King Su, wen-king@myri.com, wen-king@cs.caltech.eduArticle: 2143
In article <45svp2$jml@marina.cinenet.net>, kirani@cinenet.net (kayvon irani) wrote: We had 20-odd Synario seats, between PC and Sun. It's a very solid tool, and available on both platforms. No simulator, but it does have a waveform viewer that links to the schematic- capture tool (but, you would need to get your data into their waveform-database format). Hope this helps,Article: 2144
Try using enumerated encoding, and passing the design through the Synopsys Finite State Machine compiler. I have found that this tool does a very good job of FSM optimization, and will consistently produce a one-hot design which will run as fast, or faster than a minimally encoded equivlent.Article: 2145
wen-king@myri.com (Wen-King Su) wrote: >In my current project I need to design a PCI interface using FPGA. I >have the official PCI spec book, but I need more information on the actual >implementations that are out there. >... >Any info or pointers to info will be appreciated. Thanks. Try the PCI-SIG homepage: http://www.teleport.com/~pc2/pcisigindex.html Roland.Article: 2146
ejessen@ix.netcom.com (Erik Jessen) wrote: >In article <45svp2$jml@marina.cinenet.net>, > kirani@cinenet.net (kayvon irani) wrote: >We had 20-odd Synario seats, between PC and Sun. It's a very >solid tool, and available on both platforms. No simulator, >but it does have a waveform viewer that links to the schematic- >capture tool (but, you would need to get your data into their >waveform-database format). > >Hope this helps, Just want to clarify here: The Synario product itself runs on the PC, under Windows. It has both Verilog and VHDL simulation systems. One of the products in the Synario line is the Engineering Capture System, or ECS, which is available for both PC and Sun. It is Schematic entry and netlisting with links to most popular CAD back-end tools, and a do-it-yourself processor interface kit for those with special interface requirements. -TBBArticle: 2147
You can avoid an invalid bitstream causing any havoc by specifying CRC inclusion in the bitstream. That will cause the device to abort during programming, and stay in its quiescent mode. At least it does in XC40xx series devices. -fmArticle: 2148
subscribe comp-arch-fpga@super.org sharono@ukefl.demon.co.ukArticle: 2149
Has anyone managed to migrate a design from Xilinx 4K to 5K to see how they stack up in practice? Does the claim 'one 5K CLB = two 4K CLB' work out, provided the 4K memory feature is not used? -- Simon Bacon
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