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Messages from 2475

Article: 2475
Subject: Re: Median filter
From: Steve Knapp <stevek>
Date: 13 Dec 1995 03:09:03 GMT
Links: << >>  << T >>  << A >>
Your request has been forwarded to our DSP applications group.  The basic
structure should be close to a FIR and should operate at over 10 MHz.

In general, you can also contact our DSP applications group by sending an
E-mail to 'dsp@xilinx.com'.  Also, to see some of the benefits of using
programmable logic for DSP functions, check out

http://www.xilinx.com/apps/dsp.htm

-- Steve Knapp
   Corporate Applications Manager
   Xilinx, Inc.



Article: 2476
Subject: Your PLD/FPGA Experiences Needed for Article
From: Hank Wallace <hwallace@roanoke.infi.net>
Date: 13 Dec 1995 15:31:59 GMT
Links: << >>  << T >>  << A >>
Hello everyone...

     I am writing an article for a national publication on the
use of programmable logic in communications systems and am
searching for working engineers to interview regarding
their experiences with PLDs. Do you have such experience and
would you like to participate? If so, just jot some answers to
the following interview questions and email to
hwallace@roanoke.infi.net. I will email or call you to let you
know if your responses will be included. If I can use your
responses, I would prefer to use your name in the article, so
please NOTE BOLDLY in your response if you desire to remain
anonymous!

     Please do NOT include any confidential or proprietary
company information in your responses. Neither I nor the
publication will be held liable for publishing or not publishing
the information you provide. I am seeking only general experience
and advice to new users of PLDs so that we can all benefit from
each others' scars. Also, please include your phone number and
address for verification.


Here we go:

1. In general terms, what is your application of the PLD?

2. What is the family of the PLD (FPGA, CPLD, etc.) and its
capacity?

3. Whose parts and tools did you choose and why?

4. How many vendors did you evaluate before choosing an
architecture and tool vendor?

5. How many PLD designs have you completed?

6. Are there alternative ways of doing what you did in your PLD
design and if so why did you choose PLDs?

7. What were some of the problems using PLDs? For example,
architecture learning curves, bugs in tools, timing problems.

8. What is your background, hardware, software, analog, etc.?

9. Would you estimate the complexity and completion times for
some of your designs (i.e., gate count, days to complete)?

10. What would you do differently in your next design and
recommend to other engineers regarding PLDs?



Thanks for your participation!


Hank Wallace
Atlantic Quality Design, Inc.
(540)966-4356
hwallace@roanoke.infi.net



Article: 2477
Subject: Looking for OpenABEL
From: jpa@hobbes.inesc.pt (Jose'Pedro Abreu)
Date: Thu, 14 Dec 1995 10:16:40 GMT
Links: << >>  << T >>  << A >>
Hi,

I am looking for some pointers regarding OpenABEL. I have the ABEL
manuals from DATA-IO but there little referrence to OpenABEL.

I've checked the www site from DATA-IO but I couldn't find anything.

Thanks in advance.

Pedro
--
-----------------------------------------------------------
Jose' Pedro Abreu 
Address : INESC              Phone : +351.1.3100364
          R. Alves Redol 9   Fax   : +351.1.525843 
          1000 LISBOA        Email : jpa@inesc.pt
          Portugal                   Jose.Abreu@inesc.pt 
-----------------------------------------------------------


Article: 2478
Subject: Gated Clock Problem in Xilinx FPGA Implementation
From: ccchen@bluejays.EE.NCTU.edu.tw (Chih-Ching Chen)
Date: 14 Dec 1995 11:36:57 GMT
Links: << >>  << T >>  << A >>

I have a design bases on pipeline architechure, and I want to implement it on
Xilinx XC4000 FPGA. And my design entry is verilog HDL through Synopsys
synthesis to xnf.

That just like the figure:

         DFF1                         DFF2
         +--+                         +--+
 input1  |  |        +-------+ input2 |  |
    ---->|  |------->|       |------->|  |
         |  |        +-------+        |  |
         +--+            |            +--+
          ^        combinational       ^
          |             ckt            |
 clock1 --+                  clock2  --+

Because the clock2 is gated clock-> (clock1 and other enable signal)
so clock2 will get at least one CLB delay than clock1.
If my combinational ckt have minima delay path only one CLB delay or least,
the input1 will feedthrough DFF2. It looks like clock skew.....

Anyone have this side experinence or opinion, can you give me some recommend..
Thankx very much....

--
Chin-Chih Chen
ccchen@athletes.ee.nctu.edu.tw 



Article: 2479
Subject: Re: Gated Clock Problem in Xilinx FPGA Implementation
From: Scott Kroeger <Scott.Kroeger@mei.com>
Date: Thu, 14 Dec 1995 08:34:28 -0600
Links: << >>  << T >>  << A >>
Chih-Ching Chen wrote:
> 
> I have a design bases on pipeline architechure, and I want to implement it on
> Xilinx XC4000 FPGA. And my design entry is verilog HDL through Synopsys
> synthesis to xnf.
> 
> That just like the figure:
> 
>          DFF1                         DFF2
>          +--+                         +--+
>  input1  |  |        +-------+ input2 |  |
>     ---->|  |------->|       |------->|  |
>          |  |        +-------+        |  |
>          +--+            |            +--+
>           ^        combinational       ^
>           |             ckt            |
>  clock1 --+                  clock2  --+
> 
> Because the clock2 is gated clock-> (clock1 and other enable signal)
> so clock2 will get at least one CLB delay than clock1.
> If my combinational ckt have minima delay path only one CLB delay or least,
> the input1 will feedthrough DFF2. It looks like clock skew.....
> 
> Anyone have this side experinence or opinion, can you give me some recommend..
> Thankx very much....
> 
> --
> Chin-Chih Chen
> ccchen@athletes.ee.nctu.edu.tw

I have no experience with synthesis, but your problem stems from 
gating the clock external to the CLB.  Xilinx CLB's have CE inputs 
that internally gate the global clock.

You want to synthesize something like this:

 
          DFF1                         DFF2
          +--+                         +--+
  input1  |  |        +-------+ input2 |  |
     ---->|  |------->|       |------->|  |
          |  |        +-------+   CE-->|  |
          +--+            |            +--+
           ^        combinational       ^
           |             ckt            |
  clock1 --+----------------------------+

Unfortunately, I can't tell you how to steer Synopsys in that 
direction.

Regards,
Scott


Article: 2480
Subject: Re: Gated Clock Problem in Xilinx FPGA Implementation
From: Yuce Beser <yuce@sh.bel.alcatel.be>
Date: 14 Dec 1995 16:07:07 GMT
Links: << >>  << T >>  << A >>
ccchen@bluejays.EE.NCTU.edu.tw (Chih-Ching Chen) wrote:
>I have a design bases on pipeline architechure, and I want to implement it on
>Xilinx XC4000 FPGA. And my design entry is verilog HDL through Synopsys
>synthesis to xnf.
>
>That just like the figure:
>
>         DFF1                         DFF2
>         +--+                         +--+
> input1  |  |        +-------+ input2 |  |
>    ---->|  |------->|       |------->|  |
>         |  |        +-------+        |  |
>         +--+            |            +--+
>          ^        combinational       ^
>          |             ckt            |
> clock1 --+                  clock2  --+
>
>Because the clock2 is gated clock-> (clock1 and other enable signal)
>so clock2 will get at least one CLB delay than clock1.
>If my combinational ckt have minima delay path only one CLB delay or least,
>the input1 will feedthrough DFF2. It looks like clock skew.....
>
>Anyone have this side experinence or opinion, can you give me some recommend..


Instead of using a gated clock, you can use the clock enable input of the DFF.
Connect enable signal of clock2 to the clock enable input of the DFF2.

         DFF1                         DFF2
         +--+                    CE   +--+
 input1  |  |        +-------+   ---->|  |
    ---->|  |------->|       |------->|  |
         |  |        +-------+ input2 |  |
         +--+            |            +--+
          ^        combinational       ^
          |             ckt            |
 clock1 --+                  clock1  --+


Good Luck,

Yuce Beser
"speaking for myself"



Article: 2481
Subject: problem with statemachine
From: Lutz Buettner <bue@e-technik.tu-ilmenau.de>
Date: 15 Dec 1995 07:51:54 GMT
Links: << >>  << T >>  << A >>

I compile my State Machine (VHDL) with FPGA XILINX 4000 at the Synopsys.
	- 16 states
	- 40 transitions
	- 10 inputs
	- 8 outputs	from XILINX Data Book.
My State Machine have 
	- 9 states
	- up to 9 input-states for one state
	- up to 5 output-states in one state.
	- and complex logic in the states

At the "Extraction" I get errors :
Warning: The transition (or output) function for state <state_name> is too large.
Error: Extraction is too expensive.

How much can be the transition /output /input function for my State Machine ?
Can I set or reset other signals in the State Machine or must I use other block
for set/reset this signals ?

Who can me response ?
Thank you.




Article: 2482
Subject: Re: Gated Clock Problem in Xilinx FPGA Implementation
From: peb@trsvr.tr.unisys.com (Pete Becker)
Date: Fri, 15 Dec 1995 13:16:33 GMT
Links: << >>  << T >>  << A >>
In article <4ap28p$8ke@netnews.nctu.edu.tw>,
   ccchen@bluejays.EE.NCTU.edu.tw (Chih-Ching Chen) wrote:
>
>I have a design bases on pipeline architechure, and I want to implement it on
>Xilinx XC4000 FPGA. And my design entry is verilog HDL through Synopsys
>synthesis to xnf.
>
>That just like the figure:
>
>         DFF1                         DFF2
>         +--+                         +--+
> input1  |  |        +-------+ input2 |  |
>    ---->|  |------->|       |------->|  |
>         |  |        +-------+        |  |
>         +--+            |            +--+
>          ^        combinational       ^
>          |             ckt            |
> clock1 --+                  clock2  --+
>
>Because the clock2 is gated clock-> (clock1 and other enable signal)
>so clock2 will get at least one CLB delay than clock1.
>If my combinational ckt have minima delay path only one CLB delay or least,
>the input1 will feedthrough DFF2. It looks like clock skew.....
>
>Anyone have this side experinence or opinion, can you give me some 
recommend..
>Thankx very much....
>

I haven't worked with FPGAs, but how about instead of:

clk1 <= clk;
clk2 <= clk and enable;

you use:

clk1 <= clk and '1';
clk2 <= clk and enable;

To compensate for the CLB delay on clk2 (and specify a "don't touch" on the 
clk1 assignment so it doesn't get optimized by your compiler).


=================================================
Disclaimer: My comments are not necessarily the
opinion of my employer, myself, or anyone else.
-------------------------------------------------
  Peter Becker
  peb@trsvr.tr.unisys.com
=================================================


Article: 2483
Subject: Re: FPGA => ASIC (Summary)
From: lllapides@aol.com (Lllapides)
Date: 15 Dec 1995 10:37:19 -0500
Links: << >>  << T >>  << A >>
Dave in Message-ID: <4a3i7b$6gc@classic.iinet.com.au> provided some
information on migrating from FPGA to ASIC.  His primary issues, test
vectors and timing, are certainly correct.  There is also the issue of 
whether to just retarget the netlist, or to resynthesize to the ASIC 
target if an HDL was used as the original design source.  In most cases,
resynthesizing will give better results both in area and delay
optimization.  

Also, as far as the listed vendors, most silicon foundries will now do 
FPGA to ASIC conversions.  For the larger ones, getting their attention
may be the problem.  For those, talk to your local design center.  There
are also other companies that specialize in these conversions, including

ASIC Technical Solutions
San Jose
Kash Johal, 408-943-1332

Siquest
Sunnyvale
Jeff Strickland

Also, Dave mentioned TEMIC (Matra).  While a European company, they
also have an office in Santa Clara that has some significant experience
doing conversions.  

The other possibility is to do the conversion yourself.  The Exemplar
Logic
Galileo software has this capability, and most of the foundries and
conversion services use this software.  Galileo can do both the 
retargeting and resynthesis, as you need.  Please contact Exemplar Logic
directly for more information (info@exemplar.com).  

Regards,

Larry Lapides
Exemplar Logic


Article: 2484
Subject: WAnted: correlator!!!!!
From: <javier@world>
Date: 15 Dec 1995 18:13:25 GMT
Links: << >>  << T >>  << A >>
Does anyone have implemented a digital binary correlator, complex, of 512 taps
each channel, using a FPGA?


---------------------------------174281773831667--


Article: 2485
Subject: WAnted: correlator!!!!!
From: <javier@world>
Date: 15 Dec 1995 18:13:55 GMT
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

---------------------------------174281773831667
Content-Transfer-Encoding: 7bit
Content-Type: text/plain; charset=us-ascii

news:4asds5$20n@diable.upc.es

---------------------------------174281773831667
Content-Transfer-Encoding: 7bit
Content-Type: text/plain

Article: 2486
Subject: Re: Gated Clock Problem in Xilinx FPGA Implementation
From: pss1@hopper.unh.edu (Paul S Secinaro)
Date: 15 Dec 1995 18:55:39 GMT
Links: << >>  << T >>  << A >>
In article <4ap28p$8ke@netnews.nctu.edu.tw>,
Chih-Ching Chen <ccchen@bluejays.EE.NCTU.edu.tw> wrote:
>
>I have a design bases on pipeline architechure, and I want to implement it on
>Xilinx XC4000 FPGA. And my design entry is verilog HDL through Synopsys
>synthesis to xnf.
>
>That just like the figure:
>
>         DFF1                         DFF2
>         +--+                         +--+
> input1  |  |        +-------+ input2 |  |
>    ---->|  |------->|       |------->|  |
>         |  |        +-------+        |  |
>         +--+            |            +--+
>          ^        combinational       ^
>          |             ckt            |
> clock1 --+                  clock2  --+
>
>Because the clock2 is gated clock-> (clock1 and other enable signal)
>so clock2 will get at least one CLB delay than clock1.
>If my combinational ckt have minima delay path only one CLB delay or least,
>the input1 will feedthrough DFF2. It looks like clock skew.....
>
>Anyone have this side experinence or opinion, can you give me some recommend..
>Thankx very much....

I don't have much experience with Xilinx, but in general you don't
want to use gated clocks if you can help it.  Fortunately, I believe
flip-flops on the XC4000 have clock-enable inputs, so you can clock
both DFF1 and DFF2 off of the same global clock spine (clock1 in this
case), and then just feed the enable signal into the clock enable
input on DFF2.  This will eliminate any skew problems.

If you don't have clock enables on your flops (like in Altera FLEX
8000), it can get ugly.  One approach is to place a 2-to-1 mux in
front of the input of DFF2 and use the clock enable as the select
line, like this:

       +------------------+
       |                  |
       |   |\             |
       +-->|0|    +-----+ |
           | |--->|D   Q|-+-----> output
input2 --->|1|    |     |
           |/     |     |
            |     |     |
enable -----+     |     |
clock1 -----------|>    |
                  +-----+

As you can see, if the enable line is low, Q is fed back to D, so Q is
held constant until enable=1.

This only works well if the logic feeding input2 is pretty simple, so
that it and the mux logic can be reduced to a single logic equation
that all fits in the same CLB.

Hope that helps,

-Paul
-- 
Paul Secinaro (pss1@christa.unh.edu)
Synthetic Vision and Pattern Analysis Laboratory
UNH Dept. of Electrical and Computer Engineering


Article: 2487
Subject: Free VHDL Simulator (demo version)
From: pellerin@seanet.com (David Pellerin)
Date: 15 Dec 1995 19:24:23 GMT
Links: << >>  << T >>  << A >>


Accolade Design Automation has just released a demo
version of its Personal Edition VHDL Simulator. This
demo version operates on Windows 3.1, Windows 95,
and Windows NT, and is fully functional, but limited
in design size. The demo version is perfect for those
wanting to learn enough about VHDL to be dangerous in
an interview, or for those evaluating VHDL as a design
alternative.

The demo version of the Personal Edition Simulator
supports 1076-1987, excluding configuration declarations,
and support for IEEE 1164 and IEEE 1076.3 (the numeric
standard) is included in supplied libraries. Synthesis-
oriented examples are also included, demonstrating such
things as how to describe a state machine, how to write
various types of test benches, etc.

The simulator uses 32-bit direct compile technology, so
Windows 3.1 users will need to download an additional
32-bit support library (OLE32s) in order to use the
simulator software.

The download file is over 4MB in length, but well worth
your time if you have any interest in learning VHDL.

The demo is available from the Accolade Design Automation
Web Site (http://www.accolade.com) or from our FTP site
at ftp.accolade.com (file vhdldemo.zip).

-- David Pellerin


   Accolade Design Automation
   206-788-3768
   http://www.acolade.com



Article: 2488
Subject: Re: Gated Clock Problem in Xilinx FPGA Implementation
From: peter@xilinx.com (Peter Alfke)
Date: 16 Dec 1995 01:00:47 GMT
Links: << >>  << T >>  << A >>
In article <4ap28p$8ke@netnews.nctu.edu.tw>,
ccchen@bluejays.EE.NCTU.edu.tw (Chih-Ching Chen) wrote:

> I have a design bases on pipeline architechure, and I want to implement it on
> Xilinx XC4000 FPGA. 
> Because the clock2 is gated clock-> (clock1 and other enable signal)
> so clock2 will get at least one CLB delay than clock1.

There is a simple solution: 
Do not gate the clock. Avoid clock gating like the plague.
Xilinx provides you with a clock enable input, use that instead, and you
have a true synchronous system without the hold-time problems that you
mention.

See page 9-12 of the Xilinx data book: 
...a synchronous signal can be used to gate the clock, but this introduces
an additional clock delay, which can cause hold-time problems".


Article: 2489
Subject: Re: Gated Clock Problem in Xilinx FPGA Implementation
From: tom@dilleng.wa.com (Tom Dillon)
Date: Sun, 17 Dec 95 09:00:22 -0800
Links: << >>  << T >>  << A >>

>I haven't worked with FPGAs, but how about instead of:
>
>clk1 <= clk;
>clk2 <= clk and enable;
>
>you use:
>
>clk1 <= clk and '1';
>clk2 <= clk and enable;
>
>To compensate for the CLB delay on clk2 (and specify a "don't touch" on the 
>clk1 assignment so it doesn't get optimized by your compiler).
>

This is not a good approach with Xilinx FPGAs because you can't guarantee which 
path(from clk to clk1 or clk to clk2) will have the longer delay. And it could 
change with each route you run. You can guarantee a maximum delay but never a 
minimum.

The only reliable approach is to do what others have suggested, use the built in 
clock enable on the FFs.

Good luck,

Tom Dillon
DILLON ENGINEERING
2017 Continental Place
Suite 5
Mount Vernon, WA 98273-5649
e-mail: tom@dilleng.wa.com
Voice : (360) 424-3794
FAX   : (360) 424-5894


Article: 2490
Subject: Re: Gated Clock Problem in Xilinx FPGA Implementation
From: Ray Andraka <randraka@ids.net>
Date: 18 Dec 1995 03:24:25 GMT
Links: << >>  << T >>  << A >>
pss1@hopper.unh.edu (Paul S Secinaro) wrote:

> If you don't have clock enables on your flops (like in Altera FLEX
> 8000), it can get ugly.  One approach is to place a 2-to-1 mux in
> front of the input of DFF2 and use the clock enable as the select
> line, like this:
> 
>        +------------------+
>        |                  |
>        |   |\             |
>        +-->|0|    +-----+ |
>            | |--->|D   Q|-+-----> output
> input2 --->|1|    |     |
>            |/     |     |
>             |     |     |
> enable -----+     |     |
> clock1 -----------|>    |
>                   +-----+
> 

Actually, in Xilinx 3K, this often a better solution than the CE 
provided in the CLB!  That is because the CE included in the CLB can
only be wired to one pin on the CLB, while the above solution can 
be implemented using any of several inputs to the CLB.  This can 
greatly improve routability of the device.  Of course, this logic uses
3 of the 4/5 inputs to the 3K CLB so that trade has to be considered.

-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930   FAX 401/884-7950
email randraka@ids.net
 
The Andraka Consulting Group is a digital hardware design firm specializing 
in high performance FPGA designs.  Services include complete design, development, 
simulation, and integration of these devices and the surrounding circuits.  We 
also evaluate,troubleshoot, and improve existing designs. Please call or write 
for a free brochure.



Article: 2491
Subject: Re: WAnted: correlator!!!!!
From: Ray Andraka <randraka@ids.net>
Date: 18 Dec 1995 03:42:35 GMT
Links: << >>  << T >>  << A >>
<javier@world> wrote:
>
> 
> Does anyone have implemented a digital binary correlator, complex, of 512 taps
> each channel, using a FPGA?
> 
How many bits are the coefficients?  I've done considerable amounts of work 
in bit serial signal processors in FPGAs.  I presented a paper in 1993
at the PLD conference and exhibit describing the design of a 27 tap filter
using 12 bit coefficients. Obviously, the design is the same as a correlator.
That design was real only; to get complex coefficients and a complex data 
input, you will need to use four of these and combine the results appropriately.
 
512 taps is a large number of taps to implement in a single part.  If your
coefficients are single bit (say you are looking for a pattern in a 
serial stream) it will fit, although the solution is trivial.

-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930   FAX 401/884-7950
email randraka@ids.net
 
The Andraka Consulting Group is a digital hardware design firm specializing 
in high performance FPGA designs.  Services include complete design, development, 
simulation, and integration of these devices and the surrounding circuits.  We 
also evaluate,troubleshoot, and improve existing designs. Please call or write 
for a free brochure.





Article: 2492
Subject: Re: WAnted: correlator!!!!!
From: Ray Andraka <randraka@ids.net>
Date: 18 Dec 1995 03:42:43 GMT
Links: << >>  << T >>  << A >>
<javier@world> wrote:
>
> 
> Does anyone have implemented a digital binary correlator, complex, of 512 taps
> each channel, using a FPGA?
> 
How many bits are the coefficients?  I've done considerable amounts of work 
in bit serial signal processors in FPGAs.  I presented a paper in 1993
at the PLD conference and exhibit describing the design of a 27 tap filter
using 12 bit coefficients. Obviously, the design is the same as a correlator.
That design was real only; to get complex coefficients and a complex data 
input, you will need to use four of these and combine the results appropriately.
 
512 taps is a large number of taps to implement in a single part.  If your
coefficients are single bit (say you are looking for a pattern in a 
serial stream) it will fit, although the solution is trivial.

-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930   FAX 401/884-7950
email randraka@ids.net
 
The Andraka Consulting Group is a digital hardware design firm specializing 
in high performance FPGA designs.  Services include complete design, development, 
simulation, and integration of these devices and the surrounding circuits.  We 
also evaluate,troubleshoot, and improve existing designs. Please call or write 
for a free brochure.





Article: 2493
Subject: Floor Planning for Xilinx
From: maya@asp.co.il (Maya Reuveni)
Date: Mon, 18 Dec 1995 14:59:23 GMT
Links: << >>  << T >>  << A >>
Hi all,
My question is about floor planning for Xilinx X4013.
I am working on a large design to be mapped into a
Xilinx XC4013 device. The design consists of 4 main
blocks; utilization is 55%; and target speed is 33 Mhz!

What is the way to control the placement of the blocks?
Does anyone have experience with the .cst file that
controls placement ("PLACE INSTANCE clb_r" etc)?
Does anyone have any tips for the grafical floor planner?

ANY responce  will be appreciated.

Thnaks,

Maya

-- 

    Maya Reuveni                                  Tel: 972-9-986976
    Manager of Hardware Department                Fax: 972-9-986980
    HaTaasiya 9, Raanana 43100, Israel.           E-mail: maya@asp.co.il




Article: 2494
Subject: UART in PLD
From: chuck@aeroastro.com (Charles P. Ohrbom)
Date: Mon, 18 Dec 95 16:02:57 GMT
Links: << >>  << T >>  << A >>
Hello,

I need to implement a UA(R)T, i.e. the transmitt portion only, in an Actel
PLD.  I will use a pin on a MC68332 as the UAR(T) receiver.  Does anyone
have a design they could pass along?

Thanks

Chuck Ohrbom
AeroAstro
chuck@aeroastro.com


Article: 2495
Subject: Re: UART in PLD
From: devb@katie.vnet.net (David Van den Bout)
Date: 18 Dec 1995 13:02:49 -0500
Links: << >>  << T >>  << A >>
In article <chuck.1169690217A@news.connectnet.com>,
Charles P. Ohrbom <chuck@aeroastro.com> wrote:
>Hello,
>
>I need to implement a UA(R)T, i.e. the transmitt portion only, in an Actel
>PLD.  I will use a pin on a MC68332 as the UAR(T) receiver.  Does anyone
>have a design they could pass along?
>

I have a design that fits in an 80-macrocell EPX780.  It's expressed
in PLDASM, but it should be easy to translate.  I keep the design
and the explanatory text at ftp.vnet.net in directory
pub/xess/FPGA_Workout_II.


-- 
|| Dave Van den Bout  --  XESS Corp. ||
|| 2608 Sweetgum Dr., Apex, NC 27502 ||
|| (919) 387-0076 FAX:(919) 387-1302 ||
|| devb@xess.com       devb@vnet.net ||


Article: 2496
Subject: Re: Floor Planning for Xilinx
From: Bill Clark <wclark@duat.clark.com>
Date: Mon, 18 Dec 1995 15:38:40 -0700
Links: << >>  << T >>  << A >>
Maya Reuveni wrote:
> 
> Hi all,
> My question is about floor planning for Xilinx X4013.
> I am working on a large design to be mapped into a
> Xilinx XC4013 device. The design consists of 4 main
> blocks; utilization is 55%; and target speed is 33 Mhz!
> 
> What is the way to control the placement of the blocks?
> Does anyone have experience with the .cst file that
> controls placement ("PLACE INSTANCE clb_r" etc)?
> Does anyone have any tips for the grafical floor planner?
> 
> ANY responce  will be appreciated.

Evidently you don't have V6 tools. Get em! They're shipping/shipped.
--
Bill Clark   Clark Associates., Inc.   wclark@clark.com   +1 303 444 
1890


Article: 2497
Subject: Re: Floor Planning for Xilinx
From: jackg@downhaul.crc.ricoh.com (Jack Greenbaum)
Date: 18 Dec 1995 22:51:10 GMT
Links: << >>  << T >>  << A >>
In article <DJsEyz.GoD@asp.co.il> maya@asp.co.il (Maya Reuveni) writes:
   My question is about floor planning for Xilinx X4013.
   I am working on a large design to be mapped into a
   Xilinx XC4013 device. The design consists of 4 main
   blocks; utilization is 55%; and target speed is 33 Mhz!

   What is the way to control the placement of the blocks?
   Does anyone have experience with the .cst file that
   controls placement ("PLACE INSTANCE clb_r" etc)?

You really don't want to place every single instance by hand in a design
that big (or any design really). Any change will ripple into hours of
work. What does work well and is less brittle (but certainly not without
it's faults) is using the RLOC, or Relative Location, feature of the
Xilinx tools. RLOCs are used to place chucks of logic relative to other
chunks. In that way you can control the placement of time critical
sections of your design without having to choose a particular CLB for
every resource. FMAPS, FFs, TBUFs, and carry logic can be placed
relative to each other from the schematic. The locations can be built up
hierarchically.

Given a group of logic tied together by RLOCs, you can choose a
particular die location by declaring an RLOC_ORIGIN if you feel you need
to help PPR even further. I think you could also put the RLOC_ORIGIN in
your .cst file, not sure on that one though. 



--
Jack Greenbaum -- Research Engineer, Ricoh California Research Center
---------------------------------------------------------------------
Digital: jackg@crc.ricoh.com   |  http://www.crc.ricoh.com/~jackg
---------------------------------------------------------------------
Analog:  (415) 496-5711 voice  |  2882 Sand Hill Rd. Suite 115
         (415) 854-8740 fax    |  Menlo Park, CA 94025-7002
---------------------------------------------------------------------
-- 
Jack Greenbaum -- Research Engineer, Ricoh California Research Center
---------------------------------------------------------------------
Digital: jackg@crc.ricoh.com   |  http://www.crc.ricoh.com/~jackg
---------------------------------------------------------------------


Article: 2498
Subject: Synplicity vs. Exemplar for ORCA - Which is better?
From: fink@post.tau.ac.il (Udi Finkelstein)
Date: Mon, 18 Dec 1995 23:02:40 GMT
Links: << >>  << T >>  << A >>
Hello everyone!

My company is planning to use a Verilog synthesizer with the AT&T ORCA
2Cxx FPGA family. We know of two Verilog synthesizers - Synplicity and
Exemplar.

1. What are the latest versions of these products?

2. Which is better? (In terms of resulting design size, resulting
design speed)

3. Any other considerations? (compilation speed, etc.)

thanks,
Udi




Article: 2499
Subject: CYPRESS WARP 2+ VHDL DEVELOPMENT SYSTEM
From: mc4519@mclink.it
Date: 19 Dec 1995 08:48:41 GMT
Links: << >>  << T >>  << A >>
I have a Warp 2+ system for PAL,PLD,FPGA (Cypress,MAX,QuickLogic). 

What do you offer?






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