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Messages from 3725

Article: 3725
Subject: Re: FPGA vs CPLD
From: markc@gibelet.nexen.com (Mark Christensen)
Date: 22 Jul 1996 09:49:28 -0400
Links: << >>  << T >>  << A >>


Realistically, I doubt you'll be able to get any current FPGA with any
real logic implemented within it to run at 100MHz. It's true, that you can
achieve 100MHz operation with internal register to register logic, but
not many designs I know only implement this. Perhaps if the only 100MHz 
operation you are looking for is an internal counter or something. You will
achieve your best timing by pipelining, but my experience has shown that a
"typical" large design can usually achieve anywhere from 25MHz to 40MHz operation
depending on the vendor and amount of time spent optimizing your design. Note that
100MHz operation is even a difficult goal with most ASIC designs, and they can
be optimized for speed.

CPLDs are more predictable and can be faster in some cases, but again, I doubt you'll
hit 100MHz as a general design rule. Do the math. Just look at your on-chip and off-chip
signal times, your register setup, etc. and you'll see precious nanoseconds eaten up, and
this doesn't even include your board delays and skews.

In article <1996Jul18.115255.6511@srs.gov>, Bryan Bushart <bryan.bushart@srs.gov> writes:
|> Marc Palmarini wrote:
|> > 
|> > Hi,
|> > 
|> > I'm currently working on a project wich involves very-high speed clock rate.  Over the 100 MHz.
|> > We're considering CPLD and/or FPGA.  From what I can see, and have been informed by several compagnies.
|> > CPLD offer less complexity, but more speed.  Is this right ???  Also, I'd like to know if anybody
|> > has had to work with different brand of CPLD/FPGA.  We've been looking at two brands, first there is
|> > the CYPRESS line, and then there's the the QuickLogic line (any comment/suggestion).  Are there any other
|> > lines that works at a higher than 100 MHz clock.  Typically our project needs to access RAM (Burst Technique)
|> > with acces to a peripheral (LCD Interface).  Wich will need to be able to calculate an Adress/Data from an
|> > (x,y) pixel position.  That is about all the job for the PCLD/FPGA.  I need at the very least 64 I/O line.
|> > 
|> >         Thanks in advance for any comments and/or suggestions.
|> > 
|> > --
|> > ============================================================
|> > Tel:(418)-871-8977                      Marc Palmarini
|> > Fax:(418)-871-9021                      ATI International
|> > 
|> > E-Mail:amphi_t@acica.com
|> 
|> Timing for CPLDs is deterministic and predictable however on FPGAs the
|> timing depends on the place and route.  Which will be faster depends on
|> the size of the design.  FYI there is no difference architecturally
|> between Cypress and Quicklogic FPGAs.  Another possibility is the FPGA
|> line from Actel.  If you need a reprogrammable FPGA you might want to
|> look at the ORCA line from Lucent Technologies (formerly AT&T).
|> 
|> ------------------------------------------------------------------------------------------
|> All opinions expressed is this message are my own and should not be
|> interpreted as representing the views of DOE or WSRC.
|> 
|> Bryan Bushart                       
|> Net: bryan.bushart@srs.gov
|> Phone:  (803)725-3472
-- 
Mark Christensen				       ascom-Nexion
email: markc@nexen.com				       289 Great Road
ph: (508) 266-2315				       Acton, MA 01720

Article: 3726
Subject: Re: Hardware sort?
From: ft63@dial.pipex.com (Peter)
Date: Mon, 22 Jul 1996 15:37:53 GMT
Links: << >>  << T >>  << A >>


> 
>I am using Xilinx XC4000 FPGAs for my design that has few increment and decrement
>by one and data bus is 8-bit integers. I was wondering whether there is any design that
>uses less resources of FPGA than 8-bit adder/subtractors to increment an 8-bit number
>by one. If there is such a method would anybody tell me what VHDL code infers this 
>hardware?

Consider this:

I once did a XC3064 design in which over 95% of CLB flip-flops were
utilised. Moreover, this routed using old 1991 APR software (in about
20 hours!). This design was almost entirely made up of counters.

Before and since, I have been doing "typical" designs and have never
got anywhere near this level of utilisation. 70% is typical before the
device won't connect-up, although when I recently bought XACT6 that
made a big improvement.

So, if you can do something with "counters" you will get a lot more
into a device than if you do it with random logic.

I would think that loading your number into an 8-bit loadable counter,
and then giving that one clock, would be a lot more efficient than
building an adder. With care, you could do the whole operation in 2
clocks.

Peter.
Article: 3727
Subject: Re: Xilinx library for autologic
From: Lance Gin <c43lyg@dso.hac.com>
Date: Mon, 22 Jul 1996 09:58:21 -0700
Links: << >>  << T >>  << A >>
Fernando Pardo wrote:
> 
> Hi,
> 
> I just installed the Xilinx kit for mentor graphics and I discovered
> that there
> is no Autologic synthesis library for Xilinx, is this an error?? I there
> a public domain Xilinx synthesis library for autologic??

yes, i recently discovered the same thing. they are available 
at mentor's ftp "supportnet" site. the last time i looked, they were 
located in the following directory:

/pub/mentortech/tdd/libraries/fpga

if you have any problems finding the library you need there, i would 
suggest calling your local mentor rep or the mentor directconnect line 
(if its available in europe). good luck.

-- 
_______________________________________________________________________
Lance Gin                                         "off the keyboard
Delco Systems - GM Hughes Electronics              over the bridge,
OFC: 805.961.7567  FAX: 805.961.7739               through the gateway,
C43LYG@dso.hac.com                                 nothing but NET!"
_______________________________________________________________________
Article: 3728
Subject: Xilinx XC6200 Information
From: Raj Patel <raj.patel@Xilinx.COM>
Date: Mon, 22 Jul 1996 18:19:45 GMT
Links: << >>  << T >>  << A >>

cgamrat@gaap.saclay.cea.fr (GAMRAT Christian) writes:

>Message: 3
>From: cgamrat@gaap.saclay.cea.fr (GAMRAT Christian)
>Date: 11 Jul 1996 12:19:29 GMT
>Subject: What about the XC6200 ?
>
>Is There anybody out there who knows anything new about the Xilinx
>XC6200 partially reconfigurable fpga ?  The data available from Xilinx
>has not changed for months and it looks like if they are not pushing
>the device ahead anymore.  I hope I'm wrong because this FPGA is a must
>in the field of reconfigurable computing. It will be really Dommage !
>Thanks for any info on that .
>Cheers,
>
>Christian.
>
>
>                                     (((((  
>                                    (     )
>                                   ( 0   0 )
>                                    (  !  )
>                                    | \_/ | 
> |------------------------------ooO---------Ooo-------------------------------|
> |   De/From Christian Gamrat (MIND-1024)                                     |> 
> |   Commisariat a l'Energie Atomique / Atomic Energy Commission              |
> |   Groupe Architectures Paralleles  / Parallel Computing Group              |
> |   DTA/LETI/DEIN/SLA/GAP                                                    |
>O|   CE-SACLAY  91191 Gif-sur-Yvette Cedex -  FRANCE                          |>O
> |   e-mail : cgamrat@gaap.saclay.cea.fr                                      |
> |   phone  : +33 1 69 08 71 94                                               |
> |   fax    : +33 1 69 08 83 95                                               |> 
> |----------------------------------------------------------------------------|



In response wolf@unconfigured.xvnews.domain (William J. Wolf) writes:

>Message: 1
>From: wolf@unconfigured.xvnews.domain (William J. Wolf)
>Date: 12 Jul 1996 12:13:28 GMT
>Subject: Xilinx reconfigurable logic strategy
>
>[was Re: What about the XC6200?]
>
>cgamrat@gaap.saclay.cea.fr (GAMRAT Christian) writes:
>>Is There anybody out there who knows anything new about the Xilinx XC6200 
>>partially reconfigurable fpga ?
>>The data available from Xilinx has not changed for months and it looks like if> they
>>are not pushing the device ahead anymore. 
>>I hope I'm wrong because this FPGA is a must in the field of reconfigurable 
>>computing. It will be really Dommage !
>
>William Roelandts (new Xilinx CEO) stated that developing recongifurable logic 
>with "the ability to change the logic configuration of the FPGA during the 
>operation of the device" is something that will be aggressively continued.
>Anyone from Xilinx care to expand on the details of this strategy?
>
>- -- 
>- - Bill Wolf, Raleigh NC
>- - My opinions, NOT my employer's



Also in response Andrew Morley <andym@trend.demon.co.uk> writes:

>Message: 2
>From: Andrew Morley <andym@trend.demon.co.uk>
>Date: Sat, 13 Jul 96 15:00:09 GMT
>Subject: Re: What about the XC6200 ?
>
>In article <4s2rgh$eba@news.cea.fr> cgamrat@gaap.saclay.cea.fr  writes:
>
>> Is There anybody out there who knows anything new about the Xilinx XC6200 
>> partially reconfigurable fpga ?
>...
>> I hope I'm wrong because this FPGA is a must in the field of reconfigurable 
>> computing. It will be really Dommage !
>
>Whilst it is an exciting offering, I don't see that it is that much more 
>radical than the Atmel CacheLogic parts.  Perhaps they don't feel that thay've 
>got anything to bring to the party?  I stand corrected if I am wrong.
>
>- -- 
> -----------------------------------------------------------------------------
>| Andrew Morley, Design & Development, Trend Communications Ltd, High Wycombe.|
>| email: andrew.morley@trendcomms.com  Phone +44 1628-524977        Bucks, UK.|
> -----------------------------------------------------------------------------



Gentlemen,

Please allow me to clear up some misunderstanding.

1)  I'm glad Mr. Gamrat feels that the the Xilinx XC6200 "is a must in
the field of reconfigurable computing." We at Xilinx couldn't agree
with him more. Please rest assured that the XC6200 is very much alive.
Information about the XC6200 on our WEB page is merely a glimpse of the
'architectural' benefits it provides the user. A complete datasheet is
available directly from Xilinx, upon request.

Currently, we are beta testing the software and sampling the silicon
under NDA. Completion of a thorough beta test program for the XC6200 is
a must before we release the product to the general market. I welcome
those who believe that this architecture is a significant milestone in
enabling reconfigurable logic applications, to participate in
evaluating the software and silicon.

2)  Mr. Wolf the details of W. Roelandts' Reconfigurable Logic strategy
will unfold over the next year. Please stay tuned!

3)  Mr. Morley the similarity of the Xilinx XC6200 with the Atmel Cache
Logic parts begins and ends with perhaps the granularity of the
devices. Both can be considered 'fine grain architectures'. Beyond this
the XC6200 is completely different than the Atmel devices.

a) The XC6200 is the first and only family of devices with a built in
processor interface that allows direct random access of configuration
memory as well as all the registers on the device. A must for
coprocessor applications!

b) The architecture supports partial dynamic reconfiguration down to
the individual cell level. Elements of a single cell can be configured
in as little as 40ns.

c) It is a completely "open architecture", ie. everything the user
needs to know to program and access the device is specified in the
datasheet. This open systems approach is a key for any kind of
'computing' to take off. We feel this is also important for the 3rd
party design tool market to take off.

d) Configuration times for this architecture are faster than any other
architecture (for equivalent gate densities) by orders of magnitude.

e) Family includes devices ranging in gate densities from 9K gates up
to 100K gates.

f) Its the only architecture which can accept completely random bit
streams without causing damage to the chip (has anyone had their CPU
run off and write in areas of memory that it wasn't supposed to? how
does one guarantee a non-random bit stream in such cases?)

This is but a short list of the differentiating features. We believe
the XC6200 architecture with its host of new and innovative features
will be "Changing the Rules of System Design".

A year ago we announced the "architecture" but most people read it as a
"device" announcment and so expected the product to be released
shortly. When the products did not start to appear, it was felt that
the XC6200 was "slipping" or "not being pushed ahead anymore". In the
meantime, work on the XC6200 family continues on or ahead of schedule
and early indications are that this family will be a clear winner.



*********************************************************************
*   _   _                                                           *
*  / /\/ /                                                          *
*  \ \ \/	Raj Patel		XC6200 Product Line Manager *
*   \ \		Xilinx			email:raj.patel@xilinx.com  *
*   / /		2100 Logic Drive	(408)879-4928 Tel           *
*  / / /\	San Jose, CA 95124-3450	(408)879-4780 Fax           *
*  \_\/\_\                                                          *
*                                                                   *
*********************************************************************



----- End Included Message -----

Article: 3729
Subject: Atmel AT17Cxxx EEPROMs
From: * Atmel FPGA Apps * <martin@atmel.com>
Date: Mon, 22 Jul 1996 18:34:14 GMT
Links: << >>  << T >>  << A >>

>Klaus_Leiss@ccl.lhag.de (Klaus-Guenter Leiss) writes...

>I used information downloaded in march from www.atmel.com. After 
>your last message i downloaded the information again. New File, larger 
>than the old ( it now contains also information for in circuit 
>programming), and as you stated the information regarding the polarity 
>fuse is now inverse to the old. After trying it with the new 
>information all went correct and i could also programm the polarity 
>fuse and not only the data block. Somewhere in an older thread someone 
>stated that Atmel changed the default polarity of its reset/oe fuse, 
>maybe at this time they changed also the programming algorithm.
> 

Atmel has not changed the default Reset polarity or the device 
programming algorithim. The current on-line documentation available at 
http://www.atmel.com or Fax-on-Demand 1-800-29-ATMEL (Docs #602 & #603) 
is now up-to-date.

Samples of the device can also be obtained through Atmel's home page.

Technical questions can be sent to configurator@atmel.com

Martin Mason.

-------------------------------------------------------------------------
|       Martin Mason            | Snr FPGA/17Cxxx Applications Engineer |
|       Atmel Corp.             | (email - me)         martin@atmel.com |
|       2325, Orchard Parkway   | (email - help)         fpga@atmel.com |
|       San Jose                |                configurator@atmal.com |
|       CA 95131    USA         | (Tele)        + (408) 436 4178        |
|                               | (Fax)         + (408) 436 4300        | 
-------------------------------------------------------------------------
|Need Atmel Lit. stuff ?  WWW.ATMEL.COM or FAX-on-DEMAND 1-800-29-ATMEL | 
-------------------------------------------------------------------------
Article: 3730
Subject: I NEED HELP!!!!
From: Corporate1@notes.techni-source.com (Technisource)
Date: 22 Jul 1996 19:48:07 GMT
Links: << >>  << T >>  << A >>
SORRY TO BOTHER YOU GUYS.  I AM LOOKING FOR A ASIC DESIGNER WITH CELL3 OR 
CELL ENSEMBLE EXPERIENCE.  FOR A JOB IN FLORIDA.  THIS JOB WILL PAY VERY, 
VERY WELL FOR SOMEONE WITH THIS EXPERIENCE.  IF YOU HAVE THIS SKILL OR 
KNOW SOMEONE WHO DOES, PLEASE LET ME KNOW ASAP.  I WILL PAY A REFERRAL 
FEE FOR THE RIGHT FIT.  PLEASE CALL AT 800-940-9401 OR E-MAIL 
vvirga@notes.techni-source.com.  Thank You.

Article: 3731
Subject: Daisychain or SPROM?
From: Wilwert Marc <marc.wilwert@crpht.lu>
Date: Mon, 22 Jul 1996 13:21:36 -0700
Links: << >>  << T >>  << A >>
Hi,

 I will use two XC3064 FPGAs in a design in slave serial mode. What is 
the better approach to configurate the FPGAs: daisychain or by using 
a separate SPROM for each FPGA? By using the devices in daisy chain is it 
possible to download the configuration bit stream via the xchecker? 
Otherwise if i use the separate SPROMs, what about synchronistion 
problems?


						Thank you for reading.

						Marc 


Email: wilwert@crpht.lu
Article: 3732
Subject: ### 7 Quick Multiple Choice Questions ###
From: jcooley@world.std.com (John Cooley)
Date: Mon, 22 Jul 1996 21:21:28 GMT
Links: << >>  << T >>  << A >>

 I've had four users independently suggest that I do an anonymous survey
 of engineers to see what we, as a group, think about these issues.  As
 usual, I'm only interested in your answers, not who you are (other than
 the fact that you use these EDA tools) -- so your replies will all be
 treated as ANONYMOUS.  Please reply *on* or *before* this Thursday,
 July 25th (three days from now) to "jcooley@world.std.com" so I can get
 this quickly tabulated and written up.
                                           - John Cooley

 P.S. After answering each specific question, please feel free to add
 your own anonymous comments on what the question addresses.


  0.) Please indicate how Place & Route (P&R) tools affect you.  Choose:

          [  ] I use them directly in my work.
          [  ] I support other engineers using P&R tools.
          [  ] I don't use P&R tools, but use related EDA tools for
               IC design like synthesis, etc.
          [  ] I develope/sell EDA tools.
          [  ] I don't use or support or make any EDA tools.

      Comments:

  1.) "As an engineer, I believe that the American legal system is generally
       capable of rendering justice in technically complex lawsuits."
       Please answer TRUE or FALSE:___________

      Comments:

  2.) "As an engineer, if I were the judge in the Cadence/Avant! lawsuit,
       I ( WOULD / WOULD NOT ) grant Cadence's Sept. 11 request for an
       injuction to prevent the further sales of Avant! products that are
       alleged to contain Cadence technology."  Please choose WOULD or
       WOULD NOT:____________________

       Comments:

  3.) "My primary sources of info on the Cadence/Avant! lawsuit came from
       (please "X", at most, your top 3 three sources):

                [  ]  EE Times
                [  ]  Internet discussions
                [  ]  opinions heard at conferences
                [  ]  opinions from co-workers
                [  ]  opinions from boss/management
                [  ]  direct interactions with Cadence
                [  ]  direct interactions with Avant!
                [  ]  other (please specify) _____________________

      Comments:

  4.) "Because of this lawsuit, I am (MORE LIKELY / LESS LIKELY / UNCHANGED)
       to do business with Cadence."  Please choose MORE LIKELY or LESS
       LIKELY or UNCHANGED:___________________

      Comments:

  5.) "Because of this lawsuit, I am (MORE LIKELY / LESS LIKELY / UNCHANGED)
       to do business with Avant!."  Please choose MORE LIKELY or LESS
       LIKELY or UNCHANGED:___________________

      Comments:

  6.) "Because of this lawsuit, I am (MORE LIKELY / LESS LIKELY / UNCHANGED)
       to do business with other P&R vendors."  Please choose MORE LIKELY or
       LESS LIKELY or UNCHANGED:___________________

         [ Other P&R vendors: Agape, Cascade, Compass, Cooper & Chyan,
           Fujitsu, Gambit, IBM EDA, Mitsubishi, Mentor Graphics,
           Sagantec, Sieko, Snake, SVR, Tanner, Timberwolf, VeriBest. ]

      Comments (& What Other Vendors In Particular?):


Thanks for taking the time to answer this survey.

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 4599 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3733
Subject: Designing Dual Port RAM with 4000 series.
From: hajimow@engn.uwindsor.ca (Hajimowlana Sayed )
Date: Mon, 22 Jul 1996 22:51:19 GMT
Links: << >>  << T >>  << A >>
	I am using Xilinx 4000 series and I want to design a dual port RAM. I have 
got an application note that shows how to design it with 4000E series that CLBs are
edge triggered.Now my question is how should I change that design in order to use 4000 series instead.Basically If I be able to make RM 16x1S that is available in 4000E libraries by RM 16x1 that I have in 4000 libraries now, my problem is solved.
Any comment is highly appreciated.



---
Sayed-Hossain Hajimowlana   Dept. Of Elec. Eng.
Office:Essex Hall Rm-213    Phone-ext:2590
Univ. of Windsor            Home:253-9741



Article: 3734
Subject: Re: What does the timing report from Synthesizer mean?
From: lllapides@aol.com (Lllapides)
Date: 22 Jul 1996 20:16:23 -0400
Links: << >>  << T >>  << A >>
Felix K.C. CHEN asked about timing report from synthesis
tools.  In the Exemplar Logic Galileo tools, speed grades
are set in the Output Options window for those technologies
that have them.  For those that don't, the Synthesis Options
window contains options for degrading delay based on 
voltage, temperature and process.  

And as another poster mentioned, these delay numbers are 
estimates.  In the spirit of any information is better than
none at all, delay estimates can actually be helpful in the
design flow.  

Larry Lapides
Antares Corporation
larry_lapides@antaresco.com
***  Exemplar Logic synthesis, Model Technology simulation  ***
Article: 3735
Subject: Re: Daisychain or SPROM?
From: fliptron@netcom.com (Philip Freidin)
Date: Tue, 23 Jul 1996 05:42:37 GMT
Links: << >>  << T >>  << A >>
In article <31F3E2D0.400B@crpht.lu> Wilwert Marc <marc.wilwert@crpht.lu> writes:
>Hi,
>
> I will use two XC3064 FPGAs in a design in slave serial mode. What is 
>the better approach to configurate the FPGAs: daisychain or by using 
>a separate SPROM for each FPGA? By using the devices in daisy chain is it 
>possible to download the configuration bit stream via the xchecker? 
>Otherwise if i use the separate SPROMs, what about synchronistion 
>problems?
>						Thank you for reading.
>						Marc 
>Email: wilwert@crpht.lu

If you have two XC3064s to configure serially, and plan to use the SPROMS,
then they wont both be in slave mode. The lead device will be in master
mode. 

You can load two devices in daisy chain with XCHECKER (in which case, both
will be in slave serial mode). Use makeprom to make a combined bitstream 
file, and write it out in .TEK, .MCS, or .EXO format. XCHECKER can work 
with any of these.

If you put both parts in master mode, each with its own SPROM, then they 
will configure independently, and as they will use their own internally 
and non identical clocks, the devices will not go done at exactly the 
same time. If your system depends on both chips going done at the same 
time, then daisy chain is a better possibility. With both parts in serial 
slave mode, you could provide an external cclk to both parts which would 
then cause them to complete at the same time (because they are both the 
same type of chip), but you can't use a free running clock, because cclk 
cant start to have transitions untill about 6 uS after the init pin goes 
high.

If both chips are the same design (you didn't say), then you only need one
copy of the program. Feed the bit stream to both chips at the same time,
with one chip in master mode and the other in slave mode. Both will
complete at the same time (because you also tied the cclk pins together).
This will also configure in half the time which is almost always
irrelevant. 

What I usually do is build the board to take both the XCHECKER (or my much
faster and less capable parallel download cable) and what ever the system
is suposed to use in production (SPROM or host load), with a jumper that
changes the mode appropriately, and also flips a mux over for the source
of data and cclk. Debug with jumper in, production with jumper out. 

Enjoy,
	Philip Freidin.
Article: 3736
Subject: Cheap/free fpga/cpld software
From: jperry@norfolk.infi.net (John Perry)
Date: Tue, 23 Jul 1996 06:10:47 GMT
Links: << >>  << T >>  << A >>
Thanks to all who replied.  This is going to help a lot.  As promised,
here's the summary of replies, followed by my own results (or, more 
accurately, non-results so far :-).

***********************************************************************

From: "J.Mawer" <j.mawer@sheffield.ac.uk>
AMD palasm is now freeware, used to be a couple of hundred I think.
This will do Mach devices upto MACH 230 as well as "ordinary" PLDs,
you can get a copy from their web site.

Mach XL 2.1 is also avaliable on their web site which can be used with
upto Mach 465.

Further information http://www.amd.com/html/products/pld/pld.html

*********
From: Andreas Kugel <kugel@uni-mannheim.de>
cplds: mach-xl from amd for their mach chips, free. www.amd.com
cplds: ispLSI starterkit from lattice for the smaller ispLSI chips,
free
(or low cost). www.lattice-semi.com
fpgas: motorola mpa devices (=pilkington fpgas), free place and route,
free interfaces. front end tool may be self developed. www.pmel.com

*********
From: Paul Walker <paul@walker.demon.co.uk>
Best is PLDSHELL from Altera. Snap it up while it is still free and
before it is subsumed into their other tools. They charge a little for
the JTAG cable and the devices are quite expensive. But the tool lets
you work on devices of any size, and the devices are quite nice,
particularly the flash EPX880.

*********
From: Gareth Jones <gareth@pmel.com>
I saw your message on comp.arch.fpga, we (Pilkington
Micro-electronics) 
provide free place and route tools for all our programmable
technologies. 
Our FPGA's are currently sold under license by Motorola as the MPA1000

series devices. You can download the tools from our website
(www.pmel.com) 
this site also has links to Motorola's site which contains information
on 
device availability/pricing.

The free version of the tools are fully featured but will only support

devices up to 8000 gates. They contain free libraries for a wide range

front end tools. An upgraded version of the tools supporting up to
22000 
gate devices is available from Motorola.

*********
From: wolf@aur.alcatel.com (William J. Wolf)
>From previous consulting/contract experience:

CPLD software is generally easy to get.  FPGA software is a 
little tougher.  Few customers need support for CPLDs.  You 
will probably find more consulting/contract opportunities 
with FPGAs.  Take a survey of local/regional customers to see
which FPGAs they use, prior to investing a lot of time.

Altera seemed more willing than Xilinx to give away software.
This may depend on how well established you are, or their need 
for local support from third parties.

Consider becoming a certified Xilinx trainer.  This provides  
several benefits;  another source of (modest) income, access 
to software, and bragging rights with customers.  It does take 
a considerable investment in your time up front, with no guarantee 
that you will be "certified" and used.  Xilinx provides honest 
feedback as you go to give you both a chance to bail.  This only 
makes sense if you are serious about FPGA design, good, possess 
skills helpful in training, and are willing to travel to teach 
classes. 

*********
From: Ilpo Hamunen <ilpo@dna.fi>
John, take a look at Lattice's homepage at

http://www.latticesemi.com

They have CD which is including a very nice piece of PLD software:
Data I/O Synario Starter kit

It will only support a limited number of devices, as the other
packages that you have found, but it's for free and it's good !

ISP Synario Starter System software supports Lattice's ispLSI 2032 and
1016 high-density devices and all Lattice GAL devices. The software
can
be easily upgraded to support all or part of Lattice's high-density
families.

1016 is a 44-pin, 64 macrocell device and 2032 also 44 pins but 32
MCs.

The CD has also a lot of valuable documentation.

*********
From: hjp@ee.umr.edu (Hardy Pottinger)
Try PLDShell if you can still get it.  Intel provided it for their
FX780 series and Dave Van den Bout of Xess has a nice book out on
it (FPGA Workout).  Try
ftp://ftp.vnet.net/pub/users/xess/FPGA_Workout_II/HTML/fpgawk2.htm
Altera has it now and I don't know if they're going to support it or
not or if it's even available.  It was free so you may be able to find
a copy in an archive somewhere.  It's basically PALASM on steroids.

*********
From: devb@vnet.net
XESS Corp. sells low-cost CPLD hardware and software.  You can  check
our WEB site: www.xess.com.  

You might also get a free copy of PLDSHELL from ALTERA.  It supports
a lot of their smaller PLDs and the EPX780 and 8160 CPLDs.  Just call
(408) 894-7144 for a free copy.



***********************************************************************

I looked at the Motorola site, and the 14MB size was too much for my 
serial access! so I left the requested form for the free CD-rom, and 
am waiting for that.

I also will order the Lattice CD-rom for $14.95 (I think that's the
price
 -- I'll have to look it up again).

I downloaded AMD's Machxl, and tried to ignore the silly procedure 
they
give in the readme (copying from hard disk to floppy so I can install
to
the hard disk?!?!?), and the install procedure instantly jumped to the

end screen when I started the install step.  So I painfully copied all

that stuff onto four floppies, and the exact same thing happened. By 
that time I was so exasperated I quit and didn't try PALASM, which has

the same instructions.

Anyone know what's wrong? I'm using a standard 486-40 with a Syquest 
EZ-Drive.

I couldn't find PLDshell or any reference to it at Altera's web site, 
so I suppose devb's (is this Dave Van den Bout?) phone number is the
way to get it.

I'll check out Xess in the next few days.  If anyone wants to hear my 
results, let me know.  You can do it yourself, though.



Article: 3737
Subject: altera -> xilinx
From: Anton Scherer <ascherer@htl-bw.ch>
Date: 23 Jul 1996 12:07:10 GMT
Links: << >>  << T >>  << A >>
We have two altera-designs we want to fit into xilinx devices.
The first design is in Altera-HDL (.tdf-files) and the other design is
written with PD-Shell (one .pds-file).
We are working with Mentor Graphics Tools, Maxplus2 Version 6 and XACTstep 5.2 on Sun Sparc
Station (SunOS 4.1.3).
I tried to write an EDIF-netlist with the altera-tool (.edo) 
and to read it in the Synthesis-Tool of Mentor Graphics. But I had some problems with 
the Altera delay-Cells in the edif-out-netlist.

Is there a apropriate way to "translate" the altera-design to xilinx.
I heard that there is a way with Exemplar but we do not have Exemplar.

Anton Scherer
Microswiss-Zentrum Nord-Sued
Switzerland


Article: 3738
Subject: Information on Actel
From: fnt003@zx2.HRZ.Uni-Dortmund.DE (Dipl.-Ing. D. Lenz)
Date: 23 Jul 1996 13:30:43 GMT
Links: << >>  << T >>  << A >>
Hi,

I gathered for Information about Actel, and what suprising, I got all Info
which I asked for in about 2 weeks!
Simply go to www.actel.com an request for Databooks and Demo-CD's.
The Books are very interesting and easy to read...
By this I've no points to be dissatiefied.

Hope, this will help you

Dominik
Article: 3739
Subject: Mentor->XC3064
From: Wilwert Marc <marc.wilwert@crpht.lu>
Date: Tue, 23 Jul 1996 09:12:54 -0700
Links: << >>  << T >>  << A >>
Hi,

   By using Autologic II, we tried to synthesise a design to map it on a
Xilinx 3064 FPGA. Because this family doesn't support XBLOX we have
synthesise the design by setting the Macro mapping switch to NONE.

However, Autologic II still generates XBLOX like :INC_16U_16U...,
GT_16U_16U.... etc.

The Xact PPR tool aborts with the message XBLOX not supported by the 3000
family.

Is there anybody who can give us a very good hint to resolve this
problems.


                                        Thanks to reading this news,
                                        Thousands thanks to reply.


                                                Marc & Gilbert
Article: 3740
Subject: CFP: Evolutionary Electronics (resend)
From: monty@watson.open.ac.uk (Tony Hirst)
Date: Tue, 23 Jul 1996 16:22:07 GMT
Links: << >>  << T >>  << A >>
*****************************************************************
        1st On-line Workshop on SOFT COMPUTING (WSC1)
             August 19 (Mon.) - 30 (Fri.), 1996

                  Special Session on

       EVOLUTIONARY ELECTRONICS
               
*****************************************************************

                    Call for Papers and 
         Invitation to take part in the Discussion
        
*****************************************************************

As part of the 1st on-line workshop on soft computing, we call for papers
for the special session on 'Evolutionary Electronics'. The session is
intended as a forum for discussing the use of evolutionary computing
techniques in electronics design and manufacturing, and the application of
reconfigurable logic as the medium for the rapid prototyping of (evolved)
digital logic designs.

The session welcomes survey  and tutorial style papers.
The areas of interest include but are not limited to :

        a. Evolving anlogue circuits
        b. Intrinsic/extrinsic evolvable hardware
        c. VLSI placement, routing and testing using evolutionary
algorithms
        d. Hardware implementations of evolutionary algorithms
        e. Evolutionary co-design
        f. Embryonics
        g. Implicit fault tolerance afforded by evolutionary design
        h. Field programmable gate arrays
       (i.  Hardware implemented neural networks)

The contributions can be in the form of :

     a) 6 page (max) Original paper, to be published in the workshop
proceedings. In the case of survey or tutorial style papers authors are
encouraged to submit the paper in several parts (such as part I and part II
with the same title).
     b) 6 page (max) paper on your already published work 
     c) YOUR PARTICIPATION in the discussion during the workshop

PLEASE NOTE: 
The DEADLINE FOR SUBMISSION of abstracts and main text is Aug. 5, 1996
WSC1 will accept  both  ORIGINAL and ALREADY PUBLISHED papers  (in
electronic form). It is intended that original papers will be published in
the conference proceedings.
Please refer to the ORIGINAL CALL FOR PAPERS below for the submission and
further details.
To submit  a paper  for the  special session, use  the same submission
procedure as for the WSC1 workshop, but, please, CLEARLY INDICATE THAT YOUR
PAPER IS FOR THE SPECIAL SESSION ON EVOLUTIONARY ELECTRONICS.

For any queries about the special session (only) please send email to:
    a.j.hirst@open.ac.uk
    http://kmi.open.ac.uk/~monty/evolelec.html

To contact the WSC1 organisers:

   http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/

==============================================================
                    ORIGINAL CALL FOR PAPERS
===============================================================
 This is the preliminary CFP for the 1st Online Workshop on Soft Computing.
This is also available on WWW. The URL is

    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/

        CALL FOR PAPERS

     The 1st Online Workshop on Soft Computing (WSC1)

         Aug. 19 (Mon) - Aug. 30 (Fri)

    On Internet (WWW (World Wide Web) ) Served by Nagoya University

 We call for your papers for online discussions using the Internet. The
purpose of this workshop is to give its attendees opportunities to exchange
informaiton and ideas on various aspects of Soft Computing and "save travel
expenses" without having to visit foreign countries.
We aim to have ample discussion time between the authors and attendees make
them visible to everyone on the Internet.

 This is the 3rd workshop of On-line Workshop series on Internet. The first
on-line workshop(WEC1) was held on Oct. 9 - 20, 1995. In spite of the very
short preparation time ( 2 weeks ) for the workshop, 22 papers were
submitted and great many people visited the home page:
    http://www.bioele.nuee nagoya-u.ac.jp/wec

 Encouraged by the unprecedented repercussions, we held the second on-line
workshop(WEC2) on March 4 - 22, 1996. More people showed great interest
into the workshop. You can still visit the home page at:

    http://www.bioele.nuee.nagoya-u.ac.jp/wec2

 The scope of the 3rd on-line workshop is expanded from those of the
preceding workshops. We call for your papers on Soft Computing. The great
merit of this workshop series is that you can save travel expenses without
having to visit and attendees and make them visible to everyone on the
Internet.

 The WSC1 will welcome original contributions. The proceedings is planned
to be published. We all look forward to your active participation.

TOPICS:
 Fuzzy Logic
 Neuro - Computing
 Genetic Computing
 Probabilistic Reasoning
 Chaos Computing
 Hybrid Systems

IMPORANT DATES:
 Deadline for Submission of Abstracts and Main Text: Aug. 5, 1996
 Opening the papers to the public:                   Aug. 12, 1996
 Workshop Weeks:                                     Aug. 19-30, 1996

SUBMISSION PROCEDURE:
 Send an abstract and main text to the address below.

    mail address is : wsc@bioele.nuee.nagoya-u.ac.jp

   The abstract should be in text file. The main text should be in text
file or in ps ( PostScript ) file. The size of the paper should be either
A4 ( metric ) or letter size. Papers should be written in Times or similar
font style, 10 points or larger with 2.5 cm margins on all four sides. If
you write your paper with LaTeX, you can use "IEEEtran.sty" and
"wscsample.tex" which is available from
    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/form/IEEEtran.sty
    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/form/wscsample.tex

   Another alternative is that if you prepare a WWW page for your main
text, please send us only the abstract and tell us the Internet address (
URL ), and yours will be linked to our WWW page.

   The steering committee will make your abstracts visible on the Internet.
The home page address is:

    URL: http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/

  *Note:
    This workshop will accept papers both original and already published.
If your paper is not original, please clarify the source of your paper.
Your paper will not be included in the proceedings.

    If your paper is an original one, you need to send ps file or camera -
ready manuscript of your main text. The paper should not exceed 6 pages in
length. Please also send us the copyright form by 
postal mail or facsimile. The proceedings including your original
contribution will be published. The copyright form is available also from
    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/form/copyright.ps
    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/form/copyright.txt

DISCUSSION PROCEDURE:
 1. Read the abstracts.
 2. Copy the main texts ( ps files ) of interested papers.
 3. Send questions and comments to
    wsc@bioele.nuee.nagoya-u.ac.jp
 (The steering committee will send the questions to the authors and receive
answers from the authors, and make the Q&A visible on the Internet.) 
 4. Read the answers from the authors on
    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/
 5. Repeat the above steps 3 and 4 until you are satisfied.

OFFICIAL LANGUAGE: English
 (Notice should be made that the main texts in ps files should not include
any fonts other than English.)

 For further information, contact:
    Takeshi Furuhashi
    Dept. of Information Electronics
    Nagoya University,
    Furo-cho, Chikusaku
    Nagoya 464-01, Japan
    Tel. +81-52-789-2792
    Fax. +81-52-789-3166


        Paper Submission Form
Title :
Authors :
Affiliation :
Address :
Phone :
Fax :
e-mail :
Source(if your paper is already published):
Keywords :
Link(if you have a WWW home page of the paper) :
Abstract :

Article: 3741
Subject: Job posting
From: Daniel Payne <daniel_payne@mentorg.com>
Date: Tue, 23 Jul 1996 10:04:40 -0700
Links: << >>  << T >>  << A >>
THE COMPANY
Established in 1981, Mentor Graphics Corporation (NASDAQ:MENT) designs, 
manufactures, markets and distributes electronic design
automation (EDA) software and provides professional services supporting 
its customers' complete design environments. The company is a
leader in worldwide EDA sales, with revenues of $440,714,000 over the 
last reported 12 months. Mentor Graphics is the first EDA vendor to
win the STAR (Software Technical Assistance Recognition) award, and the 
only EDA vendor to win the award twice. The award is given
annually by the Software Support Professionals Association (SSPA) for 
service excellence. The company currently employs approximately
2,400 people worldwide. In addition to its corporate offices, Mentor 
Graphics has sales, support, software development and professional
services offices worldwide. The company's headquarters are located at 
8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World
Wide Web site: http://www.mentorg.com. 

TECHNICAL MARKETING ENGINEER
Design Creation Products

DUTIES/RESPONSIBILITIES
Provide worldwide technical field support for MGC's new line of 
Windows-PC based design entry products.  Develop and deliver product 
demonstrations, support customer visits, gather customer requirements, 
work with engineering to design/enhance products, develop and deliver 
quarterly AE training, support tradeshows, workshops and seminars.  
Develop and deliver technical papers, applications notes and technical 
articles.

QUALIFICATIONS:  EDUCATION, EXPERIENCE, SKILLS, ETC.
The ideal candidate will have: a BSEE with 2-3 years experience with 
Windows based PC EDA applications;2-3 years of Top Down hardware design 
experience with FPGA or ASICs using schematic and HDL based design 
techniques; Excellent oral and written skills;  Experience with 
Client-Server applications using UNIX-Windows products a plus. 1-2 years 
of field applications experience highly desirable.   	

Contact: John Huber, 503/685-1372, john_huber@mentorg.com
Article: 3742
Subject: Re: Designing Dual Port RAM with 4000 series.
From: peter@xilinx.com (Peter Alfke)
Date: Tue, 23 Jul 1996 10:35:01 -0700
Links: << >>  << T >>  << A >>
In article <DuyvHJ.50J@news.uwindsor.ca>, hajimow@engn.uwindsor.ca wrote:

>         I am using Xilinx 4000 series and I want to design a dual port RAM.

Pelase don't even try to do that. 
The XC4000E has additional hardware ( transistors ) that facilitate
dual-port RAM operation. The XC4000 does not. If you need true dual port
RAM operation, use the XC4000E. As a bonus, it is also cheaper than the
equivalent XC4000.
Yes, you can fake a dual-port RAM in XC4000 by time-division multiplexing
a RAM, but that awkward method is now meaningless since the XC4000E is
available.

Peter Alfke, Xilinx Applications
Article: 3743
Subject: Re: Mentor->XC3064
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 24 Jul 1996 03:30:39 GMT
Links: << >>  << T >>  << A >>
In article <31F4FA06.C68@crpht.lu> Wilwert Marc <marc.wilwert@crpht.lu> writes:
>Hi,
>
>   By using Autologic II, we tried to synthesise a design to map it on a
>Xilinx 3064 FPGA. Because this family doesn't support XBLOX we have
>synthesise the design by setting the Macro mapping switch to NONE.
>However, Autologic II still generates XBLOX like :INC_16U_16U...,
>GT_16U_16U.... etc.
>The Xact PPR tool aborts with the message XBLOX not supported by the 3000
>family.
>Is there anybody who can give us a very good hint to resolve this
>problems.


If this is a new design you might want to consider an XC3064A or XC3164A,
which I think (but am not sure) is supported by XBLOX.

Good luck,
	Philip

Article: 3744
Subject: Re: Designing Dual Port RAM with 4000 series.
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 24 Jul 1996 03:40:21 GMT
Links: << >>  << T >>  << A >>
In article <DuyvHJ.50J@news.uwindsor.ca> hajimow@engn.uwindsor.ca writes:
> I am using Xilinx 4000 series and I want to design a dual port RAM. I
>have got an application note that shows how to design it with 4000E series
>that CLBs are edge triggered.Now my question is how should I change that
>design in order to use 4000 series instead.Basically If I be able to make
>RM 16x1S that is available in 4000E libraries by RM 16x1 that I have in
>4000 libraries now, my problem is solved. Any comment is highly
>appreciated. 
>Sayed-Hossain Hajimowlana   Dept. Of Elec. Eng.

The fully synchronous dual port RAM can not be emulated with the RAM in 
the XC4000. Dual Port is a primitive, like an AND gate. i.e. if all I 
have is AND gates, how do I emulate an inverter?

If you are running your system at a reasonably slow clock rate (10 MHz or
less), then you could build a memory that supported multiple ports by time
multiplexing them with a faster clock within 1 cycle of your system clock
cycle. You will still have to face the challenges of creating a valid 
write pulse within a stable window of address and data. You need to read 
the application data in the data book, on page 8-127 thru 8-147.

good luck
	Philip Freidin.


Article: 3745
Subject: Looking for an Eval Board for XILINX
From: Bryan Harstad <bharstad@minn.net>
Date: Tue, 23 Jul 1996 20:48:39 -0700
Links: << >>  << T >>  << A >>
I am just starting to look into VHDL, and
I am having a hard time locating any kind
of evaluation board/software with a Xilinx
fpga, and some inputs/outputs.  

Does anyone know where I can buy one from?

I don't really care what family of Xilinx,
but I would prefer something in the 4000 line.
-- 
+----------------------------------+
|     mailto:bharstad@minn.net,    |
|          Software Geek           |
|  Mispellers of the world UNTIE!  |
|                                  |
|Looking for something to do in MN?|
|  http://www1.minn.net/~bharstad  |
+----------------------------------+

Article: 3746
Subject: Re: Hardware sort?
From: peter@xilinx.com (Peter Alfke)
Date: Wed, 24 Jul 1996 11:45:45 -0700
Links: << >>  << T >>  << A >>
In article <Duv0nH.F9M@news.uwindsor.ca>, safiri@engn.uwindsor.ca wrote:

I was wondering whether there is any design that
> uses less resources of FPGA than 8-bit adder/subtractors to increment an
8-bit number by one.

If you run at high speed (10 to 100 MHz ) or if you use only a few of
these incre/decrementers, then the XC4000 or XC4000E will give you the
most economical solution ( 2 bits per CLB ). 

If you are slow and also have many of these functions in the same chip,
you could use serial arithmetic with the data stored in the small RAMs,
and you would only need 2 CLBs per 16- or even 32-bit incre/decrementer (
plus a few common overhead CLBs ). There are some scientific
instrumentation applications that thus can take advantage of distributed
RAM, but it means that you need n clock ticks to operate on an n-bit word.
Cute, but too slow for most applications.

Peter Alfke, Xilinx Applications
Article: 3747
Subject: Does XACT(ver5.2) support 4000E series?
From: hajimow@engn.uwindsor.ca (Hajimowlana Sayed )
Date: Wed, 24 Jul 1996 19:27:54 GMT
Links: << >>  << T >>  << A >>
Hi;

	Does Xact (ver5.2 support 4000E series? I didn't find it in its library.

Thanks

Article: 3748
Subject: Re: Does XACT(ver5.2) support 4000E series?
From: Scott Kroeger <Scott.Kroeger@mei.com>
Date: Wed, 24 Jul 1996 21:55:22 +0000
Links: << >>  << T >>  << A >>
Hajimowlana Sayed wrote:
> 
> Hi;
> 
>         Does Xact (ver5.2 support 4000E series? I didn't find it in its library.
> 
> Thanks

I think you need XACT 6.0.1 for PC's or 5.2.1 for Unix to support 4000E.

Regards,
Scott
Article: 3749
Subject: Re: What about the XC6200 ?
From: g.mcgregor@eee.strath.ac.uk (Gordon McGregor)
Date: Thu, 25 Jul 1996 00:03:13 GMT
Links: << >>  << T >>  << A >>
<jonathan@dcs.gla.ac.uk> wrote:

>On 11 Jul 1996, GAMRAT Christian wrote:

>> Is There anybody out there who knows anything new about the Xilinx XC6200 
>> partially reconfigurable fpga ?

>depends what you mean by new? i don't think there's any more information
>available yet, preliminary timing details that i'm probably not allowed to
>disclose even if i had the timing diagram where i could find it ;-)

Xilinx have a 30-odd page data sheet on the XC6200 on their web site,
with all the advance timing information included.  The latest one is
dated June 1st, 1996.

I could not find any information in the Xilinx databook to support the
assertion that the data in a flip-flop is cleared if the cell that
contains it is being reconfigured.  Certainly the Atmel devices allows
a cell's logic to be modified while retaining the state of the
flip-flop in the cell.  I would be interested if anyone could clarify
the point that the XC6200 would clear the register state when the
remainder of the CLB was being modified.

I also noticed that IBM are now entering the FPGA market, with a
new architecture, based closely on the Atmel 6000 series (formerly the
Concurrent Logic devices).  The Atmel cell as been modified, improving
routing and cell functionality, but retaining its interesting features
such as partial and dynamic reconfigurability.


Gordon
 Communications Division           Email: g.mcgregor@eee.strath.ac.uk  
 Electronic & Electrical Eng. Dept.
 University of Strathclyde         Tel:  +44 (0)141 552 4400 x 2250
 Glasgow G1 1XW                    Fax:  +44 (0)141 552 4968



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