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Messages from 3550

Article: 3550
Subject: Re: Xilinx CLB allocation question
From: Andrew Metcalfe <metcalfe@iaccess.com.au>
Date: 20 Jun 1996 02:07:59 GMT
Links: << >>  << T >>  << A >>
Another, possibly easier way to do what you want is to use the 
CLBMAP symbol in your Xilinx schematic. This will allow you to specify 
the lookup tables in the XC3000 CLB's directly.

You might want to look at the XC4000E family - this CLB has 3 RAM and 1 
ROM mode where the ROM can be initialised at the schematic stage as a 
lookup table. See your disty or the Xilinx website for info....

-Andrew Metcalfe



Article: 3551
Subject: Re: Xilinx CLB allocation question
From: Lance Gin <c43lyg@dso.hac.com>
Date: Wed, 19 Jun 1996 19:27:06 -0700
Links: << >>  << T >>  << A >>
johnson edward eric wrote:
> 
> I am currently working on a project that will require the usage of a large
> number of CLB's available in an XC3042pc84 Xilinx Chip. Each CLB has a
> truth table represented by a group of about 10-15 AND and OR gates.
> XNFMAP generally groups all of these logic gates in CLBs in the way that
> I desire it too, but occasionally it splits up these logic gates into two
> CLBs when I want them all to be associated with the same CLB. Does anyone
> know if there is a way that I can assign a group of logic gates to a
> particuler CLB without assigning the CLB to reside in a specific location
> in the Xilinx chip?
>

i'm a fairly new xc4k user with little experience with xc3k, but i
believe there is a primitive in xc3k called a CLBMAP which you can
use in conjunction with your schematics (i assume you're not using
an HDL) to control logic partitioning. check out p3-207 of the
"XACT Libraries Guide" for more info. the equivalent capabilities
in xc4k are called FMAP's and HMAP's.

alternatives might be to use floorplanner or CST files, but this
would involve placement which you wanted to avoid. i'm not sure if
CLBMAP's would be less work though. good luck,

-- 
_______________________________________________________________________

Lance Gin                                         "off the keyboard
Delco Systems - GM Hughes Electronics              over the bridge,
OFC: 805.961.7567  FAX: 805.961.7739               through the gateway,
C43LYG@dso.hac.com                                 nothing but NET!"
_______________________________________________________________________


Article: 3552
Subject: Agencies Avaliable
From: Mark Goldberg <goldmar@wantree.com.au>
Date: Thu, 20 Jun 1996 13:53:19 +0800
Links: << >>  << T >>  << A >>
Dear Sir,

Please note that I am the manufacturer’s representative therefore should 
you see or need anything please contact me as I currently represent 
about 160 different lines.

If you like and would like to represent the manufactures goods then 
simple contact myself details supplied below and I would be more than 
honoured to put you in direct contact with the manufacturer, this way 
there is one less middle man and higher profits to be made all round.

A sample of just a few products can be found on my web page which is 
still and continuously under construction, so if you don't see anything 
please simple Email me and I will certainly obtain it at the best 
available prices.

Hope this introduction between ourselves is only the beginning of a 
fruitful relationship.

Looking forward to hear from yourself soon.

Best regards
Mark Goldberg

-- 
GoldMar Holdings
TEL:(61-9)249-6162 FAX:(61-9)248-9464
GoldMar@wantree.com.au
http://cybernet.net.au/goldmar.html


Article: 3553
Subject: XC1765 vs Atmel's AT17C65 Serial EEPROMs
From: deannelson@aol.com (DeanNelson)
Date: 20 Jun 1996 05:07:23 -0400
Links: << >>  << T >>  << A >>
Hello out there!
(((( Caution: I'm a SW type, posing this HW problem!  ;-))))

We have been using Xilinx XC1765 serial PROMs for a while. We have bought
a bunch of Atmel's AT17C65 serial EEPROM  so we wouldn't have to keep
buying 
the Xilinx chips, as the Atmel chips are EEPROMs. We bought them thinking
they would be a form fit replacement for the Xilinx chips, because they
had the
same pin-outs, specs, etc.

Problem: whem we make a MCS file from the Xilinx tools, it will burn fine
in the
Atmel chips, but will not run, at all! ARE WE MISSING A STEP?

We are thinking that the Xilinx software prepares this file in a certain
way so 
that only Xilinx chips can be used. Whaddya think?



Dean Nelson
Loral Aerospace
Las Vegas, Nv


Article: 3554
Subject: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
From: Rainer Scharnow <amigo@bintec.de>
Date: Thu, 20 Jun 1996 13:38:53 +0200
Links: << >>  << T >>  << A >>
On 20 Jun 1996, DeanNelson wrote:

> Problem: whem we make a MCS file from the Xilinx tools, it will burn fine
> in the
> Atmel chips, but will not run, at all! ARE WE MISSING A STEP?

No, in my opinion there aren't any differences regarding the bitstreams of 
the PROMs. Remember: a serial 1765-PROM is a parallel PROM with a build-in 
address counter and a parallel-to-serial converter - and you can connect 
a parallel PROM like a C256 to a XILINX with the same burned-in 
bitstream (XILINX-FPGAs offer many more modes of configuration as serial 
PROMs). But what I think is you forgot to program the RESET polarity of 
the AT17C65 correctly. Your PROM programmer must offer you to program 
this polarity! Try to change it. 

E-regards

---------------------------
Rainer Scharnow
(amigo@bintec.de)
BinTec Commmunications GmbH
---------------------------


Article: 3555
Subject: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
From: ecla@world.std.com (alain arnaud)
Date: Thu, 20 Jun 1996 12:32:39 GMT
Links: << >>  << T >>  << A >>
DeanNelson (deannelson@aol.com) wrote:
: Hello out there!
: (((( Caution: I'm a SW type, posing this HW problem!  ;-))))

: We have been using Xilinx XC1765 serial PROMs for a while. We have bought
: a bunch of Atmel's AT17C65 serial EEPROM  so we wouldn't have to keep
: buying 
	[..snip..]

: Problem: whem we make a MCS file from the Xilinx tools, it will burn fine
: in the
: Atmel chips, but will not run, at all! ARE WE MISSING A STEP?


	No, you are not missing a step.
	The same thing happened to me. The problem is the ATMEL chips,
	some of them just don't work. ATMEL recognizes the issue and
	after badgering will provide devices with appropriate date codes.
	Just return them to the distributor.

	Alain Arnaud


Article: 3556
Subject: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
From: Rune Baeverrud <r@acte.no>
Date: Thu, 20 Jun 1996 15:39:19 +0200
Links: << >>  << T >>  << A >>
DeanNelson wrote:

> We have been using Xilinx XC1765 serial PROMs for a while. We have bought
> a bunch of Atmel's AT17C65 serial EEPROM  so we wouldn't have to keep

> Problem: whem we make a MCS file from the Xilinx tools, it will burn fine
> in the Atmel chips, but will not run, at all! ARE WE MISSING A STEP?

Check that you have the right OE/RESET polarity, as I believe some Atmel chips
has been shipped with the wrong default polarity! Please give me feedback if
this turns out to be the problem.
--
Rune Baeverrud <r@acte.no>
Field Application Engineer                    |\      _,,,---,,_
ScandComp, ACTE NC Norway AS            ZZzz  /,`.-'`'    -.  ;-;;,_
P.O. Box 190, N-2020 Skedsmokorset, Norway   |,4-  ) )-,_..;\ (  `'-'
Tel: +47 6389 8969   Fax: +47 6389 8979     '---''(_/--'  `-'\_)


Article: 3557
Subject: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
From: David McKenna <dmckenna@dne.com>
Date: 20 Jun 1996 17:19:09 GMT
Links: << >>  << T >>  << A >>
I have used the Atmel programmables successfully. However, I burn them via
DATAIO 3900, using ATMEL's algorithm. Originally, I tried with my Xilinx
box and never saw a DONE/PROGRAM pin go High. The first samples from Atmel 
were bad, however that was months ago. 



Article: 3558
Subject: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
From: Kevin Steele <ksteele@silcom.com>
Date: Thu, 20 Jun 1996 23:26:59 -0700
Links: << >>  << T >>  << A >>
The 1765 has programmable OE/RESET polarity.  We have seen the same problem and it depends 
on the programmer you are using...(Data I/O Chiplab and Link in our case fail). Atmel has 
stepped back and rather than trying to convince the programmer vendors to change the 
algorithms they have changed their silicon.  The new rev should be available about now and 
is distinguishable by date code.  Ask your Atmel rep/FAE...

Kevin Steele	ksteele@silcom.com
		kevins@motnengr.com     Motion Engineering, Inc.
					Santa Barbara CA	
----------------------------------------------------------------
Dean Nelson wrote:
> > We have been using Xilinx XC1765 serial PROMs for a while. We have bought
> > a bunch of Atmel's AT17C65 serial EEPROM  so we wouldn't have to keep....

> > Problem: whem we make a MCS file from the Xilinx tools, it will burn fine
> > in the Atmel chips, but will not run, at all! ARE WE MISSING A STEP?
> > DeanNelson
> REPLY
> Check that you have the right OE/RESET polarity, as I believe some Atmel chips
> has been shipped with the wrong default polarity! Please give me feedback if
> this turns out to be the problem.
> Rune Baeverrud <r@acte.no>


Article: 3559
Subject: Routing
From: maigner@sbox.tu-graz.ac.at (Manfred Aigner)
Date: 21 Jun 1996 09:36:36 GMT
Links: << >>  << T >>  << A >>
I tried to run xmake from Mentors design-manager to place and route my
design. I used the switches x-Blox Optimization, Map-then-merge and Make
Palced & routed Design.

The Utilization of CLB's was like this:

Preliminary estimate of device utilization for part  4013MQ240:
-------------------------------------------------------------------------
14% utilization of I/O pins.                   ( 26  of 192)     
81% utilization of CLB FG function generators. (934  of 1152)
16% utilization of CLB H function generators.  (185  of 576)
51% utilization of CLB flip-flops.             (582  of 1152
17% utilization of bus resources.           ( 16  of  96)
--------------------------------------------------------------
The router wasn't able to route teh whole design on this chip ( ONLY 97 % )

Ist there a way to do it with another tool or works this tool perfect?

How can I improve my design in a way that i can root it ?

Is it normal to get rooting problem with a utilisation of 80% ?

Would it be possible to root it on a bigger device (4015)?
Remark: There is no 4015 in my partlist and as a student I have no chance to
get better (bigger,newer..) libaries.

Witch placing policy should I use (already tried Map-then-merge and Merge
than Map, but no difference.)

I hope somebody can help me, otherwise I can't enjoy my holydays ;-).

Thanx in advance
-- 
Manfred Aigner alias maigner@sbox.tu-graz.ac.at


Article: 3560
Subject: Altera place and route
From: Tony Clark <tonyc@perth.DIALix.oz.au>
Date: Sun, 23 Jun 1996 09:04:25 +0800
Links: << >>  << T >>  << A >>
I have a problem with a current fpga design I am doing.

In the design I have a 24 stage shift register.  When I do a functional 
simulation everything works fine, however when I program the chip and try 
the real thing, my shiftreg fails to work correctly.

I had a close look at the gate level simulation and found that the clock 
for the first register leaded the clock for the second register by 24ns.  
This gives me, ineffect, a 23 bit shiftreg, as Q0 and Q1 always have the 
same data.  The clock by the way is 2MHz.

It looks to me, that the plug and play fitter with Maxplus2 has put the 
first SR next to the input pin, routed the clock to this register first 
and then kindly put an lcell in series with the clock line to the next 
register while routing Q to D directly!

The design is in a fairly full(90%) 8636 device.  Can anyone suggest how 
I can control the fitting so that the registers are grouped the way I 
want them?  The clock is internally generated and I have already used the 
global inputs  :(

As I only get to this news group once or twice a week, could any replies 
kindly be CCed to tclark@aesprodata.com.au

Thanks
Tony


Article: 3561
Subject: FPGA & PCB Design tools?
From: Peter Fenn <peterf@electrosolv.co.za>
Date: 23 Jun 1996 04:33:40 GMT
Links: << >>  << T >>  << A >>
What would be the key ingredients for most cost effective-, and productivity 
enhancing mix of (Pentium platform-) FPGA CAE Design Tools ???

(This question asked by a South African company with half-a-dozen Engineers 
full-time engaged with FPGA design work, but on a tight budget for software tools!)

We need to make best possible decisions for upgrade of all our software tools 
relating to FPGA design work, including the CAD PCB tools.  
We're looking at getting:
1) a Generic front-end CAD editor, for both PCB and FPGA schematic capture, 
2) a mix of Xilinx and Altera tools,
3) 3rd party Simulators and Synthesis products.
4) 3rd party PCB auto-router

We think we should purchase VIEWLOGIC front-end tools, which provide us with a 
common hierarchical schematic design tool for both PCB's and FPGA's, and shall 
probably then have a couple've XILINX FOUNDATION sites (VIEWLOGIC schematics can be 
imported directly), but are also convinced that we should be looking at getting some 
ALTERA sites, and 3rd party VHDL simulator and possibly additional Synthesis tools 
as well. (Both FOUNDATION and MAXPLUS shall provide us with basic VHDL synthesis and 
netlist timing simulation.)

Can anybody out there advise, before we break the bank?

Thanks in advance.

PETER FENN.



Article: 3562
Subject: Atmel AT17C65/128/256 Serial EEPROM Memories.
From: * Atmel FPGA Apps * <martin@atmel.com>
Date: Mon, 24 Jun 1996 10:30:14 GMT
Links: << >>  << T >>  << A >>

Over the last few days there have been numerous postings to 
comp.arch.fpga with regard to Atmel's EEPROM family of FPGA configuration 
memories (the configurators).  I wish to clarify a few points and offer a 
contact point for any further questions.

Atmel's Configurators do work with all known SRAM based FPGAs.

We have found that due to a 'percieved' bug in our competitors s/w that 
some customers have had difficulty when loading from a MCS file created 
in their s/w.  This problem manifests itself in the FPGA taking 
approx. 20 secs to load from the serial memory.  The problem is not with 
Atmel's serial memories, but with the competitors s/w.  I can supply a work 
arround to anyone who is interested.

Atmel chips are shipped with reset polarity high.  Most customers have to 
change reset polarity to low.  The AT17Cxxx devices support programmable 
reset polarity.  A broad range of industry standard programmers support 
the Atmel EEPROM.  The reset polarity change is done in one of two 
different ways on those programmers.  If you would like more information 
on this contact me at the e-mail address below.

Atmel EEPROM are not supported on the Xilinx programmer (!) as some 
customers have tried !!  Atmel does offer a $250 programmer for the 
devices (ATDH2200) that also support ISP of the devices - see Atmels home 
page for more details.

If anyone would like more details on the in-system-(re)programmable AT17Cxxx 
serial configuration EEPROMs or any other Atmel products please contact 
me at the e-mail addresses below.

Regards,

Martin.

-------------------------------------------------------------------------
|       Martin Mason            | Snr FPGA/17Cxxx Applications Engineer |
|       Atmel Corp.             | (email - me)         martin@atmel.com |
|       2325, Orchard Parkway   | (email - support)      fpga@atmel.com |
|       San Jose                | (Fax)         + (408) 436 4300        |
|       CA 95131    USA         | (Tele)        + (408) 436 4178        |
-------------------------------------------------------------------------
|Need Atmel Lit. stuff ?  WWW.ATMEL.COM or FAX-on-DEMAND 1-800-29-ATMEL | 
-------------------------------------------------------------------------


Article: 3563
Subject: Re: Xilinx CLB allocation question
From: Rob Froyd <rfroyd@Bergsys.com>
Date: Mon, 24 Jun 1996 13:14:03 -0700
Links: << >>  << T >>  << A >>
johnson edward eric wrote:
> 
> I am currently working on a project that will require the usage of a large
> number of CLB's available in an XC3042pc84 Xilinx Chip. Each CLB has a
> truth table represented by a group of about 10-15 AND and OR gates.
> XNFMAP generally groups all of these logic gates in CLBs in the way that
> I desire it too, but occasionally it splits up these logic gates into two
> CLBs when I want them all to be associated with the same CLB. Does anyone
> know if there is a way that I can assign a group of logic gates to a
> particuler CLB without assigning the CLB to reside in a specific location
> in the Xilinx chip?
> 
> Thanks
> Ed

You can with Viewlogic schematic tools use the FMAP, HMAP attribute. 
Using attributes, you can group logic into portions of a CLB, or group 
locic relative to a CLB or group of CLB's, or fix the logic down at an 
exact location. 

Rob


Article: 3564
Subject: Re: Xilinx CLB allocation question
From: Lance Gin <c43lyg@dso.hac.com>
Date: Mon, 24 Jun 1996 17:13:00 -0700
Links: << >>  << T >>  << A >>
Rob Froyd wrote:

> You can with Viewlogic schematic tools use the FMAP, HMAP attribute.
> Using attributes, you can group logic into portions of a CLB, or group
> locic relative to a CLB or group of CLB's, or fix the logic down at an
> exact location.

i believe fmap's/hmap's are to be used with xc4k only. for xc3k, clbmap is
the equivalent.

-- 
_______________________________________________________________________

Lance Gin                                         "off the keyboard
Delco Systems - GM Hughes Electronics              over the bridge,
OFC: 805.961.7567  FAX: 805.961.7739               through the gateway,
C43LYG@dso.hac.com                                 nothing but NET!"
_______________________________________________________________________


Article: 3565
Subject: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
From: ecla@world.std.com (alain arnaud)
Date: Tue, 25 Jun 1996 14:05:59 GMT
Links: << >>  << T >>  << A >>
* Atmel FPGA Apps * (martin@atmel.com) wrote:

: Atmel's Configurators do work with all known SRAM based FPGAs.

: We have found that due to a 'percieved' bug in our competitors s/w that 
: some customers have had difficulty when loading from a MCS file created 
: in their s/w.  This problem manifests itself in the FPGA taking 
: approx. 20 secs to load from the serial memory.  The problem is not with 
: Atmel's serial memories, but with the competitors s/w.  I can supply a work 
: arround to anyone who is interested.

		[..snip..]

 Could you be more specific about this "perceived" bug, otherwise we
 can dismiss your post as marketing hype.



Article: 3566
Subject: Re: Routing
From: Kate Meilicke <katem@xilinx.com>
Date: Tue, 25 Jun 1996 10:45:25 -0400
Links: << >>  << T >>  << A >>
Manfred,

Xilinx has a Floorplanner that will help with you routing.  If
you floorplan your data flow it usually helps with the routing.
Talk to your Xilinx Rep about getting this tool.

As far as Bus Resources vs Muxes it depends on how many signals
you are muxing.  More than 4, I usually suggest using the Bus
Resources.  You can place the TBUFS using the Floorplanner and
then the router doesn't have any problems routing these signals.

If you have a reset signal, use the GSR - Global Reset Line.  This
is a dedicated resource so it doesn't use the normal routing 
resources.  Use the STARTUP symbol to access the GSR.

I think your best bet is to use the floorplanner!

Kate Meilicke



Article: 3567
Subject: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
From: peter@xilinx.com (Peter Alfke)
Date: Tue, 25 Jun 1996 15:52:48 -0700
Links: << >>  << T >>  << A >>
In article <1996Jun24.103014.18313@super.org>, * Atmel FPGA Apps *
<martin@atmel.com> wrote:
 
> We have found that due to a 'percieved' bug in our competitors s/w that 
> some customers have had difficulty when loading from a MCS file created 
> in their s/w.  This problem manifests itself in the FPGA taking 
> approx. 20 secs to load from the serial memory.  The problem is not with 
> Atmel's serial memories, but with the competitors s/w.  I can supply a work 
> arround to anyone who is interested.
> 
Well, well.
Here is company X shipping millions of one-time programmable serial PROM
to thousands of customers, with hardly a problem. ( I have learned not to
say "never", but here it is really close ).

Then comes company A and offers an interesting alternative, an
electrically erasable version of such a serial PROM. Some designers like
that.

Some of these designers then have problems with company A's PROM and
ventilate their frustration in comp.arch.fpga.

The friendly answer coming from company A is: "..due to a perceived bug in
company X's software..."

C'mon, if you want to retrofit, you better be 100% compatible. 
If you are not, it's a cheap excuse to put the blame onto the originator.

Peter Alfke, Xilinx Applications


Article: 3568
Subject: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
From: Ray Andraka <randraka@ids.net>
Date: 26 Jun 1996 01:13:16 GMT
Links: << >>  << T >>  << A >>
Geez guys, lighten up.

I've used both parts without problems, including cases
where I've used the X brand ROM to configure the A brand FPGA and 
vice-versa. Both are fine parts.  Just make sure you set the reset/oe 
polarity the right way for your application.  That's really no 
different than many other parts out there is it?  Those of you using
a programmer made for one specific part can't reasonably expect it to 
program a different part type.  Even among some of the popular PALs 
and ROMs made by several manufacturers there are a variety of 
combinations of programming algorithms/voltages required.  There are 
reasonably priced programmers out there that will handle a wide 
variety of parts.  An example is the Needham Electronics EMP-20 which 
I think sells for less than $500 and programs both of these parts as 
well as most micros, ROMs and PLDs.

-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930   FAX 401/884-7950
mailto:randraka@ids.net
http://www.ids.net/~randraka/
 
The Andraka Consulting Group is a digital hardware design firm 
specializing in high performance FPGA designs.  Services include 
complete design, development, simulation, and integration of these 
devices and the surrounding circuits.  We also evaluate,troubleshoot, 
and improve existing designs. Please call or write for a free 
brochure.





Article: 3569
Subject: XC3100A Tristates
From: Richard Meacham <R.Meacham@sheffield.ac.uk>
Date: Wed, 26 Jun 1996 10:37:42 +0100
Links: << >>  << T >>  << A >>
Has anybody created a tristate-based connection network using Xilinx 
XC3100A devices? Has anyone had any experience of using the tristates 
in these devices? What sort of delay times are we looking at?

Thanks,

Richard Meacham
Contract Researcher


Article: 3570
Subject: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
From: ft63@dial.pipex.com (Peter)
Date: Wed, 26 Jun 1996 22:23:34 GMT
Links: << >>  << T >>  << A >>

>Just make sure you set the reset/oe 
>polarity the right way for your application.

You are probably right on the mark. The trouble is that some
programmers which "support" a given device don't support user config
for what that device's manufacturer regards as *user-configurable*
features, and the only way is to edit the .hex or .jed file.

I found that my Data I/O Chiplab is in this category. It has an even
more annoying general shortcoming: it does not allow the user
electronic signature (on PLDs) to be specified.

Peter.

Article: 3571
Subject: Need recommendation for PCI interface on 68332
From: benst@stuyts.nl (Ben Stuyts)
Date: Thu, 27 Jun 1996 14:57:40 GMT
Links: << >>  << T >>  << A >>
Dear net,

I need to interface a Motorola MC68332 controller to a PCI VGA card. I am
looking at various PCI bridge chips, but they seem to offer too much for my
needs. I saw that Actel and Xilinx (and perhaps others?) support the PCI bus
with some of their chips, and even have drop-in PCI designs (Xilinx
LogiCore).

Are Actel and Xilinx the most likely candidates for this? Any others?

How good is their PCI support, and how good are these designs like LogiCore?

Thanks,
Ben
-- 
Analogic Engineering BV                 Phone:  +31 (0)23 5621623
Parellaan 44                            Fax:    +31 (0)23 5629349
2132WS Hoofddorp                        Email:  ben@stuyts.nl
The Netherlands                         (NeXT/MIME Mail OK)


Article: 3572
Subject: HELP:Foundation VHDL on WIN95
From: APURVA A BRAHMBHATT <abrahmbh@hades.ecs.umass.edu>
Date: Thu, 27 Jun 1996 14:13:31 -0400
Links: << >>  << T >>  << A >>
Can anybody tell me whether Foundation VHDL is supported on WINDOWS95?
I would be glad if anybody can tell me a good web site about Foundation
VHDL Tools..
Thanks
-Apurva Brahmbhatt
Uni. of Massachusetts, Amherst


Article: 3573
Subject: Re: XC3100A Tristates
From: peter@xilinx.com (Peter Alfke)
Date: Thu, 27 Jun 1996 11:22:07 -0700
Links: << >>  << T >>  << A >>
In article <31D104E6.41C67EA6@sheffield.ac.uk>, Richard Meacham
<R.Meacham@sheffield.ac.uk> wrote:

> Has anybody created a tristate-based connection network using Xilinx 
> XC3100A devices? Has anyone had any experience of using the tristates 
> in these devices? What sort of delay times are we looking at?

The individual device output turn-on and turn-off times are all in the
data sheet( page 2-183 in the data book ).They assume 50 pF load. You can
get a feel for the active output drive capability from page 9-23 of the
current ( and older ) Xilinx data book.
Slew-rate limited outputs have the same dc characteristics as non-slew
rate limited outputs. It's only the transition that is longer.

To really answer the question, one needs to know something about topology
and speed requirements of your network.

Peter Alfke, Xilinx Applications


Article: 3574
Subject: Re: Need recommendation for PCI interface on 68332
From: erik@blender (Erik de Castro Lopo)
Date: 27 Jun 1996 23:48:27 GMT
Links: << >>  << T >>  << A >>
Ben Stuyts (benst@stuyts.nl) wrote:
: Dear net,

: I need to interface a Motorola MC68332 controller to a PCI VGA card. I am
<stuff deleted>
: Are Actel and Xilinx the most likely candidates for this? Any others?

The Xilinx family best suited to PCI designs (the XC4000E series) are
roughly twice the price of something like the Spanner/Q-Span chips from
Newbridge Components (they may now be called Tundra??) which are designed 
specifically for the Motorola MC68k family.

The main advantage of the FPGA PCI bus interface designs is the ability to
add application specific logic to the FPGA and hence reduce chip count.

Hope this helps,
Erik.



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