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Messages from 3850

Article: 3850
Subject: Re: Xact 6.0.1: memgen
From: ecla@world.std.com (alain arnaud)
Date: Fri, 9 Aug 1996 03:22:32 GMT
Links: << >>  << T >>  << A >>
Frederic GOFFIN (fg) wrote:
: Hi,

: Does anyone knows if it's possible to generate a dual port ram
: with the memgen program of XACT 6.0.1 for Xilinx 4000E series?

: Thanks a lot

Here's a .mem file used by memgen to generate a 128x16 dpram


; ========================================================================
; DP128X16.mem:  A 128-word deep by 16-bit wide DP_RAM memory.
; ========================================================================
;
TYPE	DP_RAM	; The memory is a DP_RAM
DEPTH	128	; The memory is 128 words deep
WIDTH	16	; Each memory word is 16 bits wide
;
PART	4005EPG156
;
SYMBOL	VIEWLOGIC BUS ;  Build a VIEWLOGIC symbol with bus inputs
;
DEFAULT	0	; <-- Add a default value for unspecified locations
DATA	0	; <-- Add your DP_RAM data here
; ========================================================================
;  Your DP_RAM memory uses approximately 16942 two-input NAND-gates
;  as measured by:
;
;  GATES = (WIDTH * DEPTH * 4)  <-- 4 gates per each RAM cell.
;        + (DEPTH * 2)  <-- 2 times the depth of the RAM for bank decoding.
;        +  WIDTH  <-- 1 gate per each bit in a word for write logic.
;        +  ADDRESS_LINES  <-- 1 gate for each address line for inversions.
Article: 3851
Subject: Re: Commercial:gap in the market! ANIMAL
From: Richard Schwarz <aaps@erols.com>
Date: Fri, 09 Aug 1996 08:39:44 -0400
Links: << >>  << T >>  << A >>
roger gook wrote:
> 
> On the 6th of August, Bryan Harstad wrote:-
> 
> "I am just starting to look into VHDL, and
> I am having a hard time locating any kind
> of evaluation board/software with a Xilinx
> FPGA, and some inputs/outputs.
> 
> Does anyone know where I can buy one from?
> 
> I don't really care what family of Xilinx,
> but I would prefer something in the 4000 line."
> 
> In reply:-
> 
> Parsys Ltd are developing an absolute animal. The card is designed to be
> fitted with two off Xilinx 4025E-2/3 devices, 8MB DRAM and 128 kB Flash
> ROM together with a T9000 embedded controller which provides access to a
> DS Link network. It is intended that the card may be deployed as a
> coprocessor in a PC bus, or as a node in our switched DS Link Parallel
> Computer systems. These switched systems are designed to support up to
> 2048 nodes and we already offer the Alpha AXP 21066 as a node. For the
> 4th QTR 96 we plan to be bring news of both the Xilinx engine and the
> 500MHz Alpha AXP 21164 node, available in a heterogeneous environment,
> up to 2048 of them, hence my reference to animal !
> 
> Please keep tuned to http://www.parsys.com

I have an answer for you. APS offers a low cost ($250.00) solution which 
gives you a XILINX 4000/5000 84 pin plcc board with download software, 
oscillators, status LEDs, and VHDL examples. A more advanced board with 
4 208 pin QFP XILINX chips is also available. I have used both boards 
and they are worth their weight in GOLD!!

contact APS in MD @
@ 410-515-3883   or 

SIGTEK at rdschwarz@sigtek.com
Article: 3852
Subject: FPGA TEST BOARDS
From: Richard Schwarz <aaps@erols.com>
Date: Fri, 09 Aug 1996 08:51:09 -0400
Links: << >>  << T >>  << A >>
There is a low cost cost test board available for anyone interested in XILINX 4000/5000 development. The board is only $250.00 and can take 
any 4000 or 5000 84 pin PLCC. It works right in a PC and has test oscillators, status LEDs and test ribbon connectors as well as 24 bit of IO 
for downloading and digital IO. The board comes with VHDL examples and schematics with directions for hardware implementation of the XILINX 
chips into other designs. Another board for more complex designs like ASIC simulatiuons contains 4 208 QFP chips. These boards can take any of 
the 4000/5000 chips in the 84 pin PLCC or 208 pin QFP format  ie. 4005,4010,4020,5010,5015 etc..

CONTACT: APS @ 410-515-3883 or
rdschwarz@sigtek.com for more info!!!
Article: 3853
Subject: Re: Xilinx/FPGA Timing Problems
From: ft63@dial.pipex.com (Peter)
Date: Fri, 09 Aug 1996 13:00:06 GMT
Links: << >>  << T >>  << A >>


Ian,

I am probably missing something, but could you not overcome
metastability in your async interface simply by doubly or
triply-latching each signal?

I know this slows things down a bit.

Peter.
Article: 3854
Subject: Re: ANNOUNCE : HDL Editor
From: Martin DAnjou <mdanjou@nortel.ca>
Date: 9 Aug 1996 14:07:59 GMT
Links: << >>  << T >>  << A >>
Hi,

Nice colors for VHDL keywords, but how do I get line numbers
and vi editing style? The help menu does not tell me much about line
numbers.

Martin.
-- 
| Martin d'Anjou                    | tel: (613) 765-3058                |
| Nortel                            | fax: (613) 763-9535                |
| P.O. Box 3511, Station C          | email: mdanjou@nortel.ca           |
| Ottawa, Ontario, CANADA  K1Y 4H7  | My opinions, not Nortel's          |
| http://www.nortel.com/            | Mes opinions, pas celles de Nortel |

Article: 3855
Subject: Job Offering In Orange County, CA
From: mankeny@netcom.com (Cable And Computer Tech)
Date: Fri, 9 Aug 1996 14:32:50 GMT
Links: << >>  << T >>  << A >>

ENGINEERING

Expanding OC firm engaged in design & production of commercial/industrial/MIL-
SPEC computers & computer systems has the following immediate opening:

SENIOR SYSTEMS DESIGN ENGINEER

Requires BS degree in an Engineering discipline, or equivalent, & minimum 7 
years of Design experience.  Must be comfortable in both software & hardware 
design & debug of prototype embedded systems using both RISC & CISC 
microprocessors.  Must be familiar with assembly language, C++ or Ada; one or 
more standard busses (VME, PCI, Futurebus+); one or more micro-processors 
(68XXX, XX86, i960, MIPS); and programmable logic (PALs, CPALs, FPGAs). 
Experience in VHDL or Verilog a plus. Must be a self-starter with good 
communication & interpersonal skills.

CCT offers competitive salaries, excellent benefits & long-term stability. 

E-mail your ascii-text resume with salary history to cjohnson@c2t.com or via US. mail to:

Attn:  Cindy Johnson
       1555 So. Sinclair St.
       Anaheim, CA 92806
       cjohnson@c2t.com



-- 
                                             mankeny@netcom.com
Article: 3856
Subject: An incompatible problem of ALTERA MAXPLUS2 Ver6.2, Ver 6.1 -- need your help
From: Jim Sung <jim@diig.dlink.com.tw>
Date: Fri, 09 Aug 1996 10:26:27 -0700
Links: << >>  << T >>  << A >>
My environment :
     AST BRAVO MS-T P/100 with 64M RAM, 1.2G HD
     Windows Chinese version 3.1 with 80M permanent virtual memnory
     MAXPLUS2 Ver6.2
     Device : FLEX10K

  When I compile a project, even smaller as tutorial project "chiptrip", 
  there will be an error at the satge of "Timing SNF Extracter". The 
  error message is 

  "Internal Error:(cmp) Fatal application error in Timing SNF Extracter 
   at 5%.    Please contact ALTERA ......"

  If I choose device FLEX8000, it works.  This case worked under Ver 6.1. 
  But there is the same error while compiling my working project.  Some  
  computers in my office can finish the job.  FAEs of ALTERA Taiwan and  
  Hongkong can't fix it. It seems the incompatiblilty of MAXPLUS ver 6.2 
  for FLEX10K series. 

  Did anyone meet the same problem and solve it ? Could you share me your 
  experience ?  Thanks a lot !

  Jim
Article: 3857
Subject: XACT:error301 with flow engine
From: tw38966@vub.ac.be (Rafiki Kim Hofmans)
Date: 9 Aug 1996 18:39:41 GMT
Links: << >>  << T >>  << A >>

Hi,

can someone help me figure out wath the following error means :

error 301 : delay 7.9 on Pin I0 of AND XSYM524 is not annotated.
The pin is connected to the signal $6I32/M2OUT8.

This error appears while the flow engine is running the timing.


Thanks in advance !

Kim


--


==============================================================================

			************************************
			*	Hofmans Kim 		   *	
  		       	*				   *
			*	tw38966@vub.ac.be	   *
			*	khofmans@info.vub.ac.be	   *
			*                                  *
			*	Brouwerijstraat 62         *
			*	1630 Linkebeek             *
			*	Belgium 		   *
			*				   *
			*	32-2-3771012		   *
			*				   *
			************************************

Article: 3858
Subject: PLDCon'97
From: sbaker@best.com
Date: 9 Aug 1996 23:11:56 GMT
Links: << >>  << T >>  << A >>
PLD champions:

I’m the Program Chairman for PLDCon’97.  This isn’t a call for papers.  We need your comments about the most important topics to 
include in the program.  

A short questionnaire web form is online at www.pldsite.com.

The annual conference and exhibition for FPGAs, CPLDs and simple PLDs is PLDCon.

PLDCon’97 next spring is the seventh annual event. 

Please help us out and give us your comments so we can keep this program what engineers need.  Those attending the conference 
will thank you.

If I get enough inputs I'll send an analysis of the results back to you.  This will tell you what practicing engineers think are the most 
important topics to learn about for programmable logic.

Sincerely,
Stan Baker
Program Chairman
PLDCon’97


*****************************************
            SBAssociates
   ph. 408-356-5119 fx. 408-356-9018
   Stan Baker = sbaker@best.com
   Debbie Peel = reconfig@best.com
   Kathy Rogers = sba2@best.com
            web sites:
   www.pldsite.com - www.reconfig.com
****************************************
Article: 3859
Subject: Re: An incompatible problem of ALTERA MAXPLUS2 Ver6.2, Ver 6.1 -- need your help
From: Tony Clark <tonyc@perth.DIALix.oz.au>
Date: Sat, 10 Aug 1996 10:17:11 +0800
Links: << >>  << T >>  << A >>
I had the local Altera FAE around yesterday and he did mention that there 
were some bugs in 6.2O that effected the 10k family.  He did say there 
was a fix available.

on Fri, 9 Aug 1996, Jim Sung wrote:

> My environment :
>      AST BRAVO MS-T P/100 with 64M RAM, 1.2G HD
>      Windows Chinese version 3.1 with 80M permanent virtual memnory
>      MAXPLUS2 Ver6.2
>      Device : FLEX10K
> 
>   When I compile a project, even smaller as tutorial project "chiptrip", 
>   there will be an error at the satge of "Timing SNF Extracter". The 
>   error message is 
> 
>   "Internal Error:(cmp) Fatal application error in Timing SNF Extracter 
>    at 5%.    Please contact ALTERA ......"
> 
>   If I choose device FLEX8000, it works.  This case worked under Ver 6.1. 
>   But there is the same error while compiling my working project.  Some  
>   computers in my office can finish the job.  FAEs of ALTERA Taiwan and  
>   Hongkong can't fix it. It seems the incompatiblilty of MAXPLUS ver 6.2 
>   for FLEX10K series. 
> 
>   Did anyone meet the same problem and solve it ? Could you share me your 
>   experience ?  Thanks a lot !
> 
>   Jim
> 
> 
Article: 3860
Subject: Re: Commercial:gap in the market! ANIMAL
From: Richard Schwarz <aaps@erols.com>
Date: Sat, 10 Aug 1996 02:10:14 -0400
Links: << >>  << T >>  << A >>
roger gook wrote:
> 
> On the 6th of August, Bryan Harstad wrote:-
> 
> "I am just starting to look into VHDL, and
> I am having a hard time locating any kind
> of evaluation board/software with a Xilinx
> FPGA, and some inputs/outputs.
> 
> Does anyone know where I can buy one from?
> 
> I don't really care what family of Xilinx,
> but I would prefer something in the 4000 line."
> 
> In reply:-
> 
> Parsys Ltd are developing an absolute animal. The card is designed to be
> fitted with two off Xilinx 4025E-2/3 devices, 8MB DRAM and 128 kB Flash
> ROM together with a T9000 embedded controller which provides access to a
> DS Link network. It is intended that the card may be deployed as a
> coprocessor in a PC bus, or as a node in our switched DS Link Parallel
> Computer systems. These switched systems are designed to support up to
> 2048 nodes and we already offer the Alpha AXP 21066 as a node. For the
> 4th QTR 96 we plan to be bring news of both the Xilinx engine and the
> 500MHz Alpha AXP 21164 node, available in a heterogeneous environment,
> up to 2048 of them, hence my reference to animal !
> 
> Please keep tuned to http://www.parsys.com

The APS X-84 is a low cost FPGA board which works with the XILINX 4000 & 
5000 84 pin PLCC family of FPGA parts. The board allows the programming 
 of parts from proms or PC ISA bus via supplied C code. On board 
oscillators and status LEDs are provided along with 24 bits of PC IO 
lines. The X-84 is a low cost PC ISA card with download software and 
sample VHDL and C code. It sells for $250.00.
Article: 3861
Subject: Re: Commercial:gap in the market! ANIMAL
From: Richard Schwarz <aaps@erols.com>
Date: Sat, 10 Aug 1996 02:13:01 -0400
Links: << >>  << T >>  << A >>
roger gook wrote:
> 
> On the 6th of August, Bryan Harstad wrote:-
> 
> "I am just starting to look into VHDL, and
> I am having a hard time locating any kind
> of evaluation board/software with a Xilinx
> FPGA, and some inputs/outputs.
> 
> Does anyone know where I can buy one from?
> 
> I don't really care what family of Xilinx,
> but I would prefer something in the 4000 line."
> 
> In reply:-
> 
> Parsys Ltd are developing an absolute animal. The card is designed to be
> fitted with two off Xilinx 4025E-2/3 devices, 8MB DRAM and 128 kB Flash
> ROM together with a T9000 embedded controller which provides access to a
> DS Link network. It is intended that the card may be deployed as a
> coprocessor in a PC bus, or as a node in our switched DS Link Parallel
> Computer systems. These switched systems are designed to support up to
> 2048 nodes and we already offer the Alpha AXP 21066 as a node. For the
> 4th QTR 96 we plan to be bring news of both the Xilinx engine and the
> 500MHz Alpha AXP 21164 node, available in a heterogeneous environment,
> up to 2048 of them, hence my reference to animal !
> 
> Please keep tuned to http://www.parsys.comThe APS X-84 is a low cost FPGA board which works with the XILINX 4000 & 
5000 84 pin PLCC family of FPGA parts. The board allows the programming 
 of parts from proms or PC ISA bus via supplied C code. On board 
oscillators and status LEDs are provided along with 24 bits of PC IO 
lines. The X-84 is a low cost PC ISA card with download software and 
sample VHDL and C code. It sells for $250.00.
Article: 3862
Subject: Shareware XILINX Synthesis Tool???
From: Richard Schwarz <aaps@erols.com>
Date: Sat, 10 Aug 1996 02:26:48 -0400
Links: << >>  << T >>  << A >>
I am currently using the board described below with XILINX XACT and 
EXEMPLAR logic for synthesis. I have heard rumors about a shareware or 
very low cost synthesis tool which could synthesize into .XNF files. Has 
anyone heard of such a thing??


The APS X-84 is a low cost FPGA board which works with the XILINX 4000 & 
5000 84 pin PLCC family of FPGA parts. The board allows the programming 
 of parts from proms or PC ISA bus via supplied C code. On board 
oscillators and status LEDs are provided along with 24 bits of PC IO 
lines. The X-84 is a low cost PC ISA card with download software and 
sample VHDL and C code. It sells for $250.00.
Article: 3863
Subject: ASIC simulations in multiple FPGAs
From: Richard Schwarz <aaps@erols.com>
Date: Sat, 10 Aug 1996 02:34:25 -0400
Links: << >>  << T >>  << A >>
I am currently producing an ASIC using 2 XILINX 4010s and 2 XILINX 
4020s. It is great for testing, but I will soon be combining the 
multiple chip entiites in order to get one VHDL chip. Has anyone done 
anything similiar to this, and could they pass along any information 
about this. I would love to find a RAM based part in the 30,000 to 
40,000 gate range which I could use, and which could get resonable % of 
routing. Also, any reccomendations on ASIC vendors. The ASIC will be 
entirely digital.
Article: 3864
Subject: Re: Shareware XILINX Synthesis Tool???
From: ft63@dial.pipex.com (Peter)
Date: Sat, 10 Aug 1996 19:04:58 GMT
Links: << >>  << T >>  << A >>


>I am currently using the board described below with XILINX XACT and 
>EXEMPLAR logic for synthesis. I have heard rumors about a shareware or 
>very low cost synthesis tool which could synthesize into .XNF files. Has 
>anyone heard of such a thing??
>

The cheapest way I know of to XNF is any PLD compiler capable of
producing a PALASM-compatible file (e.g. PALASM, CUPL etc), and using
the old PDS2XNF program (which Xilinx used to give away) to convert
this to XNF.

But I suspect you are after VHDL input. If you do a "VHDL" web search
you will find sites that have freeware VHDL -> .EXE compilers which
produce standalone DOS executables which "run" (i.e. simulate) your
VHDL code. This is where I would investigate. I can see someone
charging $1000s for one of these free programs!

Peter.
Article: 3865
Subject: Technical Job posting ( and ads) not related to the newsgroup.
From: "Jim Lewis, ASIC and HDL Consultant" <telejim@teleport.com>
Date: 12 Aug 1996 01:28:30 GMT
Links: << >>  << T >>  << A >>
Recently, I have noticed that some of the Job (and ad) postings that have
been posted to comp.lang.vhdl were not even for VHDL type jobs. 
I became a little concerned that some of the posters are missing
the concept of what the news group was for, so I sent them email to 
see what was up and to ask that if they did not have something on topic
not to post it here. 

What I learned was that this type of posting was intentional.
The following is a direct quote:
B>  "No, there isn't anything specific to VHDL in the listings, but
B>  it has been my experience in the past that quite often individuals who do
B>  have VHDL knowledge have DSP in there background as well."

So you might ask yourself, is this a fluke or will it continue.
Here I will quote the entire contents of a follow up email.
B>  Wow, I can not believe that the only thing you got out of my note was that I
B>  was going to continue to post non-VHDL messages to the VHDL newsgroup.  I
B>  guess people will read into things what they want to.  I took my best shot at
B>  explaining things to you. But I will try one last time  As I told you before,
B>  it has been my experience in the past and now I can tell you it is also my
B>  experience in the present (as I have received resumes from individuals who
B>  saw my posting guess where?) that individuals with VHDL experience  in many
B>  instances have DSP in their background as well.  I have just sent over more
B>  than 20 candidates for seven open positions to my client.  EVERY single one
B>  of them responded to one of my postings on the technical news groups.  Three
B>  of them in particular were from the VHDL user group.  So again, I know none
B>  of this will make any difference to you but I do what I do because it works.
B>   I understand that you are not interested in my postings and I do respect
B>  that.  However, there are obviously people out there who do care - please try
B>  to respect that as well.....


In fact, the person with whom I corresponded also felt that very few 
people object to this type of posting.  Going back to the first email,
I quote:

B>  "My responses are about 100 to 1 favorable to unfavorable.  I have so few
B>  negative responses that I do take the time to write a thoughtful answer to
B>  the issues at hand as I am doing with you


I am do not have an extremist point of view reguarding posting jobs 
(or advertising).  All I care is that if someone is going to post
a job or advertise that they stay within the scope of the newsgroup 
(and hence only post VHDL jobs to the VHDL news group, ...).

As I pointed out earlier, these people feel that they are getting an 
overwelmingly favorable response to what they are doing and do intend to 
continue.  Perhaps they will set a precedence and others will join.  

If you disagree with them, a simple polite email would do.
I have included the following as an example and a good way to 
get started (do include the postmaster of the site that the 
person emailed from):

====================
Mail To:  BKOjobs@aol.com, postmaster@aol.com
subject:  Your off topic job postings to comp.lang.vhdl

Dear Postmaster,
    Please disable, BKOjobs@aol.com, account, as they are not repecting
our newsgroups charter.

Dear Bridget, 
    Please stop posting non-related job postings to comp.lang.vhdl.

Thank You,
A concerned newsgroupie

======

While you are at it, you might send email to otto@ottocad.com 
concerning his autocad advertisments in comp.cad.synthesis.  He is
also of the opinion that no one objects to him spamming the newsgroup.
In fact postmaster@ottocad.com (probably otto himself) responded 
with the following:

O>  In checking the logs, I find that Otto has posted approximately once every
O>  two weeks to comp.cad.systhesis for a total of five posts.

O>  In looking at the postings (dating back to 10/95) in this group as provided
O>  by our newsfeed, I can find only one objection to Otto's postings. 

Feel free to let them know.
=======

I feel the personal, polite follow up will bring much faster and 
hopefully more conclusive results than posting in the newsgroup.

Cheers,
Jim Lewis
telejim@teleport.com

Article: 3866
Subject: Technical Job posting ( and ads) not related to the newsgroup.
From: "Jim Lewis, ASIC and HDL Consultant" <telejim@teleport.com>
Date: 12 Aug 1996 01:38:55 GMT
Links: << >>  << T >>  << A >>
Recently, I have noticed that some of the Job (and ad) postings that have
been posted to comp.lang.vhdl were not even for VHDL type jobs. 
I became a little concerned that some of the posters are missing
the concept of what the news group was for, so I sent them email to 
see what was up and to ask that if they did not have something on topic
not to post it here. 

What I learned was that this type of posting was intentional.
The following is a direct quote:
B>  "No, there isn't anything specific to VHDL in the listings, but
B>  it has been my experience in the past that quite often individuals who do
B>  have VHDL knowledge have DSP in there background as well."

So you might ask yourself, is this a fluke or will it continue.
Here I will quote the entire contents of a follow up email.
B>  Wow, I can not believe that the only thing you got out of my note was that I
B>  was going to continue to post non-VHDL messages to the VHDL newsgroup.  I
B>  guess people will read into things what they want to.  I took my best shot at
B>  explaining things to you. But I will try one last time  As I told you before,
B>  it has been my experience in the past and now I can tell you it is also my
B>  experience in the present (as I have received resumes from individuals who
B>  saw my posting guess where?) that individuals with VHDL experience  in many
B>  instances have DSP in their background as well.  I have just sent over more
B>  than 20 candidates for seven open positions to my client.  EVERY single one
B>  of them responded to one of my postings on the technical news groups.  Three
B>  of them in particular were from the VHDL user group.  So again, I know none
B>  of this will make any difference to you but I do what I do because it works.
B>   I understand that you are not interested in my postings and I do respect
B>  that.  However, there are obviously people out there who do care - please try
B>  to respect that as well.....


In fact, the person with whom I corresponded also felt that very few 
people object to this type of posting.  Going back to the first email,
I quote:

B>  "My responses are about 100 to 1 favorable to unfavorable.  I have so few
B>  negative responses that I do take the time to write a thoughtful answer to
B>  the issues at hand as I am doing with you


I am do not have an extremist point of view reguarding posting jobs 
(or advertising).  All I care is that if someone is going to post
a job or advertise that they stay within the scope of the newsgroup 
(and hence only post VHDL jobs to the VHDL news group, ...).

As I pointed out earlier, these people feel that they are getting an 
overwelmingly favorable response to what they are doing and do intend to 
continue.  Perhaps they will set a precedence and others will join.  

If you disagree with them, a simple polite email would do.
I have included the following as an example and a good way to 
get started (do include the postmaster of the site that the 
person emailed from):

====================
Mail To:  BKOjobs@aol.com, postmaster@aol.com
subject:  Your off topic job postings to comp.lang.vhdl

Dear Postmaster,
    Please disable, BKOjobs@aol.com, account, as they are not repecting
our newsgroups charter.

Dear Bridget, 
    Please stop posting non-related job postings to comp.lang.vhdl.

Thank You,
A concerned newsgroupie

======

While you are at it, you might send email to otto@ottocad.com 
concerning his autocad advertisments in comp.cad.synthesis.  He is
also of the opinion that no one objects to him spamming the newsgroup.
In fact postmaster@ottocad.com (probably otto himself) responded 
with the following:

O>  In checking the logs, I find that Otto has posted approximately once every
O>  two weeks to comp.cad.systhesis for a total of five posts.

O>  In looking at the postings (dating back to 10/95) in this group as provided
O>  by our newsfeed, I can find only one objection to Otto's postings. 

Feel free to let them know.
=======

I feel the personal, polite follow up will bring much faster and 
hopefully more conclusive results than posting in the newsgroup.

Cheers,
Jim Lewis
telejim@teleport.com

Article: 3867
Subject: Re: Technical Job posting ( and ads) not related to the newsgroup.
From: spp@plitvice.EECS.Berkeley.EDU (Steve Pope)
Date: 12 Aug 1996 07:41:52 GMT
Links: << >>  << T >>  << A >>
"Jim Lewis, ASIC and HDL Consultant" <telejim@teleport.com> writes:

>I am do not have an extremist point of view reguarding posting jobs 
>(or advertising).  All I care is that if someone is going to post
>a job or advertise that they stay within the scope of the newsgroup 
>(and hence only post VHDL jobs to the VHDL news group, ...).

I think that's overreacting.   I guess there are some sweatshops
out there where people do "VHDL jobs" 60 hours a week without
ever learning DSP, applications, Verilog, architecture, etc.,
but all my experience would suggest that this is the exception.
Engineering work is interdisciplinary, and many people reading
a group like this have their main strengths elsewhere.

Steve
Article: 3868
Subject: Evolutionary Electronics W/S Papers
From: monty@watson.open.ac.uk (Tony Hirst)
Date: Mon, 12 Aug 1996 10:29:57 GMT
Links: << >>  << T >>  << A >>
The 1st On-line Workshop for Soft Computation is now open for business....

******************************************************
      CALL FOR PARTICIPATION & DISCUSSION

                  Special Session
               Evolutionary Electronics
-------------------------------------------------------------
http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/papers/Evol_Elec.html
******************************************************
DISCUSSION PROCEDURE:

1. Read the abstracts.
2. Copy the main texts ( ps files ) of interested papers.
3. Send questions and comments to
     wsc@bioele.nuee.nagoya-u.ac.jp
     (The steering committee will send the questions to the authors
      and receive answers from the authors, and make the Q&A visible
      on the Internet.) 
4. Read the answers from the authors on 
    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/
5. Repeat the above steps 3 and 4 until you are satisfied.
******************************************************
Analogue Circuits:

       COMPONENT VALUE SELECTION FOR ACTIVE FILTERS USING
         GENETIC ALGORITHMS
       D.H. Horrocks, M.C. Spittle
       University Of Wales, Cardiff. School Of Engineering,

       Genetically Derived Filter Circuits Using Preferred Value
           Components
       David H. Horrocks, Yaser M.A. Khalifa
       University Of Wales, Cardiff. School Of Engineering, Circuits and
       Systems Group.

       Genetically Evolved FDNR and Leap-Frog Active Filters Using
          Preferred Component Values
       David H. Horrocks, Yaser M.A. Khalifa
       University Of Wales, Cardiff. School Of Engineering,Circuits and
       Systems Group.

       Genetic Algorithms Design of Electronic Analogue circuits 
          Including Parasitic Effects
       David H. Horrocks, Yaser M.A. Khalifa
       University Of Wales, Cardiff. School Of Engineering,Circuits and
       Systems Group.


Co-Design:

       An Evolutionary Approach to System-Level Synthesis
       Juergen Teich, Tobias Blickle, Lothar Thiele
       Institute TIK

       Evolving Adaptive Computer Systems
       Tony Hirst
       HCRL, Gardiner Bldg, Walton Hall, Open University


Digital Logic Synthesis:

       Experiences of using Evolutionary Techniques in Logic Minimisation
       Julian F. Miller, Peter V. G. Bradbeer, Peter Thomson
       Dept. of Computer Studies, Napier University

       Genetic Synthesis Techniques for Low-Power Digital Signal 
            Processing Circuits
       T. Arslan, E Ozdemir, M. S. Bright, D.H. Horrocks
       University Of Wales, Cardiff. School Of Engineering, Circuits and
       Systems Group.


Fault Tolerance:

       EVOLUTIONARY TECHNIQUES FOR FAULT TOLERANCE
       Adrian Thompson
       School of Cognitive and Computing Sciences, University of Sussex


Hardware Evolution:

       SILICON EVOLUTION
       Adrian Thompson
       School of Cognitive and Computing Sciences, University of Sussex


Hardware Implementations:

       Implementing a Generic Systolic Array for Genetic Algorithms 
       I. M. Bland, G. M. Megson
       Algorithm Engineering Research Group, Dept. of Computer Science,
       University of Reading

       HGA:A Hardware-Based Genetic Algorithm
       Stephen D. Scott, Ashok Samal, Sharad Seth
       Washington University in St. Louis, University of Nebraska-Lincoln
         and University of Nebraska-Lincoln

       A HARDWARE ARCHITECTURE FOR A PARALLEL GENETIC
       ALGORITHM FOR IMAGE REGISTRATION
       B.C.H. Turton, T. Arslan, D.H. Horrocks
       University Of Wales, Cardiff. School Of Engineering,Circuits and
       Systems Group.

        An Architecture for Enhancing Image Processing via Parallel
          Genetic Algorithms & Data Compression
       B.C.H. Turton, T. Arslan
       University Of Wales, Cardiff. School Of Engineering, Circuits and
       Systems Group.

       A Parallel Genetic VLSI Architecture for Combinatorial Real-Time
         Applications - Disc Scheduling
       B.C.H. Turton, T. Arslan
       University Of Wales, Cardiff. School Of Engineering, Circuits and
       Systems Group.


VLSI Placement:

       A Genetic Framework For The High-Level Optimisation Of Low
         Power VLSI DSP Systems
       M.S. Bright, T. Arslan
       University Of Wales, Cardiff. School Of Engineering, Circuits and
       Systems Group.

       Structural Cell-based VLSI Circuit Design using a Genetic 
         Algorithm
       T. Arslan, D.H. Horrocks, E. Ozdemir
       University Of Wales, Cardiff. School Of Engineering,Circuits and
       Systems Group.

       STRUCTURAL SYNTHESIS OF CELL-BASED VLSI CIRCUITS USING
          A MULTI-OBJECTIVE GENETIC ALGORITHM
       T. Arslan, D.H. Horrocks, E. Ozdemir
       University Of Wales, Cardiff. School Of Engineering,Circuits and
       Systems Group.


VLSI Test:

       Hierarchical Test Pattern Generation Using A Genetic Algorithm
         With A Dynamic Global Reference Table
       M. J. O'Dare, T. Arslan
       University Of Wales, Cardiff. School Of Engineering,

       GENERATING TEST PATTERNS FOR VLSI CIRCUITS USING A
         GENETIC ALGORITHM
       M. J. O'Dare, T. Arslan
       University Of Wales, Cardiff. School Of Engineering, Circuits and
       Systems Group

Article: 3869
Subject: Re: ASIC simulations in multiple FPGAs
From: jeff.cunningham@valley.net (Jeff Cunningham)
Date: 12 Aug 1996 13:43:06 GMT
Links: << >>  << T >>  << A >>
In article <320C2D71.6341@erols.com>
Richard Schwarz <aaps@erols.com> writes:

> I am currently producing an ASIC using 2 XILINX 4010s and 2 XILINX 
> 4020s. It is great for testing, but I will soon be combining the 
> multiple chip entiites in order to get one VHDL chip. Has anyone done 
> anything similiar to this, and could they pass along any information 
> about this. I would love to find a RAM based part in the 30,000 to 
> 40,000 gate range which I could use, and which could get resonable % of 
> routing. Also, any reccomendations on ASIC vendors. The ASIC will be 
> entirely digital.

I spoke with AMI about a year ago about doing this sort of thing,
though I never followed through with it. Their reccomendation was to
create a giant xnf of the whole design, i.e. combine the separate FPGA
designs into one large schematic that you can simulate but would be too
large to target to a real FPGA. Then use that large design to generate
a set of functional test vectors. AMI will then take the giant xnf and
run it through their proprietary translator that converts to their own
netlist format. The functional test vectors are then applied to the
translated netlist to make sure somebody didn't do something bonehead
along the way. AMI will for an extra charge insert scan chains and run
their ATPG tool on it so you needn't worry about test vector coverage.
Otherwise you need to create high-coverage test vectors in addition to
the functional vectors. To keep things clean in terms of timing
analysis and ATPG, they reccomend keeping the design 100% synchronous.
Flops can have async set and clear, but they should all go to an
external reset pin for start-of-the-day reset. They reccomend against
having internal logic controlling async set and clear.

-JCC
Article: 3870
Subject: Re: ### 7 Quick Multiple Choice Questions ###
From: jcooley@world.std.com (John Cooley)
Date: Mon, 12 Aug 1996 15:26:22 GMT
Links: << >>  << T >>  << A >>
jcooley@world.std.com (John Cooley) writes:
>
> .....................  Please reply *on* or *before* this Thursday,
> July 25th (three days from now) to "jcooley@world.std.com" so I can get
> this quickly tabulated and written up.
>                                           - John Cooley

Pete Peterson <rep@genrad.com> wrote:
>You seem to have an overly optimistic expectation of news propagation times.
>We get our news feed from BBN Planet and your message didn't get to our
>site until 27 July at 0144, although it appears to have been posted on 22
>July at about 2121.
>
>It may be that BBN is just a particularly unreliable source for a news
>feed.  I notice that there are significant numbers of articles that I get
>through my home Internet provider that NEVER show up here at work.  I can't
>successfully correlate the missing articles with anything else, though.
> 
>        pete peterson


Pete, sorry for the assumption that the survey would get out on the net
quickly; I was acting under a tight deadline.  Either way, I got roughly
350 responses to this survey with 90 percent of them within the first
36 hours of putting out on ESNUG and the newsgroups.  I find it ironic
that BBN, one of the pioneers in computer networking has a "particularly
unrealiable source for a news feed" -- it's like hearing that AT&T has
really bad internal phone connections!  :^)

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 4599 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3871
Subject: Re: Using Carry logic in XC4000...
From: Marc Baker <marc.baker@xilinx.com>
Date: Mon, 12 Aug 1996 09:11:54 -0700
Links: << >>  << T >>  << A >>
The app note is available on the Xilinx web site
( http://www.xilinx.com )
under Application Notes -> XAPP Application Notes -> 013, or
directly at http://www.xilinx.com/xapp/xapp013.pdf .  There is also an
article on Advanced Carry Logic Techniques in the latest issue
of the XCELL newsletter, XCELL 21.  The article's address is
http://www.xilinx.com/xcell/xl21/xl21-42.pdf .  (Just after the
article recommending this newsgroup!).

Xilinx app notes and other information are easy to find using
SmartSearch, the Xilinx search engine that includes the Xilinx
web site and related sites, at http://www.xilinx.com/search/search.com
Article: 3872
Subject: Re: Quick question for Model Tech. experts:
From: lllapides@aol.com (Lllapides)
Date: 13 Aug 1996 01:03:15 -0400
Links: << >>  << T >>  << A >>
Tim Lindquist's response -- creating a higher level of hierarchy -- is
correct.  I
would also point out that the creation of this "wrapper file" top level
design can
be done automatically with Exemplar Logic's Galileo synthesis tools.  For
more info please contact their customer support at support@exemplar.com.

Larry Lapides
Article: 3873
Subject: FPGA's/C++/OWL, Data Acquisition Systems, to 30k, Northants, UK - ECM
From: Topjob <topjob@ecmsel.demon.co.uk>
Date: Tue, 13 Aug 1996 12:54:00 +0100
Links: << >>  << T >>  << A >>
Subject: Ref:n.6158 - FPGA's/C++/OWL,Data Acquisition Systems, to 30k,
NORTHANTS

This young, dynamic company develops high quality data acquisition and
monitoring software for a range of clients in the automotive and
travel sectors.

With continued success, they seek a number of high calibre Development
Engineers looking to work in both hardware and software design.

You will have an excellent academic background with skills in either
FPGA's / PLC's, or Borland C++ / OWL, or a mixture of both.

In addition to good development skills, you will also have excellent
client liaison and technical support skills.

Any exposure to DSP / Speech Processing will be a plus.

-- 
For further information on ECM visit www.ecmsel.co.uk

Please contact us by Email (Cvs in plain ASCII text - not coded!)
topjob@ecmsel.co.uk  ------ Alternatively Snail, Fax or Phone:
ECM Selection Ltd, The Maltings, Burwell, Cambridge, CB5 0HB.
Tel:  01638 742244                      Fax:  01638 743066

Article: 3874
Subject: Re: ACTEL Prices
From: CoxJA@augustsl.demon.co.uk (Julian Cox)
Date: Tue, 13 Aug 1996 15:59:05 GMT
Links: << >>  << T >>  << A >>
bxa8@po.CWRU.Edu (Bassam Al-Kharashi) wrote:


>Hello ...

>I would like to know the cost of the following devices
>Actel ... A1425A    84 pins       2,500 gates
>Actel ... A1240A    84 pins       4,000 gates 
>Actel ... A14100A   257 pins     10,000 gates.

>Thanks for your help

>Bassam 
>bxa8@po.cwru.edu
>-- 
>Bassam A. Al-Kharashi
>email bxa8@po.cwru.edu

I'm a user not a distributor so I only have prices for the devices I
use.  All I have is:

	100 off A1240A-PL84C 		35.07 ukp each
	1000 off A1240A-PL84C		24.65 ukp each

	100 off A1240XL-PL84C		24.22 ukp each
	1000 off A1240XL-PL84C	17.39 ukp each 

 All PLCC 84 pin commercial grade.

The XL version is fully compatible with th A.  Actel claim they are
33% faster,  in my application I only got about 9% speed advantage.

Prices came from 
Microprocessor and Memory Distribution.  +44 1734 633700.

If you havn't committed yourself to Actel yet I strongly recommend you
try the development kit for a month.  IMHO it sux.

TTFN

Julian.
-- 
---------------------------------------------------------------------
CoxJA@augustsl.demon.co.uk              error: smartass.sig not found
---------------------------------------------------------------------
                                          




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