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Messages from 10700

Article: 10700
Subject: Re: How about Lattice ispLSI?
From: r.kellenbach@NO_SPAM_multiweb.nl (Rene Kellenbach)
Date: Thu, 11 Jun 1998 13:30:03 GMT
Links: << >>  << T >>  << A >>
Garry Allen <garrya@abc.gov.au> wrote:

>How can I slag the ispVHDL?Viewlogic combination enough. The lattice
>fitter is a good tool. the Viewlogic VHDl tools OTOH were the worst I
>have ever used.

That bad, eh? This morning, I had a visit from a local representative.
She demonstrated the ispVHDL/Viewlogic design flow, and I think
a package is pretty complete (although my reference is pretty limited
in this area). However, I feel the Viewlogic tools may need better
integration. I would prefer a single IDE, not a bunch uncorrelated
windows that clutter my desktop.

>The minimised code Viewsynthesis produced for one of my designs would
>not fit into a 256 macrocell device with less than 5 levels of logic. I
>expected around 190 with 2 levels. Using another tool (Synplicity) I got
>the types of resiults I expected. Thsi suggests that the minimisation
>from viewlogic is around 30-40% worse than a more optimal tool. FWIW
>Lattice use Synplicity for their technical support and are happy to sell
>it to you at a much reduced price. If you are serious about using the
>lattice devices and VHDL, get the Synplicity tool.

Hmm...the local Lattice distributor over here recommends the
ispVHDL/Viewlogic combo. Will ask about the Synplicity tools.

Thanks, Gary.

Rene Kellenbach,
The Netherlands


Article: 10701
Subject: Re: How about Lattice ispLSI?
From: r.kellenbach@NO_SPAM_multiweb.nl (Rene Kellenbach)
Date: Thu, 11 Jun 1998 13:55:38 GMT
Links: << >>  << T >>  << A >>
aaj15@dial.pipex.com (Kim Carter) wrote:

>Bear in mind that once you have fixed your pins, getting an acceptable fit
>gets increasingly difficult - If you go much over 70% on the 3256's you are
>running at rapidly increasing risk of not being able to modify and still get 
>a fit. If you are pushing for speed as well this is accentuated - If as you 
>suggested in an earlier post you are planning in the field mods, leave a good
>margin for it or you will come unstuck.

Good tips! Is the 70% limitation caused by the chip architecture, or
by the fitter? What about other software packages - do they all depend
on the Lattice fitter?

>We were using the 3256 devices - considerably larger, along with a few 
>1024s. There was a lot of interest in using the 6000 series - at the time
>Synario could not handle these in a properly integrated fashion ie one could 
>neither call the RAM/FIFO sections up as 'symbols' in the schematic editor
>nor as macros within Abel, is this still the case? and how are these functions
>dealt with in the Viewlogic system?

AFAIK, the ispVHDL/Viewlogic supports the 6000 series, but only via
schematic entry. The ABEL/Synario package doesn't support the
6000 series, to my knowledge.

>It rather depends on what else you are likely to do in future - if you are
>likely to move on to FPGAs as opposed to other CPLDs, VHDL will handle this
>whereas Abel will not.

Maybe - learning VHDL seems like a good investment. I am pretty
fluent in ABEL, but don't know anything about VHDL. Any good
VHDL tutorials on the net?

>There is also the issue of what form the schematics take - Some schematic
>editors are basically HDL code generators, so you end up with code which
>is entirely in HDL and therefore (within limits) portable, others including
>the Synario/Abel arrangement are entirely proprietry and therefore are non
>portable. AFAIK the Synario schematic format cannot be exported as anything 
>else so you can't eg document your PLD by just embedding the schematic in
>a word document, only print it. 

This is a major disadvantage of proprietary formats. A standard system
like Viewlogic would be a better choice in this respect.

>You should also be aware that some systems enable you to take your fitted design
>and feed it back into a schematic editor to give a gate level diagram.

The Viewlogic system has this capability.

>So rumour (mainly from Lattice) had it, the other manufacturers had problems
>with data retention - fine if you want built in obsolescence but not much good
>if it was expected to work for 10 years or so. Probably bs**t but if you do 
>want to use Vantis, might be worth comparing with Lattice.

Hmm...should I be worried about this? Some of our products are used
in pretty harsh environments (high temperatures and other nasty
things). Would Lattice be a safe choice in this respect?

Thanks, Kim.

Rene Kellenbach
The Netherlands


Article: 10702
Subject: Re: Are you looking for a good VHDL/Verilog Editor?
From: meserve@my-dejanews.com
Date: Thu, 11 Jun 1998 14:22:31 GMT
Links: << >>  << T >>  << A >>
In article <357f7caf.0@139.134.5.33>,
  "John Maher" <jmaher@silicon-systems.com> wrote:
>
> For all of you VHDL or Verilog users:
>
> Silicon Systems Solutions produce a product called "ED for Windows - HDL"
> (ED4W-HDL) which is a very sophisticated productivity editor, to FAST TRACK
> your VHDL/Verilog code development.
>
> The editor runs under Windows 3.1/95/98/NT
>
> Features include:
>
> + Syntax Highlighting
> + Automatical Language Template insertion and expansion
> + Automatic TESTBENCH template generation
> + Dozens of common VHDL models for FPGA development
> + Advance Search/Replace across files etc
> + Syntax and Template Expansion support for 30+ other languages, including
> C. C++, BASIC, PASCAL
>
> and much more ...
>
> A FREE evaluation copy is available, at
> http://www.silicon-systems.com/prod01.htm
>
> The evaluation version is restricted to 45 days use, from the time of
> installation
>
> Regards,
>
> John
>


Seems your site is password protected. Makes things a little difficult
to view.

Further, is there a port for UNIX platforms?  Not everyone works in
a PC environment.

Martin Meserve

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 10703
Subject: Re: How about Lattice ispLSI?
From: r.kellenbach@NO_SPAM_multiweb.nl (Rene Kellenbach)
Date: Thu, 11 Jun 1998 14:22:55 GMT
Links: << >>  << T >>  << A >>
ems@see_sig.com (ems) wrote:

>my 2 cents: if you're just moving up from plds, get the starter
>kit, and stick with abel. i think you can get support for
>everything up to the 1032 (1048?) with the starter kit. this gives
>you the minimum-investment solution and the smallest learning curve.
>you'll have working devices *much* faster than if you decide to go for
>VHDL, and it'll cost you a *lot* less.

Agreed, the starters kit seems much easier to use than the
ispVHDL/Viewlogic combo. Price isn't that important, but
my time is limited.

>
>schematics:
>
>why bother? not only do you have to learn an HDL, but
>you also have to learn the schematic package, and how to
>integrate the HDL with the schematics. You have to cope with bugs
>from both environments and support from 2 vendors (except that
>one of them isn't supporting you - you try going to viewlogic/
>aldec/etc to tell them that your lattice/xilinx/etc package has
>a bug). i personally never use schematics, but i've used synario and
>viewlogic, and both are second-rate (but i've seen worse). you often
>end up just putting HDL modules on a page with their inputs and
>outputs labelled - you might as well just put in a top-level HDL
>source instead.

I have seen both Synario and Viewlogic in the past few days,
and I think the integration of both packages with the Lattice
fitter still have a lot of room for improvement. Maybe an
HDL-only approach would be wise, just to circumvent
quirks.

>Abel:
>
>+  easy to learn, except that the manuals are useless
>+  you can buy it separately - you don't need synario
>+  functional simulation is very easy; much easier than
>   using a gate-level simulator such as viewsim (also
>   second-rate)
>-  has it reached end-of-life? i think it probably has.
>   this is not a good time to be paying thousands of
>   dollars for it.
>-  annual maintenance (what do you get for this? nothing,
>   in my case)
>-  buggy, but you quickly learn what not to do
>-  very expensive. why buy it if you're only interested
>   in one vendor, and they do a cheap vendor-locked
>   version?

Agreed, I would not start using Abel from scratch nowadays.
However, I have had some exposure to Abel - this would get
me started with Synario/Abel in a short period of time.

>Lattice starter kit:
>
>+  much cheaper than abel (i paid 2K UKP for abel; if i'd
>   waited a couple of months i could have got all the
>   devices i was using at that time for a couple of
>   hundred dollars in the starter kit)
>+  no maintenance
>+  covers most of the devices you'd want to use (i reckon
>   lattice isn't cost-effective at the 1048 or higher
>   level, but i think the kit now includes the 1048
>   anyway)

I already tried the starter kit and I was not impressed.

>ispVHDL/Viewlogic:
>
>haven't used it, but i have used viewlogic with vhdl and
>abel for xilinx, and i guess it's much the same. i didn't
>like it - see comments about multiple vendors, viewsim,
>need for schematics, etc.
>
>timing:
>
>i'm not sure why, but i've never felt the need to use
>anything other than a static timing analyser for
>lattice devices (i've used 1016/24/32/48). the timing
>is well-defined and the devices don't encourage you
>to do things which you'll need a timing simulator to
>verify. on the other hand, i always use a timing
>simulator with xilinx.

The timing model of Lattice CPLDs is pretty simple -
probably simple tools will suffice to verify timing.


>VHDL:
>
>i personally use VHDL for almost everything, but i
>would say that - for me - it's not an efficient solution
>for devices as small as a 1016 or 1024.
>
>-  *very* hard to learn. if you're faced with a choice
>   of learning abel or vhdl, and it's important to get
>   results quickly, then it's a no-brainer - go for
>   abel.

This is the scary part.

>   it's not just the language, which is bad enough,
>   but the synthesis issues, the entire
>   design flow, the differences between vendors,
>   etc.

I have seen a demo of the design flow this morning.
It's not straightforward, but I think I can manage this.

>+  the primary advantage - simulatability. you
>   can do far more complex simulations than
>   you could hope to do with abel or a gate-
>   level simulator.
>-  but - you have to buy a separate simulator.
>   the "cheap" (!) vendor-locked packages include
>   only a synthesiser, which supports only
>   a subset of the language.
>   this can be expensive - i use modelsim, at
>   about 5K UKP.

The ispVHDL/Viewlogic package inludes a
simulator (Viewsim), but I haven't tried it yet.
Probably gate-level only.

>you often hear people saying that they don't use
>vhdl because it's too high-level, too far from the
>hardware, etc. but you can use whatever subset of
>the language you want - you could even write in
>a completely structural style, and just wire up
>modules in the same way that you would on a
>schematic (or in abel, for that matter).
>synthesis shouldn't be a problem - if you stick with the
>simple stuff it'll synthesise well.

Just like moving from C to C++, eh?

>and forget the device utilisation arguments. if you're
>a software engineer and you synthesise vhdl code,
>then you may very well end up with lots of unnecessary
>hardware; but, if you know what you want, then there's
>no reason that you shouldn't get it. 

Hey - software engineers should spend some time
programming in solder (or solder++) before they
start programming in VHDL. That'll teach them
to use hardware resources efficiently!

>in short - you need a very good reason, and lots of time,
>money, and patience, to start down the vhdl route, even
>more so if you want to use schematics as well.

Pretty discouraging....especially the 'lots of time' part.

>on the other hand, you could start with abel and the
>starter kit for almost nothing, and have working
>hardware quickly.

Will give the starter kit another look.

Thanks, Evan.

Rene Kellenbach
The Netherlands.

Article: 10704
Subject: floorplanning in xilinx
From: Joshua Schwartz <josh@gezernet.co.il>
Date: Thu, 11 Jun 1998 16:31:03 +0200
Links: << >>  << T >>  << A >>
Tools : MTI VHDL, Leonardo synthesis, Xilinx M1.4.12, Windows NT 4
Target part: large 4000XL

Question :  I want to do the equivalent of floorplaning. I have a
block with some predefined blocks (from the core generator) that.
I instanciate this block (with some memory, multipliers, inferred
(from the vhdl) adders/subtractors/counters etc.) several times
and notice that M1 makes some bad decisions as to where to place
things. I would like to tell the tool to keep all logic in one
instance in a square relocatable region so that it won't put a
multiplier from instance 1 on the other side of the chip from
the adder which feeds it in the same instance.

Please note that in each coregen block the rloc attribute is used
and also Leonardo uses the rloc attribute for each modgen (ie. adder
,counter...) that it produces. Furthermore, the M1 tool does
keep the relative locations with in each modgen/coregen part. The
problem is I also want to keep relative locations of
modegen/coregen parts with in each block instance close.

I hope I've been clear on want it is I'm after. Thanks in
advance for any and all help.

Joshua


--
Joshua Schwartz
ICC Design
972-8-9287375
Josh@gezernet.co.il


Article: 10705
Subject: Re: How about Lattice ispLSI?
From: r.kellenbach@NO_SPAM_multiweb.nl (Rene Kellenbach)
Date: Thu, 11 Jun 1998 14:31:20 GMT
Links: << >>  << T >>  << A >>
Tim Forcer <tmf@ecs.soton.ac.uk.nojunk> wrote:

>I got the pDS starter kit several years ago, which was OK but very
>limited.  Because I wanted to use the 1024, I had to buy "Full pDS", and
>all I got extra over the starter kit was support for the full range of
>devices.  Even after an upgrade, this software is AWFUL.  It isn't a
>true Windows app, doesn't save configuration, etc. 

My sentiments exactly.

> Since my application was, in
>several respects, a trivial one, this wasn't any great hardship.  I've
>heard several people say the starter Synario is pretty good for a
>freebie, but haven't tried it myself.

I have tried the Synario/ABEL tutorial  - seems pretty
straightformard, IMHO. Other people over here tell me
it has some quirks, though.

>As to the ICs, they are fine, and have delivered excellent performance. 
>I've got reliable 9ns glitch recognition out of a 90MHz part, which I
>think is good going.  The only reservation I have, which I pass on
>whenever anyone asks about ispLSI, is WATCH YOUR 5V line.  With most
>logic ICs, the data sheet says max Vcc (or Vdd) is 7V.  With 74-type
>logic, and with many PLDs I've used, if there's a microsecond-order
>supply transient which exceeds 7V, even one of over 10V, the ICs don't
>die, and some just carry on working as is nothing had happened.  But
>ispLSI chips fail short-circuit in an EXTREMELY short time if the rail
>exceeds 7.0V.  The fix in my case was to use a 1N5908 across the power
>pins relatively close to the IC.  I also used a tantalum bulk decoupler
>to limit the rise rate of 5V transients.  If you can guarantee that your
>board's power rails will NEVER glitch this way, then you are very
>fortunate, and should ignore this problem.  I couldn't so protected the
>devices explicitly.  The failure mode is related to the charge pump
>involved in providing 5V-only isp, so is likely to be found in other isp
>families.

Good tips - will give this some extra attention if we are going to
use the Lattice parts.

>Support, from distributors and from Lattice, has been patchy.  Sometimes
>it's been excellent, sometimes poor.  No obvious reason for the
>variation.

Support from the local distributor has been excellent so far.

Thanks, Tim.

Rene Kellenbach,
The Netherlands.

Article: 10706
Subject: Re: floorplanning in xilinx
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Thu, 11 Jun 1998 07:41:31 -0700
Links: << >>  << T >>  << A >>
Currently, floorplanning support seems to be a bit light from Xilinx if
you're using the M1 tools.  However, there are some excellent third-party
tools available from Morphologic.  You should take a look at their MorphMCFP
(multi-chip floorplanner) tool.  There is more information available at
http://www.morphologic.com/mmcfp.htm.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

Joshua Schwartz wrote in message <357FEA27.8CE67D6F@gezernet.co.il>...
>Tools : MTI VHDL, Leonardo synthesis, Xilinx M1.4.12, Windows NT 4
>Target part: large 4000XL
>
>Question :  I want to do the equivalent of floorplaning. I have a
>block with some predefined blocks (from the core generator) that.
>I instanciate this block (with some memory, multipliers, inferred
>(from the vhdl) adders/subtractors/counters etc.) several times
>and notice that M1 makes some bad decisions as to where to place
>things. I would like to tell the tool to keep all logic in one
>instance in a square relocatable region so that it won't put a
>multiplier from instance 1 on the other side of the chip from
>the adder which feeds it in the same instance.
>
>Please note that in each coregen block the rloc attribute is used
>and also Leonardo uses the rloc attribute for each modgen (ie. adder
>,counter...) that it produces. Furthermore, the M1 tool does
>keep the relative locations with in each modgen/coregen part. The
>problem is I also want to keep relative locations of
>modegen/coregen parts with in each block instance close.
>
>I hope I've been clear on want it is I'm after. Thanks in
>advance for any and all help.
>
>Joshua
>
>
>--
>Joshua Schwartz
>ICC Design
>972-8-9287375
>Josh@gezernet.co.il
>
>


Article: 10707
Subject: VHDL/Verilog Consultants interested in delivering Training for Esperan
From: Simon Moreton <simon@esperan.com>
Date: Thu, 11 Jun 1998 16:19:15 +0100
Links: << >>  << T >>  << A >>
Due to Esperan's rapid expansion in the provision of VHDL and Verilog
training services in the US and Europe.  We are actively seeking to
recruit consultants as trainers to out source the delivery of the
training courses to, on a week by week basis.

Esperan specialize in supplying independent, application orientated VHDL
and Verilog based training and have very close relationships with most
of the main EDA and FPGA vendors such as Synopsys, Mentor, Viewlogic,
Xilinx and Altera our courses are recommended or re-sold by many of
them.

In addition to the obvious financial benefits our experience with other
consultants has shown that delivering the training courses provides an
excellent opportunity for the consultant to market their own, and their
organizations expertise to potential customers.

Primarily we want to to talk with Designers/Consultants who have:

# Real world experience of VHDL and/or Verilog based design using
synthesis.
# Experience in the use of FPGAs would be a distinct advantage.
# Good communication skills and the ability to explain complex topics in
a clear, concise manner.
# Availability for periods of up to one week for between four and ten
weeks per year.
# A willingness to travel.

We own and develop all the training material, but subcontract the
delivery to consultants.  All the logistics of the courses, such as
marketing, software licenses,  training materials, presentation
materials etc. are managed by Esperan.

If you think you have what we are looking for please return by email
your answers to the following questions to give me a summary of your
experience to date.

How many years experience of VHDL/Verilog?=
What real design experience have you had?=
Does it include Synthesis?=
How many ASIC's or FPGA's have you synthesized?=
What experience of testbench design have you had?=
What design tools have you used?=
What would your availability be during the year for training (ie. 6 five
day course )?=
When would you be available to start?=

Would you also send me an up to date resume'.

I look forward to discussing this opportunity with you.

Regards
Simon Moreton
Training Manager

Article: 10708
Subject: Re: Xilinx 4000/Spartan: Maximum pin pullup
From: thiessen@iee.et.tu-dresden.de (Thilo Thiessenhusen)
Date: 11 Jun 1998 15:33:52 GMT
Links: << >>  << T >>  << A >>
In article <357FBE69.9F9D85B1@bltinc.com>, Ed McCauley <edmccauley@bltinc.com> writes:
>Would turning on the internal pull-up resistor in the 'load' IOB solve
>your problem?  I'm assuming you're trying to guard against the sensor
>going open circuit.

No, it is not the usual pullup. The thing acts as a 'Nand' in the old
MOS-style. The OBUFT is an open drain, the sensor is the second switch
in the chain. When both are active, the 'dot' should be drawn down to
logic Low. And there is the problem. When the open-drain is not active,
a leakage current somewhere should not bring the 'dot' beneath the
High threshold.

On the other hand, R must be big enough that when both the sensor has
its 20K and the OBUFT connects to ground, the 'dot' is not above the
Low threshold. From looking into the handbook I think R=100K might
be OK, but I might have forgotten something; so I'd rather hear from
somebody who has more experience than me. 

Regards,

Thilo


>Thilo Thiessenhusen wrote:
>> 
>> Hello,
>> 
>> I have a configuration like this:
>> 
>>                  Vdd
>>                   |
>>                  ---
>>                  | |
>>                  | | R
>>                  ---
>>         _         |          _
>>   OBUFT _>--------o---------<_ IBUF
>> 
>> What is the maximum resistance that guarantees a valid input level
>> at any time? Would 100K be O.K.?
>> 
>> [The actual configuration is a bit more complicated since there is
>> a sensor between OBUFT and the dot, which can switch between
>> open and about 10-20K].


-- 
Support the anti-Spam amendment - Join at http://www.cauce.org/


Article: 10709
Subject: Looking for "A" designers only
From: richkol@aol.com (RichKol)
Date: 11 Jun 1998 16:16:15 GMT
Links: << >>  << T >>  << A >>
A small well funded Boston area firm is searching for A Players for its state
of the art
compression/decompression and image processing/enhancement technology products.

This is a world leader in the development and marketing of image processing
chips,
controller boards and software tools.

There are two positions that are being hotly searched for.  The company is
willing to pay
A salary and bonus for A players.  These are permanent positions.

1. ASIC Designers/ASIC Test Engineers 

Responsible for specification, architecture, behavioral modeling, design,
synthesis,
implementation, and simulation of state-of-the-art ASICs. Minimum 3 years IC
design; C,
algorithm development, image processing/coding and MSEE preferred. We have
developed a 133 MHz SIMD DSP, and the world's fastest JPEG @ 70 MHz.  

2. Principle Image Processing Engineer

In this leadership role, you will design & implement real-time image processing
algorithms
for color and monochrome printers, copiers, and scanners. Requires a BSEE (MSEE
preferred), 5+ years algorithm development experience, RISC/DSP assembly, and
C.
Project Management and printer experience a plus.  

3. Digital Design Engineer

Design, implement and debug advanced imaging board-level products. Requires
BSEE, 5
+ years of digital circuit design experience, familiarity with embedded system
design,
microcontrollers, high speed logic (>50 MHz), PLD and FPGA design. Experience
in
system and board level design analysis. Position includes project level
responsibility. 


If you are interested in finding out more regarding these positions, about the
challenges,
and one of the highest rate of salary - higher than the bay area, please
contact me by email.

richkol@aol.com
Rich Kolikof
Winthrop Research

Thanks for your time.
Rich Kolikof
Winthrop Research
503-644-9111
Article: 10710
Subject: Re: TESTBENCH
From: William White <will@fpga.demon.co.uk>
Date: Thu, 11 Jun 1998 17:30:23 +0100
Links: << >>  << T >>  << A >>
Yes, Speedwave will run "testbenches". Indeed any VHDL simulator should have this
capability. There is nothing special about testbenches. The general form of a testbench
is an empty entity with the DUT component Instantiated in the architecture. There will
then be a process to provide stimulus. See template below. There are also tools
available to automatically generate testbenches from timing diagrams such as QuickBench
from Chronology. If you require any further information on this please email me
directly.

Regards

Will


------------------------------------------------------------------------------ 
--
--  Typical testbench skeletons
--
------------------------------------------------------------------------------ 

--
-- Top-level entity/architecture
--
library ieee ;
use ieee.std_logic_1164.all ;

entity testbench is
end testbench;

architecture only of testbench is

    --
    -- Paste in any necessary signals and component declarations here.
    -- Declare DUT component here.
    --

begin

    --
    -- Paste in the instantiation(s) of the DUT component and any other testbench
    -- components here.
    --
    --

    -- Stimulus thread
    --

    stim : process
        
    begin

        --
        -- Paste in your test sequence here 
        --

        wait;
    end process;
end only;   

configuration testbench_config of testbench is 
    for only


        --
        -- Paste in your configuration statements here.
        --

    end for;
end testbench_config;


In article <6l853l$cee$1@goanna.cs.rmit.edu.au>, Hamish Moffatt <hamish@moffatt.nu>
writes
>In comp.arch.fpga John Huang <hungi@tpts4.seed.net.tw> wrote:
>>      I got some questions about Viewlogic/Speedwave,
>>      I have a design that use VHDL for a FPGA.
>>      1. Can I use VHDL testbench in the speedwave, if
>>         it is YES, how will I do?
>>      2. What simulaors support the VHDL testbench?
>
>Aldec's ActiveVHDL seems to run them nicely.
>
>>      3. Would you please give me an example for
>>         write testbench?
>
>Best to grab a book eg Skahill's VHDL for Programmable Logic,
>it has a whole chapter on it. Aldec's also has a thing for generating
>test benches for you, I haven't tried it.
>
>
>Hamish

-- 
William White                 <
 ------------------------  <  <  <  ----------  Mailto: will@fpga.demon.co.uk
| Direct Insight Ltd    <  <  <  <  >           Tel: +44 1280 700262       |
|                          <  <  <              Fax: +44 1280 700577       |
 ---------------------------  <  ------------------------------------------
Article: 10711
Subject: Re: Are you looking for a good VHDL/Verilog Editor?
From: jimmeans@my-dejanews.com
Date: Thu, 11 Jun 1998 17:21:41 GMT
Links: << >>  << T >>  << A >>
In article <357f7caf.0@139.134.5.33>,
  "John Maher" <jmaher@silicon-systems.com> wrote:
...
>
> A FREE evaluation copy is available, at
> http://www.silicon-systems.com/prod01.htm
>
> The evaluation version is restricted to 45 days use, from the time of
> installation
>
> Regards,
>
> John
>
>

I tryed this link and received a request for a username and password to get
into this site! Of course I don't have the username and password. Even trying
to go to www.silicon-systems.com gets the same response. Not a very effective
way to present a company on the Web.

Cheers,
Jim Means


-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 10712
Subject: Re: Are you looking for a good VHDL/Verilog Editor?
From: "John Maher" <jmaher@silicon-systems.com>
Date: Fri, 12 Jun 1998 08:18:31 +1000
Links: << >>  << T >>  << A >>
Apologies to all who tried to access our site, and found a password
protected page!

The web is now available.

-John


John Maher wrote in message <357f7caf.0@139.134.5.33>...
>For all of you VHDL or Verilog users:
>
>Silicon Systems Solutions produce a product called "ED for Windows - HDL"
>(ED4W-HDL) which is a very sophisticated productivity editor, to FAST TRACK
>your VHDL/Verilog code development.
>
>The editor runs under Windows 3.1/95/98/NT
>



Article: 10713
Subject: Re: Are you looking for a good VHDL/Verilog Editor?
From: "John Maher" <jmaher@silicon-systems.com>
Date: Fri, 12 Jun 1998 08:20:04 +1000
Links: << >>  << T >>  << A >>
Apologies to all who tried to access our site, and found a password
protected page!

The problem has been resolved by our web administrator, and the web is now
available.

-John

John Maher wrote in message <357f7caf.0@139.134.5.33>...
>For all of you VHDL or Verilog users:
>
>Silicon Systems Solutions produce a product called "ED for Windows - HDL"
>(ED4W-HDL) which is a very sophisticated productivity editor, to FAST TRACK
>your VHDL/Verilog code development.
>
>The editor runs under Windows 3.1/95/98/NT
>



Article: 10714
Subject: Re: floorplanning in xilinx
From: Carl Christensen <carl@philipsdvs.com>
Date: Thu, 11 Jun 1998 16:58:39 -0600
Links: << >>  << T >>  << A >>


Joshua Schwartz wrote:

> Tools : MTI VHDL, Leonardo synthesis, Xilinx M1.4.12, Windows NT 4
> Target part: large 4000XL
>
> Question :  I want to do the equivalent of floorplaning.

Call our Xilinx FAE and beg him/her  for help. The floorplanner is
coming back!  He/She should have access to a pre-released  copy.

Article: 10715
Subject: Re: TESTBENCH
From: leslie.yip@asmpt.com
Date: Fri, 12 Jun 1998 01:27:13 GMT
Links: << >>  << T >>  << A >>
Dear William White

How can I use SpeedWave to do testbenches? In the past, I used ModelSim's
V-System to do testbenches. Yet I know SpeedWave requires synthesis before,
right?

Leslie Yip

In article <RePGPJAfYAg1EAfI@fpga.demon.co.uk>,
  William White <will@fpga.demon.co.uk> wrote:
>
> Yes, Speedwave will run "testbenches". Indeed any VHDL simulator should have
this
> capability. There is nothing special about testbenches. The general form of a
testbench
> is an empty entity with the DUT component Instantiated in the architecture.
There will
> then be a process to provide stimulus. See template below. There are also
tools
> available to automatically generate testbenches from timing diagrams such as
QuickBench
> from Chronology. If you require any further information on this please email
me
> directly.
>
> Regards
>
> Will
>
> ------------------------------------------------------------------------------
> --
> --  Typical testbench skeletons
> --
> ------------------------------------------------------------------------------
>
> --
> -- Top-level entity/architecture
> --
> library ieee ;
> use ieee.std_logic_1164.all ;
>
> entity testbench is
> end testbench;
>
> architecture only of testbench is
>
>     --
>     -- Paste in any necessary signals and component declarations here.
>     -- Declare DUT component here.
>     --
>
> begin
>
>     --
>     -- Paste in the instantiation(s) of the DUT component and any other
testbench
>     -- components here.
>     --
>     --
>
>     -- Stimulus thread
>     --
>
>     stim : process
>
>     begin
>
>         --
>         -- Paste in your test sequence here
>         --
>
>         wait;
>     end process;
> end only;
>
> configuration testbench_config of testbench is
>     for only
>
>         --
>         -- Paste in your configuration statements here.
>         --
>
>     end for;
> end testbench_config;
>
> In article <6l853l$cee$1@goanna.cs.rmit.edu.au>, Hamish Moffatt
<hamish@moffatt.nu>
> writes
> >In comp.arch.fpga John Huang <hungi@tpts4.seed.net.tw> wrote:
> >>      I got some questions about Viewlogic/Speedwave,
> >>      I have a design that use VHDL for a FPGA.
> >>      1. Can I use VHDL testbench in the speedwave, if
> >>         it is YES, how will I do?
> >>      2. What simulaors support the VHDL testbench?
> >
> >Aldec's ActiveVHDL seems to run them nicely.
> >
> >>      3. Would you please give me an example for
> >>         write testbench?
> >
> >Best to grab a book eg Skahill's VHDL for Programmable Logic,
> >it has a whole chapter on it. Aldec's also has a thing for generating
> >test benches for you, I haven't tried it.
> >
> >
> >Hamish
>
> --
> William White                 <
>  ------------------------  <  <  <  ----------  Mailto: will@fpga.demon.co.uk
> | Direct Insight Ltd    <  <  <  <  >           Tel: +44 1280 700262       |
> |                          <  <  <              Fax: +44 1280 700577       |
>  ---------------------------  <  ------------------------------------------
>


-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 10716
Subject: DSP Pro's, H/W, S/W, C++, ALL disciplines...
From: "Hunter Int." <cleaner@starnetinc.com>
Date: Thu, 11 Jun 1998 22:01:26 -0500
Links: << >>  << T >>  << A >>
Hi,

We're Hunter International, and we are currently looking for qualified DSP
based Engineering Professionals from a broad variety of disciplines.  Our
client is one of, if not THE, best firms you could be associated with in the
Northern California area.  This beautiful firm, located in the Silicon
Valley, is simply at the top of it's class with opportunities and care for
it's employees.  The benefits are second to none, and the technology is
stellar, so you can't go wrong.  There is even a fully functioning Health
Club built into the premises!  We absolutely guarantee that you will be
thrilled with this firm if you are qualified!

PLEASE note before you read further:  This company is a publicly held,
incredibly successful firm, BUT, because of certain clients, they do require
the ability to secure a Secret Clearance.  This means citizenship of you,
and your direct family to Mother and Father, if they are still living.
Because of this, the candidate pool becomes thin.  So if you are qualified,
AND can get clearance, you will be received with enthusiasm and given the
'red carpet' treatment, as they need engineers in a big way!

In an effort to help with the massive growth they are experiencing, we need
to find Engineers who fall into the areas of expertise listed below.  The
descriptions are intentionally brief, and this is because the amount of
available jobs are more than you could read through in a single post.  All
jobs are new positions, not vacancies.

Software Engineers:

*Experience developing Real-Time, software intensive projects using Ada, C,
C++, in a UNIX, NT, and/or VMS environment.
*Requirements definition, preliminary/detailed design code/unit testing and
software integration.
*Familiarity with OO methodologies, signal processing, telecommunications,
distributed systems, GUI builders, reusable software, relational data bases
and automated test tools.
*Looking for a BS/MS, CS or Math, or equivalent.  Experience much more
important than degree!

DSP Engineers:

*Lead, or be a part of, a multi-functional team working on digital/
DSP/communications subsystems utilizing state of the art design/analysis
tools/techniques and modern packaging.  Responsibilities may include:
Participate in architectural and design trades, generate hardware and
software specifications, simulate/evaluate DSP algorithm, design digital
circuits used in standard and custom interfaces and micro-processor based
designs, design high speed digital logic, develop/code DSP firmware,
implement custom DSP hardware using PLD/FPGA, and test and integrate the
hardware in the subsystem.
*Languages: C or C++ in a UNIX environment, with knowledge of Windows NT a
plus.  Also, knowledge of high speed digital logic, Modem/PLL Datacom
products, embedded control firmware, custom DSP hardware implementation,
ASIC design and methodology a plus.

Hardware Engineer:

*Serve as Technical Leader for small to medium sized projects.  Coordinate
technical efforts of small engineering project teams.
*Perform high level system design.  Develop algorithms for key communication
functions.  Define architecture for state of the art communication products.
*MSEE with emphasis on Communications theory and DSP.  Minimum of 5 years of
related experience.  Experience with SPW, Xilinx, and Viewlogic design
tools.

Please also consider that we need Systems Engineers, Intelligence Engineers,
a variety of Systems Administrators, and Directors also.

The descriptions above are only general!  There are multiple openings in
every area, and the expertise varies from position to position, so please
don't hesitate should you feel there might be a match!

Again, this IS a fantastic company!  You will not be wasting your time if
you decide to respond, and ALL qualified candidates WILL be responded to
very quickly.

Thank you for making it this far, and we hope to hear from you soon!

Contact us at:

Hunter International
Fax:  (815)356-9225, or,
cleaner@starnetinc.com

Our thanks in advance,

Dave Steiger...





















Article: 10717
Subject: Re: AHDL vs. VHDL vs. Verilog HDl
From: eteam.nospam@aracnet.com (bob elkind)
Date: Thu, 11 Jun 1998 20:23:22 -0700
Links: << >>  << T >>  << A >>
Victor Levandovsky said...
> On Wed, 10 Jun 1998 17:39:44 -0700, Gary Helbig <ghelbig@slip.net>
> wrote:
> 
> >I won't get into the VHDL vs/ Verilog argument.  But, AHDL is good
> >for Altera-made chips only, which limits its usefulness.
> >
> >AHDL also has poor documentation, and a few bugs.
> 
> What bug?
> 
> >
> >In other words, Verilog, VHDL; pick one.  Or both.  AHDL, stay away.
> >
> >My opinions only,
> >Gary.

I'm missing an intermediate posting on this thread but...

AHDL has one very compelling virtue:  It is amazingly easy to pick up and 
use successfully.  I've seen Xilinx schematics jockies develop working 
Altera devices, using AHDL for the first time, in a day.  And they are 
amazed, and encouraged.  I've seen the same folks try their hands at VHDL 
and come away muttering and frustrated.

Say what you want about Altera's technology and their design tools, but 
that is a very compelling argument for a lot of my clients!

I haven't seen a VHDL or Verilogs development environment yet that presents 
such a "shallow" learning curve.  If you think there is a comparable 
product, in terms of ease of attaining moderate proficiency, I'd love to 
hear of it.

****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com 
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 10718
Subject: Re: AHDL vs. VHDL vs. Verilog HDl
From: graeme@wallaby.digideas.com.au (Graeme Gill)
Date: 12 Jun 1998 15:43:39 +1000
Links: << >>  << T >>  << A >>
Gary Helbig (ghelbig@slip.net) wrote:
: AHDL also has poor documentation, and a few bugs.

Out of all the help files I ever seen on MS Windows systems,
the on line AHDL documentation would have to be amongst the best -
lots of info, well cross referenced.

Graeme Gill.
Article: 10719
Subject: Free Computer (Read--Easy, No money down)
From: beaver@usa.net (J Klukan)
Date: Fri, 12 Jun 1998 06:07:41 GMT
Links: << >>  << T >>  << A >>
 Want a free computer?  I mean REALLY free--no gimmicks or gags and
really easy to do!  Don't pass up this superb offer.  Here's what you
get:
 -IBM Pentium 233 MMX-classified processor (faster than Intel)
 -Mini-tower case
 -7 expansion slots (5 open)
 -32mb RAM
 -4.3gb hard drive (Quantum or Cyrix)
 -3.5 floppy drive
 -56k flex Fax/Modem
 -Acer 24X CD-ROM drive
 -16-bit MMX sound card
 -Cyrix Logic 5466 full-3D video card (DVD Compatible)
 -80-watt speakers
 -L2 meg cache w/ TXPIO motherboard
 -Digi-View 15" SVGA monitor
 -Windows95 and over 70 software titles
Software includes:
 Microsoft Office97 Professional, Microsoft Internet Explorer 4.0,
 Groliers Multimedia Encyclopedia, 3D Key Design Center, 3D Card
 Design, Video Game Pack, Master Clip 6000 (clipart), Media Wizard
 Design, Bitware, Zoo Explorer, and much more!

And...it's all FREE!!!
 "What's the catch?" you ask.  The catch is not really a catch at all.
All you need to do is sign up 6 people for this program under you.
That's it!  Sign up 6 people for this great program with you as their
sponsor and you're done.  You never need to do anything else with this
program again.  You will have 30 days to sign up these 6
people...which should be no problem.  If you don't sign up all 6 in
time, you will have to begin paying the lease until you have signed up
6 people.  If you sign up 6 or more people, the lease will be paid for
you and as an added bonus, you will receive $150 for every person that
you signed up.  Even if you don't get 6 people within 30 days, if you
get one person you will have $150, which can be applied to the lease
payment.
 "What happens when I've signed up all 6 people?" you ask.  Once you
have signed up 6 or more people, you are under no obligation to
continue participating in this program.  This program is incredible!
 "How do I get involved?"  It's easy.  Go to this web site:
  http://www.camelotenterprises.com/jklukan/
read through the information presented there, and if you're still
interested, follow the instructions there.  If you have any questions,
feel free to e-mail me (this address and the one listed there end up
at the same mailbox) and I'll try to answer them.
 Thank you for your interest!

-Jeremy

PS:  This is not spam.  I have posted it to newsgroups that I have
found computer-related material in.  Please do not criticize me for
that.


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Keith Christensen   <radiopro@gte.net >
309093
I am a Washington State resident! Spamming me is subject
to  a $500 (or more) penalty. Complaints WILL be sent to:
your provider and the Wa. Attorney General's Office. Be
warned that I reserve the right to post any unsolicited
messages to public newsgroups as well!




Article: 10720
Subject: Re: TESTBENCH
From: David Pashley <David@fpga.demon.co.uk>
Date: Fri, 12 Jun 1998 10:15:16 +0100
Links: << >>  << T >>  << A >>
In article <6lq05h$dj7$1@nnrp1.dejanews.com>, leslie.yip@asmpt.com
writes
>Dear William White
>
>How can I use SpeedWave to do testbenches? In the past, I used ModelSim's
>V-System to do testbenches. Yet I know SpeedWave requires synthesis before,
>right?
>
<Will's testbench guidelines snipped>

No.

SpeedWave is a Windows-based VHDL simulator supporting full 1076 VHDL
and VITAL. So is ModelSim.

Therefore you can simulate the design together with its testbench in
SpeedWave both before and after implementation of that design.

SpeedWave and ModelSim are two directly competing products, one belongs
(via Viewlogic Systems) to Synopsys, and the other to Mentor. 

SpeedWave, Viewsim and VCSi are, respectively, the VHDL, Gate-level and
Verilog simulation engines within the Viewlogic Fusion environment. The
user sees a single GUI, with Fusion calling whichever simulators are
needed during simulation of the various components of the design
hierarchy.

I hope this helps - I sense your confusion is merely to do with product
names!

In Will's absence (he's on the beach in Majorca!)

-- 
David Pashley                 <
 ------------------------  <  <  <  ---------- Mailto: david@edasource.com
| Direct Insight Ltd    <  <  <  <  >            Tel: +44 1280 700262      |
|                          <  <  <               Fax: +44 1280 700577      |
 ---------------------------  <  ------------------------------------------
Article: 10721
Subject: Fastest and biggest FPGA fast and big enough?
From: Lars <larsher@online.no>
Date: Fri, 12 Jun 1998 12:35:12 +0200
Links: << >>  << T >>  << A >>
Hi,
What are the fastest and biggest FPGA available in samples within next
few months?

The reason for me asking is that we have a large design that has to run
fast, 66MHz. I know this does not sound too hard, but within these 15ns
a 64 bit magnitude comparing (data greater or less than a register
value) and 180 bit equality comparing has to be done. This plus alot of
other logic adds up to over 100K ASIC gates. So the FPGA has to be big.
We can accept pipelineing to some extent, but this requires also more
resources in registers to hold data.

The alternative is of cource ASIC, but our vloumes are low, so FPGA
would be great.

Has anyone done 64 bit magnitude comparator in an FPGA before?
Does anyone have a feel about if this is feasable or not in an FPGA?
Any input from you FPGA experts would be nice.
Article: 10722
Subject: book on ASIC
From: "Arie Zychlinski" <ariez@ibm.net>
Date: Fri, 12 Jun 1998 17:14:44 +0300
Links: << >>  << T >>  << A >>
I am an experienced user of FPGAs, doing also conversion to ASIC from FPGAs.
Yet, (as the conversion is done in Orbit, AMI, ...) I have lack of knowledge
on the ASIC field (such as , but NOT only: the processes during the
production, the impact on using gate-array vs. standard-cell and other
issues.)

I am looking for a recommendation on a tutorial book. Can any one suggest
one ?

Thank you in advance.




Article: 10723
Subject: old PLDShell software wanted
From: rkoblish@my-dejanews.com
Date: Fri, 12 Jun 1998 14:53:32 GMT
Links: << >>  << T >>  << A >>
I am tasked with understanding an old design that used the Altera EP1210,
which is equivalent to the Intel 5C121. Both of these PLDs are long since
discontinued. I have the Jedec files but no logic equations.

I have PLDShell versions 4 and 5, both of which appear to be too new to
understand the EP1210/5C121. Altera's tech support had a datasheet for the
part, but no old software available.

Can anyone point me to, or send me, a version of PLDShell old enough to cover
this part, or another means of disassembling the Jedec file to recover the
logic equations?

Thanks in advance,
Bob Koblish

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 10724
Subject: Re: Fastest and biggest FPGA fast and big enough?
From: husby@fnal.gov (Don Husby)
Date: Fri, 12 Jun 1998 15:00:14 GMT
Links: << >>  << T >>  << A >>
larsher@online.no wrote:
> The reason for me asking is that we have a large design that has to run
> fast, 66MHz. I know this does not sound too hard, but within these 15ns
> a 64 bit magnitude comparing (data greater or less than a register
> value) and 180 bit equality comparing has to be done. This plus alot of
> other logic adds up to over 100K ASIC gates. So the FPGA has to be big.
> We can accept pipelineing to some extent, but this requires also more
> resources in registers to hold data.

Lucent does pretty good with wide functions.  They claim to have their
3T80 part available now.
Adding up the numbers for the -6 Speed grade, it can do a 64-bit arithmetic
function in ~13ns.  If you include routing delays, this will probably
exceed your 15ns requirement.

However, it's very easy to pipeline this function.  Registers are essentially
free.  A 2-deep 64-bit pipelined comparator with input and output 
registers would take  9 PFU (Programmable Funcion Units) which is about
2% of the 3T80.  (A single PFU can be an 8-bit comparator with 8-bit register 
at its input and 1-bit register at its output)
My guess is that this could easily run at 100MHz with their -5 speed grade.

A 180-bit pipelined equality comparator would also have similar performance.
Each PFU can do a 16-bit equality-compare.  SLICs (Supplimental Logic and
Interconnect Cells) can be used to OR the outputs.  My guess is that it would 
take less than 15 PFU to implement this function and could possibly be
done in a single 15ns cycle.  It would take 23 PFU if you want to include a 
180-bit input register.  The 3T80 has 484 PFU arranged in a 22x22 array.

Also, if the number you are comparing to can be hard-wired (or firm-wired), 
the logic becomes much smaller and faster because it can be coded directly
into the logic blocks.  Then it might be possible to compare as many as 32
bits per PFU (probably limited by routing to ~24).











> 
> The alternative is of cource ASIC, but our vloumes are low, so FPGA
> would be great.
> 
> Has anyone done 64 bit magnitude comparator in an FPGA before?
> Does anyone have a feel about if this is feasable or not in an FPGA?
> Any input from you FPGA experts would be nice.


--
Don Husby <husby@fnal.gov>                        Phone: 630-840-3668
Fermi National Accelerator Lab                      Fax: 630-840-5406
Batavia, IL 60510


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