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Messages from 13925

Article: 13925
Subject: NOW IS: 20V01, A Logic Idiocy (IS: 2001, A Logic Odyssey (WAS: 22V10 Metastability - help please))
From: rk <stellare@NOSPAMerols.com>
Date: Sat, 02 Jan 1999 17:56:46 -0500
Links: << >>  << T >>  << A >>
Magnus Homann wrote:

> rk <stellare@NOSPAMerols.com> writes:
>
> > the logic in a gray coded state machine can glitch as much as it
> > wants, it's a don't care, as it only cares about what happens at the
> > clock edge.  if you choose to insert an asynchronous input into the
> > combinational logic of a state machine, any state machine, then you
> > can have problems, irregardless of what the coding is.
>
> Exactly. You seem to agree that gray coding a SM is not a cure-all for
> asynchronous inputs to SMs.

of course.  the state assignment of a sequencer doesn't excuse the designer
of following reliable design practices; as i stated before, a state machine
with a gray code state assignment is useful if another circuit will capture
the states, asynchronously, resulting in a small error.  if all the inputs
to the sequencer with a gray code state assignment glitch, yoiu have a POS.

happy new year,

rk

Article: 13926
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: rk <stellare@NOSPAMerols.com>
Date: Sat, 02 Jan 1999 18:17:13 -0500
Links: << >>  << T >>  << A >>
Ron Cline wrote:

> Hal Murray wrote:
> >
> > What happens to metastability if I build a FF with something
> > really strange like Josephson Junctions?
>
> A Josephson Junction, inherently a latch, will be metastability free, as
> will any other quantum device.  It just picks a universe to exist in.

not my area, but carver and mead write in _intro to vlsi systems_:

we might ask if metastable behavior is possible during transitions between
the discrete eigenstates of a quantum mechanical system.  if we interrupt a
quantum mechanical transition midway, we are left with a system with equal
probability of being in either state.  since the states now have equal
energies, there is no preferred direction to the transition.  this situation
is the quantum equivalent of the "hung" flip-flop.  even after an
arbitrarily long time, there is a finite probability that the system will
not have recovered from its mixed state.  quantum mechanics offers no escape
from the possibility of incomplete transitions. designers must cope with the
phenomenon of metastability at a system level, as discussed in chapter 7.

happy new year,

rk

Article: 13927
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: Ron Cline <rcline@swcp.com>
Date: Sat, 02 Jan 1999 17:11:02 -0700
Links: << >>  << T >>  << A >>
rk wrote:
> 
> Ron Cline wrote:
> 
> > A Josephson Junction, inherently a latch, will be metastability free, as
> > will any other quantum device.  It just picks a universe to exist in.
> 
> not my area, but carver and mead write in _intro to vlsi systems:
> 
> we might ask if metastable behavior is possible during transitions between
> the discrete eigenstates of a quantum mechanical system.  if we interrupt a
> quantum mechanical transition midway, we are left with a system with equal
> probability of being in either state.  since the states now have equal
> energies, there is no preferred direction to the transition.  this situation
> is the quantum equivalent of the "hung" flip-flop.  even after an
> arbitrarily long time, there is a finite probability that the system will
> not have recovered from its mixed state.  quantum mechanics offers no escape
> from the possibility of incomplete transitions. designers must cope with the
> phenomenon of metastability at a system level, as discussed in chapter 7.

Not my area, either ... my layman's understanding, however, is that the
the system can only be in a superposition of states as long as it is not
being sampled or measured.  At the point that the "latch is read," only
one state or the other can exist, with no delay.

I'll bow to any higher authority on this...

Happy 1999.

-- RLC

Article: 13928
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: wen-king@myri.com (Wen-King Su)
Date: 2 Jan 1999 18:37:40 -0800
Links: << >>  << T >>  << A >>
In a previous article rk <stellare@NOSPAMerols.com> writes:
:
;Wen-King Su wrote:

;> That is still amplified noise, even though it is the switching noise of
:> the buffer itself that is getting amplified.  Meta-stable condition is a
;> different beast, for it is something that still exists when all noises
:> are eliminated.  Funny thing about your example is if you write in the
;> parasitic capacitances and inductances explicitly in the feedback path
:> of your circuit representation, what you have is no longer amplified noise
;> but a bona fide oscillation.  Noise is merely a poorly characterized signal.
:> When you put the parasitic elements into your circuit representation, you
;> ended up defining part of it.
:
;good morning, wen-king:
:
;i was responding to peter from X's point, i believe, that buffers could
:oscillate, not merely amplify noise.

That is not the way I read it.  He said latches don't oscillate, but the
next buffer stage can "oscillate" when the latch's output is stuck in a
meta-stable state.  I don't see how he could have been talking about the
hidden feedback loop in one while ignoring an explicit one in the other.

In any case, parasitic capacitances and inductances are typically considered
to be something that is in addition to a named device.  Thus it is the
R+C+inverter network that oscillates, not the inverter itself. The inverter
still just amplifies whatever signals there is in its input; and when
those signals are poorly defined spurious signals, they are properly
called noise.

Article: 13929
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: rk <stellare@NOSPAMerols.com>
Date: Sat, 02 Jan 1999 22:17:15 -0500
Links: << >>  << T >>  << A >>
good evening, wen-king,

=======================================

Wen-King Su wrote:

> In a previous article rk <stellare@NOSPAMerols.com> writes:
> :
> ;Wen-King Su wrote:
>
> ;> That is still amplified noise, even though it is the switching noise of
> :> the buffer itself that is getting amplified.  Meta-stable condition is a
> ;> different beast, for it is something that still exists when all noises
> :> are eliminated.  Funny thing about your example is if you write in the
> ;> parasitic capacitances and inductances explicitly in the feedback path
> :> of your circuit representation, what you have is no longer amplified noise
> ;> but a bona fide oscillation.  Noise is merely a poorly characterized signal.
> :> When you put the parasitic elements into your circuit representation, you
> ;> ended up defining part of it.
> :
> ;good morning, wen-king:
> :
> ;i was responding to peter from X's point, i believe, that buffers could
> :oscillate, not merely amplify noise.
>
> That is not the way I read it.  He said latches don't oscillate, but the
> next buffer stage can "oscillate" when the latch's output is stuck in a
> meta-stable state.  I don't see how he could have been talking about the
> hidden feedback loop in one while ignoring an explicit one in the other.

well, perhaps you read it wrong, perhaps my writing stinks.  in any event, my post
was quite specific, that a buffer will oscillate.  here's what i wrote:

        hmmm ... i believe that you can get a buffer to oscillate.

looks pretty clear to me, but then again i did write it (i'm an engineer, not a
wordsmith!).

for peter from X's (not xilinx) statement about the latch not oscillating and the
next stage will, i suggest that you take that up with him.

==============================================================

> In any case, parasitic capacitances and inductances are typically considered
> to be something that is in addition to a named device.

if you wish to define things that way, then that is ok, but i don't think that
would be considered the general usage of the term.  for example, if i was to take a
sawtooth waveform and put it into the input buffer of a chip and observed
oscillation as the slope of the signal was decreased, i would say that the input
buffer oscillates when you don't meet the transition time requirements.

however, i could probably say that the system consisting of the input buffer, power
and ground connections, bond wires, circuit card inductances, gate to source
capacitances, gate to drain capacitances, parasitics in the bypass capacitors
oscillates would tend to be a bit, well, wordy.  i think that the way i said it is
more readily accepted mumbo jumbo (or lingo or jargon or buzzwords if you prefer
:-).

i would disagree to a certain extent, i would say that capacitance between the
buffer's gate and source, for example, is part of the device.  just like the
parasitic inductance of a wire-wound resistor is part of the resistor.  if you
model one of those resistors as, well, a resistor, then you are, of course, gonna
be screwed.  i would say that a resistor model would include the parasitics.  then
again, for a capacitor, say, i'd count the parasitic circuit elements that are part
of the leads.  this way of thinking about it tends to help, as you will quickly
start deleting the leads and get those nice little surface mount caps, as the
properties of the cap itself, w/out the parasitics that are there in the real
circuit, is not nearly as valuable.

=================================================================

>
> Thus it is the
> R+C+inverter network that oscillates, not the inverter itself.

don't forget the L, please.  however you look at it, you can make the buffer +
assorted mumbo jumbo oscillate like a sunofab*tch, in most instances.  some of the
older slower technologies would just go linear.

==================================================================

>                                                                               The
> inverter
> still just amplifies whatever signals there is in its input; and when
> those signals are poorly defined spurious signals, they are properly
> called noise.

sorry, i believe you are referring to an ideal amplifier.  i think most transistor
amplifiers in the class of circuits we're taling about will have parasitic
components that do couple back to the gate, affecting the circuit operation.  from
a more practical standpoint, if you go down to the store, pick up a nice precision
sawtooth wave generator, set it up for a nice and mellow ramp rate, and stick it
into a high-speed input buffer, you will see it break into oscillation.  and the
output waveform will not be just an amplification of noise.

===================================================================

good night!

happy year 2k-1,

rk




Article: 13930
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: "Bruce Nepple" <brucen@imagenation.extra_words.com>
Date: Sun, 03 Jan 1999 05:58:16 GMT
Links: << >>  << T >>  << A >>


Wen-King Su <wen-king@myri.com> wrote in article
<76j71s$l8g@neptune.myri.com>...
| In a previous article rk <stellare@NOSPAMerols.com> writes:
| :
| ;Wen-King Su wrote:
| :
| ;> In a previous article "Bruce Nepple" <brucen@imagenation.extra.com>
writes:
| :>
| ;> ;If a cross coupled latch does not go unstable when there is a race on
its
| :> :input, then why is it not, then, a metastable free synchronizer?
(which
| ;> ;according to theories I am familiar with, is impossible).
| :>
| ;> Metastable does not equate oscillation.  When output stays in the
illegal
| :> region for an extented period of time, even if it is not oscillating,
it
| ;> is still called metastable.  Oscillation-free synchronizer does exist
and
| :> is being used in many places.
| ;
| :to summarize from what i have read, if a flip-flop goes "metastable" it
may:
| ;
| :    1. oscillate
| ;
| :    2. transition to one value and then return to the original one
| ;
| :    3. have a delayed propagation delay time
| ;
| :    4. hang out at non-logic levels.
| 
| The word meta-stable refers to a system that remains in a state near a
| local energy maximum because all the forces acting on it more or less
| canceled out.  The little imballance in forces eventually will push the
| system away from the local maximum, but the amount of time it takes is
| unbounded. 
| 
| When there is an oscillation in a properly designed latch, the output
| state itself is not meta-stable.  It is the state of the oscillatory
| behavior that is meta-stable.  The latch is bi-stable with respect to its
| output state, but mono-stable with respect to its oscillatory behavior.
| That means the output eventually settles into one of two states, and the
| oscillatory behavior eventually settle to the state of non-oscillation.
| A properly designed oscillator is also mono-stable with respect to its
| oscillatory behavior, except the stable point is when the circuit is
| oscillating.  An oscillator made of an odd number of inverters does not
| have a stable output state.  It is astable with respect to output state.
| 
| It is not possible to design a latch that will never be excited into a
| meta-stable state with respect to its output, for at some point in its
| operation it has to make transition across the meta-stable point -- or
| else you didn't need to have a latch.  But it is possible to design one
| that will never be excited into a meta-stable state with respect to its
| oscillatory behavior.  Or more precisely you can say it will not be
excited
| into a state where its oscillatory behavior will stay meta-stable for
| longer than some fraction of the cycle time of any possible oscillation.
| 

I agree with everything you guys have said to date.  My point was not that
modern digital circuits oscillate, but that a simple thought exercize can
illustrate the roots of meta-stable behavior, and remove some of the
mystery.  I think classic metastability becomes the result when you have
slower rise-fall times relative to the prop delay allowing the device to
settle at its thresholds rather than act like a ring oscillator.

I'll have to admit that in my example, technically, the oscillating state
itself, not the latch, is metastable.  Never thought of it that way.

Good Stuff!  

Bruce

Article: 13931
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: "Bruce Nepple" <brucen@imagenation.extra_words.com>
Date: Sun, 03 Jan 1999 06:11:35 GMT
Links: << >>  << T >>  << A >>
I wish I knew the answer to what you would see with 7400 gates.  At the
very least you will see classic metastability.

Your point about slew rates is the real issue.  The slow slew rates can
cause the latch to hang in an analog state, which is the classic metastable
state.

So, given the prop-delay/rise/fall time characteristics of 7400 gates, what
will happen?  Will it behave at all like a 2 stage ring oscillator?  I'm
not sure.

Bruce

Frank Bemelman <fbemelx@euronet.nl> wrote in article
<76ir1b$25h6$2@beast.euro.net>...
| Bruce Nepple heeft geschreven in bericht ...
| >Peter, you seem to be missing the point which is that the
| cross coupled
| >2 nand gates with 1 ns prop delay and 0 ns. rise/fall time,
| are connected as
| >a simple RS latch.  The R and S inputs are connected
| together.  Initially
| >they are connected to ground, and then are brought to logic
| 1.  The ideal
| >latch then oscillates forever (as a digital ring
| oscillator).
| 
| 
| Not knowing very much about digital stuff, I apologize for
| my possibly stupid thoughts,
| but post them anyway here:
| 
| I can understand that this ideal flipflop oscillates like
| mad at 500 mhz or would it oscillate at perhaps 250 mhz ?
| 
| Assuming 5 volts vcc, and rise/fall 2.5 volts/ns, would the
| flipflop then go into a stable condition with logic ouput
| levels at 2.5 volts ?
| 
| What interests me now is, what happens if one gate has 1 ns
| prop delay, and the other one 1.1 ns prop delay. It would
| not oscillate forever anymore (I suppose) but how many
| oscillations would occur before it's stable ?
| 
| Also, if prop delays are exactly 1 ns, and rise/fall is 10
| ns, does it oscillate also ? In my imagination it would
| oscillate. I am now under the impression that equal gates
| would always oscillate ?
| 
| Apart from these ''ideal'' flipflops, what are my chances to
| see a few oscillations if I simply take an old 7400
| nand-gate and wire them for this experiment ? I would have
| done that already, but unfortunately I do not have an
| oscilliscope here.
| 
| Happy new year,
| Frank Bemelman
| (reageren per email ? verwijder dan de 'x' uit mijn
| emailadres)
| 
| 
| 

Article: 13932
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: wen-king@myri.com (Wen-King Su)
Date: 2 Jan 1999 22:52:11 -0800
Links: << >>  << T >>  << A >>
In a previous article rk <stellare@NOSPAMerols.com> writes:
:
;Wen-King Su wrote:

:> In any case, parasitic capacitances and inductances are typically considered
;> to be something that is in addition to a named device.
:
;if you wish to define things that way, then that is ok, but i don't think that
:would be considered the general usage of the term.  for example, if i was to take a
;sawtooth waveform and put it into the input buffer of a chip and observed
:oscillation as the slope of the signal was decreased, i would say that the input
;buffer oscillates when you don't meet the transition time requirements.

My usage is the general usage.  The properties that are generally considered
to be part of a buffer are those you find in a data sheet -- propogation
delay, output rise and fall time, power consumption, etc.  When I see the
buffer's output switches back and forth between 1 and 0, I would call it
amplified noise because there is no information for me to know which part
of what I see came from a feed back loop involving the the buffer.  I
would have seen exactly the same thing even if the buffer is not involved
in an oscillation.  Poorly characterized signal in this case is properly
called noise whereever it came from.

;however, i could probably say that the system consisting of the input buffer, power
:and ground connections, bond wires, circuit card inductances, gate to source
;capacitances, gate to drain capacitances, parasitics in the bypass capacitors
:oscillates would tend to be a bit, well, wordy.  i think that the way i said it is
;more readily accepted mumbo jumbo (or lingo or jargon or buzzwords if you prefer
::-).

It is an accepted practice to lump together all of that which is not well
characterized into a noise source.  And when a parasitic element is
characterized, it can then be factored out of the noise source and added
to the circuit representation as a separate component from the
 buffer itself. 

:> Thus it is the
;> R+C+inverter network that oscillates, not the inverter itself.
:
;don't forget the L, please.  however you look at it, you can make the buffer +
:assorted mumbo jumbo oscillate like a sunofab*tch, in most instances.  some of the
;older slower technologies would just go linear.
:
;==================================================================
:
;>                                                                               The
:> inverter
;> still just amplifies whatever signals there is in its input; and when
:> those signals are poorly defined spurious signals, they are properly
;> called noise.
:
;sorry, i believe you are referring to an ideal amplifier.  i think most transistor
:amplifiers in the class of circuits we're taling about will have parasitic
;components that do couple back to the gate, affecting the circuit operation.  from
:a more practical standpoint, if you go down to the store, pick up a nice precision
;sawtooth wave generator, set it up for a nice and mellow ramp rate, and stick it
:into a high-speed input buffer, you will see it break into oscillation.  and the
;output waveform will not be just an amplification of noise.

I am referring to what is commonly called an inverter, not an ideal
inverter.  An ideal inverter would not have such things as propogation
delay or output rise time.  What you have got on silicon is not just an
inverter, but transistors that implement an inverter plus a set of parasitic
elements.  When the signal source is poorly characterized, it is proper
to call it noise.  If I set up a nice sawtooth wave generator, set it up
for a nice and mellow ramp rate, and stick it into a high-speed input
buffer, what I would see is amplified noise when input is near a certain
value.  And any potential oscillation involving the inverter and the
parasitic elements, being poorly characterized, is simply regarded as
noise that has the potential of sneaking into the input of the inverter.

Article: 13933
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: alexs@seanet.com (Alexander Stoll)
Date: Sun, 03 Jan 1999 06:58:10 GMT
Links: << >>  << T >>  << A >>
On Sat, 02 Jan 1999 22:17:15 -0500, rk <stellare@NOSPAMerols.com>
wrote:

>sorry, i believe you are referring to an ideal amplifier.  i think most transistor
>amplifiers in the class of circuits we're taling about will have parasitic
>components that do couple back to the gate, affecting the circuit operation.

I was wondering when the reality check would be performed.
If one talks about the abstract, philosophical aspects of
metastability, then we can go around the block on this
indefinitely.  Reduced to practice, there are always
parasitics etc which spoil the sterile, simplified argument.

Article: 13934
Subject: Gamma correction in YUV space
From: Armin Mueller <ual6@rz.uni-karlsruhe.de>
Date: Sun, 03 Jan 1999 21:22:31 +0100
Links: << >>  << T >>  << A >>
Hello,

I know the Gamma correction is normally done in the
RGB color space (by component).

Would it be possible to do the Gamma directly in YUV terms?
Sure, the exp-function can't be added, but maybe there are
some simplifications...

Armin

Article: 13935
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: rk <stellare@NOSPAMerols.com>
Date: Sun, 03 Jan 1999 17:56:19 -0500
Links: << >>  << T >>  << A >>
yup, it's noise, just like this thread!

rk

p.s. but whateveryoucallit, it'll oscillate like a sonab*tch.

p.s.s. take your buffer, delete those parasitic things like bond wires and all, and it
won't buffer anything, just lie there like a dead dog, unpowered.

================================================

Wen-King Su wrote:

> In a previous article rk <stellare@NOSPAMerols.com> writes:
> :
> ;Wen-King Su wrote:
>
> :> In any case, parasitic capacitances and inductances are typically considered
> ;> to be something that is in addition to a named device.
> :
> ;if you wish to define things that way, then that is ok, but i don't think that
> :would be considered the general usage of the term.  for example, if i was to take a
> ;sawtooth waveform and put it into the input buffer of a chip and observed
> :oscillation as the slope of the signal was decreased, i would say that the input
> ;buffer oscillates when you don't meet the transition time requirements.
>
> My usage is the general usage.  The properties that are generally considered
> to be part of a buffer are those you find in a data sheet -- propogation
> delay, output rise and fall time, power consumption, etc.  When I see the
> buffer's output switches back and forth between 1 and 0, I would call it
> amplified noise because there is no information for me to know which part
> of what I see came from a feed back loop involving the the buffer.  I
> would have seen exactly the same thing even if the buffer is not involved
> in an oscillation.  Poorly characterized signal in this case is properly
> called noise whereever it came from.
>
> ;however, i could probably say that the system consisting of the input buffer, power
> :and ground connections, bond wires, circuit card inductances, gate to source
> ;capacitances, gate to drain capacitances, parasitics in the bypass capacitors
> :oscillates would tend to be a bit, well, wordy.  i think that the way i said it is
> ;more readily accepted mumbo jumbo (or lingo or jargon or buzzwords if you prefer
> ::-).
>
> It is an accepted practice to lump together all of that which is not well
> characterized into a noise source.  And when a parasitic element is
> characterized, it can then be factored out of the noise source and added
> to the circuit representation as a separate component from the
>  buffer itself.
>
> :> Thus it is the
> ;> R+C+inverter network that oscillates, not the inverter itself.
> :
> ;don't forget the L, please.  however you look at it, you can make the buffer +
> :assorted mumbo jumbo oscillate like a sunofab*tch, in most instances.  some of the
> ;older slower technologies would just go linear.
> :
> ;==================================================================
> :
> ;>                                                                               The
> :> inverter
> ;> still just amplifies whatever signals there is in its input; and when
> :> those signals are poorly defined spurious signals, they are properly
> ;> called noise.
> :
> ;sorry, i believe you are referring to an ideal amplifier.  i think most transistor
> :amplifiers in the class of circuits we're taling about will have parasitic
> ;components that do couple back to the gate, affecting the circuit operation.  from
> :a more practical standpoint, if you go down to the store, pick up a nice precision
> ;sawtooth wave generator, set it up for a nice and mellow ramp rate, and stick it
> :into a high-speed input buffer, you will see it break into oscillation.  and the
> ;output waveform will not be just an amplification of noise.
>
> I am referring to what is commonly called an inverter, not an ideal
> inverter.  An ideal inverter would not have such things as propogation
> delay or output rise time.  What you have got on silicon is not just an
> inverter, but transistors that implement an inverter plus a set of parasitic
> elements.  When the signal source is poorly characterized, it is proper
> to call it noise.  If I set up a nice sawtooth wave generator, set it up
> for a nice and mellow ramp rate, and stick it into a high-speed input
> buffer, what I would see is amplified noise when input is near a certain
> value.  And any potential oscillation involving the inverter and the
> parasitic elements, being poorly characterized, is simply regarded as
> noise that has the potential of sneaking into the input of the inverter.



Article: 13936
Subject: Re: Can a cross coupled latch "oscillate"? was Re: ..........
From: wen-king@myri.com (Wen-King Su)
Date: 3 Jan 1999 19:16:41 -0800
Links: << >>  << T >>  << A >>
In a previous article rk <stellare@NOSPAMerols.com> writes:
:
;yup, it's noise, just like this thread!
:
;rk
:
;p.s. but whateveryoucallit, it'll oscillate like a sonab*tch.

Not necessarily.  Whether it would oscillate depends on loop-gain vs
frequency.  When the parasitics are not well characterized, you cannot
tell by looking at the output whether part of it is due to the buffer
and the parasitics acting as an oscillator. 

;p.s.s. take your buffer, delete those parasitic things like bond wires and all, and it
:won't buffer anything, just lie there like a dead dog, unpowered.

Bond wire is not parasitic.  It is an ideal bond wire plus parasitics.
When parasitic capacitances are deleted, they are replaced with open
circuit.  When parasitic inductances and resistance are deleted, they are
replaced with a short circuit.  Hence deleting parasitics from the
transistors that implemented a buffer will leave behind a functional
buffer with no parasitics. 

Article: 13937
Subject: IS: y2k-1 problem: when is this year gonna end???????? (WAS: Re: Can a cross coupled latch "oscillate"? was Re: .........._
From: rk <stellare@NOSPAMerols.com>
Date: Sun, 03 Jan 1999 22:50:11 -0500
Links: << >>  << T >>  << A >>
Wen-King Su wrote:

> In a previous article rk <stellare@NOSPAMerols.com> writes:
> :
> ;yup, it's noise, just like this thread!
> :
> ;rk
> :
> ;p.s. but whateveryoucallit, it'll oscillate like a sonab*tch.
>
> Not necessarily.  Whether it would oscillate depends on loop-gain vs
> frequency.  When the parasitics are not well characterized, you cannot
> tell by looking at the output whether part of it is due to the buffer
> and the parasitics acting as an oscillator.

you got me here, yes or no?  if i hook up the slow waveform to the input, i measure
oscillation on the output, and in most cases can see the signal also superimposed onto the
input line, too, and i don't see noise from my signal generator but a nicely controlled
frequency, THEN THE CIRCUIT IS
OSCILLATING!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

you seem quite hung up on definitions.  me, dunno much 'bout nuttin', just a little 'ol
uneducated boy from new york, taught myself some of that engineering stuff by the glow of
the tv watching taped NY Ranger games mailed to me by mom in new york when i was in that
land of barbarians, los angeles.  so please, permit me one little 'ol definition that i can
call my own.  when the device starts oscillating, not amplifying noise on the signal being
fed it, IT'S OSCILLATIONG LIKE A SONOFAB*TCH. (*)

(*) all asteriks represent the fact that this is a family channel.

===================================================

> ;p.s.s. take your buffer, delete those parasitic things like bond wires and all, and it
> :won't buffer anything, just lie there like a dead dog, unpowered.
>
> Bond wire is not parasitic.  It is an ideal bond wire plus parasitics.
> When parasitic capacitances are deleted, they are replaced with open
> circuit.  When parasitic inductances and resistance are deleted, they are
> replaced with a short circuit.  Hence deleting parasitics from the
> transistors that implemented a buffer will leave behind a functional
> buffer with no parasitics.

if you delete the parasitics from the transistors, and you delete the parasitics from the
metal traces, and you delete the parasitics of the bond wires, and you delete parasitics
from the package leads, and you delete the parasitics of the bypass caps, know what you
got?  a very nice circuit.  and do you know it's operating region?  fantasy land.

============================================================

good night,

hey, anybody see my wire cutters?  time to cut this phone cord, my computer is babbling at
me and i'm actually answering it.

rk

p.s. note to the reader: i'm writing, i hate writing, so this is my re-lax-a-tion.

p.s.s. got 1 1/4 pages left to write tonight, so perhaps i'll need a response to this for
my next break.

Article: 13938
Subject: Re: Gamma correction in YUV space
From: bob elkind <eteam@aracnet.com>
Date: Mon, 04 Jan 1999 00:23:22 -0800
Links: << >>  << T >>  << A >>
Sure, since there is a 1-to-1 mapping of YUV space coordinates to RGB space coordinates.

BUT:

1.  Since the Gamma correction is generally a correction of RGB displays, the "simplest" solutions tend to be implemented in RGB
colour space.

2.  When you're done convoluting the YUV values, it isn't always obvious that the results will map to a valid/legal set of RGB
values.  Remember that U and V components are signed magnitude, not unsigned values.  Add "pad" bits to guard against underflow
and overflow, and be careful when using off-the-shelf colour space converter chips.

My $.02

-- Bob Elkind

Armin Mueller wrote:

> Hello,
>
> I know the Gamma correction is normally done in the
> RGB color space (by component).
>
> Would it be possible to do the Gamma directly in YUV terms?
> Sure, the exp-function can't be added, but maybe there are
> some simplifications...
>
> Armin

--
****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****


Article: 13939
Subject: Re: PLL in FPGAs?
From: "Martin Duffy" <martin_duffy@penarth31.freeserve.co.uk>
Date: Mon, 4 Jan 1999 08:57:31 -0000
Links: << >>  << T >>  << A >>
Brett

Check out DynaChip FPGAs on www.dyna.com.
Their DY6000 family have 2 on-chip analog PLLs.

Martin Duffy, Ambar Components (UK)

Brett George wrote in message <367F428F.5641E93E@clarityeq.com>...
>Hi all,
>
>Has anyone tried implementing a PLL in an FPGA (eg. ALTERA), we are
>thinking of using it to reduce clock jitter from an externally generated
>clock source.
>Do they come in Macrofunctions?
>Whal would be the accuracy of such a PLL?
>eg. If the incoming clock had a frequency of 48kHz with jitter of 20 ns,
>would
>the implemented PLL be able to reduce the jitter to 1ns?
>
>The delay throught the FPGA is not a problem, just the jitter.
>
>Thanks in advance,
>Brett.
>


Article: 13940
Subject: Re: How to import EDIF file in Foundation Software?
From: Le mer Michel <michel.lemer@ago.fr>
Date: Mon, 04 Jan 1999 10:33:48 +0100
Links: << >>  << T >>  << A >>
Stuart Clubb wrote:

> On Thu, 31 Dec 1998 09:36:11 +0100, Le mer Michel
> <michel.lemer@ago.fr> wrote:
>
> >So why did xilinx say us we needed Xilinx Foundation and Xilinx Alliance and asked us
> >to PAY for both?
>
> Perhaps the salesperson misunderstood your existing design entry
> requirements?
>
> Cheers
> Stuart
> An employee of Saros Technology, The HDL Solutions Company:
> Renoir
> Model Technology
> Exemplar Logic
> TransEDA
> www.saros.co.uk
> (I sell these products, so paint me biased)

They understood it as they liked it (payed).

Michel.

Article: 13941
Subject: Re: Array Range Legal?
From: "Kenneth Elmkjaer Larsen" <elmkjaer@post3.tele.dk>
Date: Mon, 4 Jan 1999 15:17:34 +0100
Links: << >>  << T >>  << A >>
Hi Rk, yes this is legal vhdl
/Kenneth

rich katz skrev i meddelelsen <36687FA3.A8A81595@gsfc.nasa.gov>...
>hi,
>
>is the following code legal vhdl, with the starting and ending index the
>same?
>
>        ZData : Out Std_Logic_Vector(0 downto 0)
>
>it's the output of vhdl-generating software and normally is a
>multiple-bit bus - however, the architecture permits single bit
>outputs.  is this ok or does it need to be recoded to be a Std_Logic
>signal.
>
>thanks a bunch
>
>rk
>


Article: 13942
Subject: Re: IS: y2k-1 problem: when is this year gonna end???????? (WAS: Re: Can a cross coupled latch "oscillate"? was Re: .........._
From: wen-king@myri.com (Wen-King Su)
Date: 4 Jan 1999 06:28:40 -0800
Links: << >>  << T >>  << A >>
In a previous article rk <stellare@NOSPAMerols.com> writes:
:
;Wen-King Su wrote:
:
;> In a previous article rk <stellare@NOSPAMerols.com> writes:
:> :
;> ;yup, it's noise, just like this thread!
:> :
;> ;rk
:> :
;> ;p.s. but whateveryoucallit, it'll oscillate like a sonab*tch.
:>
;> Not necessarily.  Whether it would oscillate depends on loop-gain vs
:> frequency.  When the parasitics are not well characterized, you cannot
;> tell by looking at the output whether part of it is due to the buffer
:> and the parasitics acting as an oscillator.
;
:you got me here, yes or no?  if i hook up the slow waveform to the input, i measure
;oscillation on the output, and in most cases can see the signal also superimposed onto the
:input line, too, and i don't see noise from my signal generator but a nicely controlled
;frequency, THEN THE CIRCUIT IS
:OSCILLATING!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

You need to know the source of that superimposed input waveform. Otherwise
it could be that your scope probe is picking up RF interferience from the
output, or it could be the input lead is picking up the signal from some
where else.  It could even be that they were coupled back from the output
as would happen with an oscillator, but the circuit was merely acting as
a resonator to another noise source.  In any case, if the superimposed
waveform is actually there what the buffer part of the functionalities
implemented by the transistors on the chip is doing is to amplify the
noise it sees in its input.   It is accurate, and useful in the case where
the noise source is not well characterized, to say the function of the
buffer is to amplify the noise. 

:you seem quite hung up on definitions.  me, dunno much 'bout nuttin', just a little 'ol
;uneducated boy from new york, taught myself some of that engineering stuff by the glow of
:the tv watching taped NY Ranger games mailed to me by mom in new york when i was in that
;land of barbarians, los angeles.  so please, permit me one little 'ol definition that i can
:call my own.  when the device starts oscillating, not amplifying noise on the signal being
;fed it, IT'S OSCILLATIONG LIKE A SONOFAB*TCH. (*)

Actually you do come a cross as someone who is a little lacking in practical
experience, but otherwise quite knowlegeable.  The only definition that
you are calling your own here is the definition of a device -- does or
does not a buffer includes all the parasitics of the transistors that
implements it, and all the parasitics in the signal and power wires
connected to it.  What we are disagreeing here is the usefulness of the
definitions.

;===================================================
:
;> ;p.s.s. take your buffer, delete those parasitic things like bond wires and all, and it
:> :won't buffer anything, just lie there like a dead dog, unpowered.
;>
:> Bond wire is not parasitic.  It is an ideal bond wire plus parasitics.
;> When parasitic capacitances are deleted, they are replaced with open
:> circuit.  When parasitic inductances and resistance are deleted, they are
;> replaced with a short circuit.  Hence deleting parasitics from the
:> transistors that implemented a buffer will leave behind a functional
;> buffer with no parasitics.
:
;if you delete the parasitics from the transistors, and you delete the parasitics from the
:metal traces, and you delete the parasitics of the bond wires, and you delete parasitics
;from the package leads, and you delete the parasitics of the bypass caps, know what you
:got?  a very nice circuit.  and do you know it's operating region?  fantasy land.

Of course, that is why we take parasitics into account when going from
logical design to physical design.  Otherwise the design may only work
on paper, or fantasy land, as you call it.

Article: 13943
Subject: Immediate Opening/FPGA/Boston Area
From: briercliff@aol.com (BRIERCLIFF)
Date: 4 Jan 1999 17:29:38 GMT
Links: << >>  << T >>  << A >>
Have immediate need for BSEE with minimum of three years experience in the
areas of FLGA design, imaging systems, video standrds and analog design.
Excellent established company in the Boston area. Please e-mail resume as an
attached word doc.and information on compensation required.
Carey O'Neill
Direct line 407-869-1066
Fax line 407-869-9158   

Article: 13944
Subject: 1.5i changes
From: "Ido Kleinman" <kleinn@REMOVETHIS.mail.biu.ac.il>
Date: Mon, 4 Jan 1999 19:43:55 +0200
Links: << >>  << T >>  << A >>
I've been asked by somebody at the office what's the differences berween
Foundation 1.5 (with Service Pack) and Foundation 1.5i, and I was puzzled.

Anyone?

--

Yours,

  -- Ido Kleinman.
  kleinn@REMOVETHIS.mail.biu.ac.il
 ** Please delete the "REMOVETHIS." substring to EMail me.






Article: 13945
Subject: Re: 1.5i changes
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Mon, 04 Jan 1999 12:12:47 -0800
Links: << >>  << T >>  << A >>
Ido Kleinman wrote:
> 
> I've been asked by somebody at the office what's the differences berween
> Foundation 1.5 (with Service Pack) and Foundation 1.5i, and I was puzzled.
> 
> Anyone?

1) The 'i' indicates "Internet enabled" meaning they've added a
menu entry that starts up Internet Explorer to go to their web site.
Truly awesome. It could save me seconds per month!

2) New TBUF registers supported (according to the release notes)

3) Bug fixes, some of them documented on the Xilinx site. More recent
bug fixes refer only to the 1.5i release, so they are likely not
available for 1.5.

4) You need the 1.5i CD - no downloadable upgrade. Perhaps to encourage
people to keep their maintenance contract up to date? 

There are probably others, but I admit I found it puzzing too.


Tom Burgess
-- 
Digital Engineer
National Research Council of Canada
Herzberg Institute of Astrophysics
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3

Email:        tom.burgess@hia.nrc.ca
Office:       (250) 490-4360 
Switch Board: (250) 493-2277
Fax:          (250) 493-7767

Article: 13946
Subject: Bit-Serial Multiplier
From: John Kennedy <johnkennedy@home.com>
Date: Mon, 04 Jan 1999 20:13:57 GMT
Links: << >>  << T >>  << A >>
I need some advice on how to implement a Bit-Serial multiplier using the
Xilinx Logicore Scaled By 1/2 Accumulator.  I need to scale a 20 bit
signed 2's complement number.  I am using XC4010 fpga to try to do some
digital audio signal processing, and need a compact (ok if slow)
multiplier.  Any advice would be greatly appreciated.

John

Article: 13947
Subject: Re: 22V10 Metastability - help please
From: "Ken Coffman" <kcoffman@intermec.com>
Date: Mon, 4 Jan 1999 12:38:28 -0800
Links: << >>  << T >>  << A >>
>Bob is right, but the reason that there is no glitch, even when the
>multiplexer acts like a break-before-make switch (  it undoubtably >does,
either in one direction or the other ) is more subtle., There is >no glitch
even with break-before-make because the stray >capacitance between these
pass transistors holds the old value for >the fractional nanosecond in
question.
>
>Having answered this question many times...


What about a Xilinx HardWired device where the pass transistors are replaced
with metal? Could be ugly...


Article: 13948
Subject: Re: How to import EDIF file in Foundation Software?
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Mon, 04 Jan 1999 20:43:23 GMT
Links: << >>  << T >>  << A >>
On Mon, 04 Jan 1999 10:33:48 +0100, Le mer Michel
<michel.lemer@ago.fr> wrote:

>They understood it as they liked it (payed).

Without wishing to appear to be "FPGA manufacturer-baiting":

Perhaps you, or your purchasing people might do well to "renegotiate"
on those payment terms. Perhaps a proportional discount on the first
order of production silicon to show "good-will" over a
misunderstanding? 

Stuart
For Email remove "NOSPAM" from the address

Article: 13949
Subject: Re: 1.5i changes
From: Marc Baker <marc.baker@xilinx.com>
Date: Mon, 04 Jan 1999 12:46:57 -0800
Links: << >>  << T >>  << A >>
Xilinx has a page on the new features in 1.5i at
http://www.xilinx.com/products/software/release15i.htm

Ido Kleinman wrote:

> I've been asked by somebody at the office what's the differences berween
> Foundation 1.5 (with Service Pack) and Foundation 1.5i, and I was puzzled.
>
> Anyone?
>
> --
>
> Yours,
>
>   -- Ido Kleinman.
>   kleinn@REMOVETHIS.mail.biu.ac.il
>  ** Please delete the "REMOVETHIS." substring to EMail me.



--
Marc Baker
Xilinx Applications
(408) 879-5375




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