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I'm running some older XNF files through M1.4. They have unbonded pad definitions in them like: EXT,sig1,U,,UPAD It seems like xnf2ngd always converts them into bonded pads. For example, if I want to use 96 unbonded pads for internal FFs and 14 bonded pads in a 4010e-pc84, which has 160 pads total, 61 of them bonded, Map will bomb and tell me that I'm trying to use 110 of the 61 bonded pads. It seems like all of this worked in Xact, so there must be a way to do this in M1.4. Has anyone run into this problem ? Of course, I couldn't find anything that matches this on the Xilinx web site in the answer search. Of course, if I really get desperate, I can use the template for a chip with all of the pins bonded and tie down how I want to use them with the constraints file. For this, I'll need figure out how the pins on each package map to each other... Seems like a hack, though. See ya, -ingo -- /* Ingo Cyliax, cyliax@derivation.com, Tel/Fax: 812-333-4854/4852 */Article: 13651
The 22V10 is a 15 year old design. I would look for a more modern part, like a CPLD that performs a similar function, but might alleviate your timing constraints by being more integrated. Or, my favorite, go to an FPGA that lets you integrate many levels of 22V10s and achieve even higher systems speed. Just a friendly thought, no ulterior commercial motives. :-) Peter Alfke, Xilinx Applications Tim Forcer wrote: > Does anyone know of a manufacturer of a 22V10 with guaranteed > combinational propagation delay 5ns or better for the full INDUSTRIAL > temperature range? > > All the devices I've looked at so far are limited to COMMERCIAL > temperature range. The fastest industrial grade devices appear to be > 7.5ns (several sources). > > -- > Tim Forcer tmf@ecs.soton.ac.uk > Department of Electronics & Computer Science > The University of Southampton, UK > > The University is not responsible for my opinionsArticle: 13652
Have you got RAMS included in your TIMEGRP? For a simple design using sync RAMS I have one (schematic) timegrp with property C_GRP=FFS RAMS and one timespec TS01=PERIOD C_GRP 15. If I leave out the RAMS, delay paths involving RAMS aren't traced and the timing looks MUCH better :) By the way, according to a Xilinx M1 tutorial that someone posted the URL to a few months ago, the PERIOD constraint traces THROUGH the address pins of all RAM, TO the D/WE pins of Sync RAM, or THROUGH the D/WE of Async RAM, so it does the right thing - I was unable to find this in the official docs, but it sounds believable. Rickman wrote: > <snipped> > > I am building a FIFO with multiple banks of RAM and I am not getting > timing errors even though I find very long net delays when I check by > hand. > regards Tom Burgess -- Digital Engineer National Research Council of Canada Herzberg Institute of Astrophysics Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.ca Office: (250) 490-4360 Switch Board: (250) 493-2277 Fax: (250) 493-7767Article: 13653
Peter Alfke <peter@xilinx.com> wrote: >The 22V10 is a 15 year old design. I would look for a more modern part, >like a CPLD that performs a similar function, but might alleviate your >timing constraints by being more integrated. Or, my favorite, go to an >FPGA that lets you integrate many levels of 22V10s and achieve even >higher systems speed. >Just a friendly thought, no ulterior commercial motives. :-) Notice that an industrial 7.5ns GAL22V10C will clock at 133MHz with internal feedback while the more modern 7.5ns 9536 will only do 83MHz. Cheers Terry...Article: 13654
On Fri, 11 Dec 1998 08:26:33 GMT, z80@ds2.com (Peter) wrote: >I wonder why there appears to be *no* support for schematics? I'm not entirely sure Peter. I would surmise that "real" schematics was not supported primarily because as part of Mentor, there was no perceived requirement for another such tool to be developed by the Renoir team. Perhaps also the issues of then simulating what would be proprietary netlist, or existing Mentor stuff (Design Architect?) also came to the fore. >Otherwise, it sounds very good. How much? How many users? How long in >beta before release? Price is very much closer to ViewDraw than it is to David's estimate, but it depends what you want, what platform, and the form of licensing. Company policy precludes me... blah blah. It has been a remarkably successful product for us at Saros in the short time that we have had the product to sell officially. As a text-basher I admit that I was sceptical, but am now a convert, and do honestly find it a useful design tool. Feedback has been constructive and enthusiastic, or diametric opposition. It can be quite a considerable methodology change for existing HDL "gurus". Some have viewed it as de-skilling the role of the HDL authoring engineer. Hence their dislike. As an design entry product it is solid. Where we get the vast majority of negative comments is when evaluating customers find some piece of HDL that is perhaps a state machine, but the HDL2GRAPHICS process does not recognise as such, and turns into a flow chart, or just brings the original text into the design. The code generated by Renoir is perceived to be high quality, easy to read, and produces good results through many synthesis tools, not just Exemplar's Cheers Stuart An employee of Saros Technology, The HDL Solutions Company: Renoir Model Technology Exemplar Logic TransEDA www.saros.co.uk (I sell these products, so paint me biased)Article: 13655
On Fri, 11 Dec 1998 12:33:01 +0000, David Pashley
<David@edasource.com> wrote:
>Never much call for that with FPGAs (the subject here)! Many of the most
The analogy is the same though. Schematics helped to replace
polygon-pushing, and HDL's have almost totally replaced schematics in
the vast majority of ASIC design starts. In the same way, HDLs will
replace schematics in the FPGA market space too.
>talented and productive designers of FPGAs small and large still use
>schematics for good reasons that are frequently discussed here. I don't
>think that they are about to trash Viewdraw and go to synthesis only
>when they can have the best of both worlds. Neither are they going to
>use Renoir ($20k? $30k?) to do block diagrams and schematics instead of
Oh David, if you think that is what it is worth, then can I be on your
Christmas list, please?
<snip>
>Let me see. It's a very expensive tool, only affordable to high-end ASIC
>designers, that takes block diagrams and graphical state machines and so
>on and turns them into thousands of lines of nasty machine-generated
>VHDL ;-)
I assume that is a tongue-in-cheek comment? Season of goodwill and all
that. Otherwise you are wrong, wrong, part right, and wrong. :-)
Just for fun though, below is some "nasty machine-generated" VHDL code
from a hierarchical graphical state machine.
<snip>
>The whole design is then presented to FPGA Express for synthesis, which
>accepts both VHDL/Verilog and EDIF blocks from Viewdraw within a single
>design. The whole process is managed by Intelliflow.
That is interesting. Does FPGA Express cross-border optimise the EDIF
blocks? Can you prevent it from doing so? Can it manipulate, create,
and destroy the hierarchy for optimum synthesis, or does it just
flatten the whole thing? Does it support VHDL and Verilog at the same
time, with one language instantiating the other etc?
>I would say, in conclusion, that many of your comments are more
>appropriate to ASIC design than FPGA.
The differences between large FPGAs and small ASICs are rapidly
diminishing. Perhaps it's just that we each address a different market
space of FPGA designer requirements. Very few of my customers using
Renoir are doing ASIC, but many are doing what would be considered
small & medium size FPGAs. Some are also doing 10K130's, 3T125's and
the take up and interest in Virtex hes been remarkable.
Cheers
Stuart
--
An employee of Saros Technology, The HDL Solutions Company:
Renoir
Model Technology
Exemplar Logic
TransEDA
www.saros.co.uk
(I sell these products, so paint me biased)
--
-- VHDL Entity UART.control_operation.symbol
--
-- Created:
-- by - Stuart.UNKNOWN (IDTZRGSK)
-- at - 21:11:58 11/12/98
--
-- Generated by Mentor Graphics' Renoir(TM) 98.4 (Build 5)
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY control_operation IS
PORT(
clk : in std_logic ;
clr_int_en : in std_logic ;
cs : in std_logic ;
nRW : in std_logic ;
rst : in std_logic ;
xmitdt_en : in std_logic ;
clear_flags : out std_logic ;
enable_write : out std_logic ;
start_xmit : out std_logic
);
-- Declarations
END control_operation ;
--
-- VHDL Architecture UART.control_operation.fsm
--
-- Created:
-- by - Stuart.UNKNOWN (IDTZRGSK)
-- at - 21:11:58 11/12/98
--
-- Generated by Mentor Graphics' Renoir(TM) 98.4 (Build 5)
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE fsm OF control_operation IS
-- Architecture Declarations
TYPE state_type IS (
waiting,
xmitting,
writing_to_reg,
clearing_flags,
reading_from_reg
);
-- State vector declaration
ATTRIBUTE state_vector : string;
ATTRIBUTE state_vector OF fsm : architecture IS "current_state" ;
-- Declare current and next state signals
SIGNAL current_state, next_state : state_type ;
BEGIN
----------------------------------------------------------------------------
clocked : PROCESS (
clk,
rst
)
----------------------------------------------------------------------------
BEGIN
IF (rst = '0') THEN
current_state <= waiting;
-- Reset Values
ELSIF (clk'EVENT AND clk = '1') THEN
current_state <= next_state;
-- Default Assignment To Internals
END IF;
END PROCESS clocked;
----------------------------------------------------------------------------
nextstate : PROCESS (
clr_int_en,
cs,
current_state,
nRW,
xmitdt_en
)
----------------------------------------------------------------------------
BEGIN
CASE current_state IS
WHEN waiting =>
IF (nRW='1' AND cs='0') THEN
next_state <= writing_to_reg;
ELSIF (nRW='0' AND cs='0') THEN
-- I can attach comments to
-- Transitions too
next_state <= reading_from_reg;
ELSE
next_state <= waiting;
END IF;
-- Here's a comment I attached to
-- the xmitting state in the graphics
WHEN xmitting =>
IF (cs = '1') THEN
next_state <= waiting;
ELSE
next_state <= xmitting;
END IF;
WHEN writing_to_reg =>
IF (cs = '1') THEN
next_state <= waiting;
ELSIF (nRW='1' AND xmitdt_en='1') THEN
next_state <= xmitting;
ELSE
next_state <= writing_to_reg;
END IF;
WHEN clearing_flags =>
IF (cs = '1') THEN
next_state <= waiting;
ELSE
next_state <= clearing_flags;
END IF;
WHEN reading_from_reg =>
IF (cs = '1') THEN
next_state <= waiting;
ELSIF (nRW='0' AND clr_int_en='1') THEN
next_state <= clearing_flags;
ELSE
next_state <= reading_from_reg;
END IF;
WHEN OTHERS =>
next_state <= waiting;
END CASE;
END PROCESS nextstate;
----------------------------------------------------------------------------
output : PROCESS (
current_state
)
----------------------------------------------------------------------------
BEGIN
-- Default Assignment
clear_flags <= '0';
enable_write <= '0';
start_xmit <= '0';
-- Default Assignment To Internals
-- State Actions
CASE current_state IS
-- Here's a comment I attached to
-- the xmitting state in the graphics
WHEN xmitting =>
start_xmit <= '1';
WHEN writing_to_reg =>
enable_write <= '1';
WHEN clearing_flags =>
clear_flags<='1';
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output;
-- Concurrent Statements
END fsm;
Article: 13656On Fri, 11 Dec 1998 09:24:56 -0500, Ray Andraka <no_spam_randraka@ids.net> wrote: >Stuart, >can you create relatively placed macros with this tool flow, or are you >forced to put placement info in the flat constraints file (either by hand or >through attributes in the VHDL)? The problem with instantiating components >like the CY4 is that you NEED to put RLOCs on it for the PAR tool to be able >to use them...they need to be placed in specific locations relative to one >another. So far, the HDL tools I've looked at don't make this easy. Yes Ray, you can. You need to declare the attribute, and then attach it to the component instantiation, and this will then be passed through as regular RLOC and HU_SET attributes on the components. I guess this is a property you set on schematic parts, so the process is probably similar? I've also used it for cliquing system blocks for Altera 10K parts. Quite useful as that goes through in the EDIF to MP2. If you don't want to bother with HU_SETs (required for a flat netlist), synthesising and preserving the hierarchy takes the pain away. Useful with multiple instantiations of a single component. It's almost certainly not as pretty as schematics if you do a LOT of instantiation, because you don't get nice pretty gate symbols, just rectangular boxes with ports. It does enable designers to do gate level stuff when they really have to. Regards Stuart An employee of Saros Technology, The HDL Solutions Company: Renoir Model Technology Exemplar Logic TransEDA www.saros.co.uk (I sell these products, so paint me biased)Article: 13657
Andrew Plumb wrote: > Anyone know where I can get 5 or 6 of Xilinx' newer Virtex XVC300 (or > '400, '600, '800, or '1000) chips? Even one or two will do. > > Any help is GREATLY appreciated! (no one seems to have any...) > The proper way to order and buy chips is to contact the local Xilinx sales office ( In this particular case in Dallas, call 972 960 1043, or the local Xilinx representative ( Bonser-Philower Sales in Austin, Houston or Richardson, Texas). As has been mentioned before in this group, it is good etiquette to state the name of your employer, unless the posting is just a personal opinion. Peter Alfke, XilinxArticle: 13658
sorry to get in so late, but i couldn't let this pass without comment: On Tue, 8 Dec 1998 10:00:03 +0000, David Pashley <David@edasource.com> wrote: >In the "olden days" of digital design, we used to talk about >hierarchichal and top-down design (now called "re-use"). At the bottom >level of these designs would be gate-level schematics, very efficiently >designed with the target architecture in mind. Because we would put the >bottom-level modules in a library and re-use them either directly, or >modified, the trick was to make them as fast and small as possible. 'modern' design is exactly the same. you can't re-invent the wheel every time you start a new ASIC or FPGA. you can do everything you mentioned in VHDL; you don't need a schematic tool. the lowest level of abstraction in VHDL is a 'structural' description, which is exactly equivalent to drawing a schematic - you join up library modules with signals, and this is translated directly into a netlist. >Hand drawn schematics are often many times more efficient than what a >synthesis tool can produce. i've seen this said several times in this newsgroup, but i've never seen an example. in short, it's not true, unless your synthesiser is brain-damaged. if your synthesiser is producing bad code, then it's almost certainly because (a) you don't understand your technology, or (b) because you don't know how to write RTL VHDL. rubbish in, rubbish out. and, a couple of other points: (a) take a look at your synthesiser's netlist output. you'll see that it includes modules which are heavily optimised for xilinx - the synthesiser understands the contents of a CLB, and how to place CLBs (if it doesn't, get another synthesiser). (b) if you don't like what your synthesiser has produced, and you think you can do it better (maybe it didn't get that state machine quite right?... or maybe i can do a better job of reducing that combinatorial function of 10 variables?), then you can simply do it yourself, and code a structural description. this is, after all, exactly what you're doing with your schematic tool. >Of course you can't start out on a 200,000k >gate design with just a schematic editor. But a mixed approach, with >highly efficient, schematic-drawn reusable elements alongside >synthesized modules at the bottom level, and perhaps with a block >schematic at the top does make sense. And this approach is more widely >used than you may think. as i said, you don't need a schematic editor to produce your hand-coded lower-level blocks. and, as stuart says, renoir does a good job at the top level (although i personally am quite happy with a pencil and paper for my top level block diagrams). >5 years ago, if, as an EE, you knew VHDL, then you were a prized >specimen. If I'm right, before long, designers who can work at the gate >level and drive schematic editors will be the rare and sought-after >commodity. > >The portability and productivity of HDL-based design are of undoubted >benefit, but there is no reason to abandon the performance advantages of >designing with schematics, while we can do both together. Given the >right tools, of course. ;-) i don't know of any performance advantages to using schematics, but i'd be grateful to hear from anyone who does know of any. i've got some example VHDL code for creating slices, and RLOC'ing them, which i'll try to post today or tomorrow. evan ps. it's a little unfair to call peter anonymous - he's been posting here a long time, and you can find his email address if you look hard enough. what's the point of giving your company name if you're not trying to sell anything?Article: 13659
On 12 Dec 1998 22:12:16 GMT, "Khaled Benkrid" <k.benkrid@qub.ac.uk> wrote: >Does any body knows the EDIF routing property for the 4000 series? >Where aould I get this information? what's a 'routing' property? what are you trying to do? evanArticle: 13660
I don't consider Foundation tools to be usable. What is your desired design entry method? Foundation might be okay for schematics, I wouldn't know because I've never used a schematic to design an FPGA. The combination of Synplicity Synplify or Exemplar Leonardo for Verilog or VHDL design with the Xilinx Design Manager for place and route works very well. Altera has simple silicon, so their software is correspondingly simple and easy, and works very well. If you're looking for all-in-one vendor software that works well, MAXPLUS2 is great. For silicon I'd say Altera works well for datapath type functions (filters and other pipelined functions) and Xilinx works well for more random and mixed logic. If you need to lock down your pins and create a circuit board before the FPGA design is done, then you don't want to use Altera. glenn kubota wrote in message <364E13BF.5C4EB701@earthlink.net>... >i've got a project where i'm looking at using CPLDs from either Altera >or Xilinx. it looks like they both have chips that will fit the bill. >my question, however, is what're the relative pros and cons of Xilinx >Foundation vs. Altera Max Plus? what's easier to learn? what will serve >me better in the future? > >thanks, >glenn k. > >Article: 13661
Terry Harris wrote: > Notice that an industrial 7.5ns GAL22V10C will clock at 133MHz with > internal feedback while the more modern 7.5ns 9536 will only do 83MHz. > > Cheers Terry... There can be no argument that a small design can often beat a more complex design on raw clock speed. But I was addressing a different issue: The original question was for a specific delay, say 5 ns, and I think that the need for this pin-to-pin delay might just have been dictated by the simplicity ( lack of logic levels ) of the 22V10 architecture. A larger, more complex chip might be able to get the total job done faster, even though it might have a longer pin-to-pin delay. I ask our customers routinely: "Please don't tell me this microscopic part of your design problem, but rather tell me what you really need to get done. Maybe a parallel approach gives you much higher speed ( maybe not...) If you stay on the chip, you can go through several logic levels in one look-up table in less than 2 ns, etc..." Performance is not just pin-to-pin delay. Peter Alfke, Xilinx ApplicationsArticle: 13662
Tim wrote > >Does anyone know of a manufacturer of a 22V10 with guaranteed >combinational propagation delay 5ns or better for the full INDUSTRIAL >temperature range? > Tim- Lattice makes GAL22V10s with 4ns speed in commercial grade, but we don't offer industrial grade at that speed. Why? Industrial ratings require both thermal and operating voltage ranges that make it difficult to guarantee the speed. I would suggest talking to the local Lattice guys about possibly getting the factory to work on an 'ASPEC' device for you, if you're willing to work with tighter voltage swings they may be able to help. The ISPGAL22LV10 is available in 3.3v at 4ns, so power and thermals can be better controlled in your design. The most critical part of our specs is the thermal limit for the die, which takes into account operationg frequency, temperature and design utilization. Good luck in your pursuit of the GAL, I won't attempt to sway you with our 3.5ns ISPLSI2032E or 4ns ISPLSI2032VE. :) Mike Thomas Lattice FAE New YorkArticle: 13663
Peter Alfke <peter@xilinx.com> wrote: >Terry Harris wrote: > >> Notice that an industrial 7.5ns GAL22V10C will clock at 133MHz with >> internal feedback while the more modern 7.5ns 9536 will only do 83MHz. >> >> Cheers Terry... >There can be no argument that a small design can often beat a more >complex design on raw clock speed. >But I was addressing a different issue: Guess we are both guessing at what the original poster really needs. Having been in possibly a similar situatuion (about 18 months ago) I was making the point at slightly glib answers about using some newer bigger part may not be the solution. It wasn't for me then - 2 x GAL22V10Cs was the messy (should be one chip, and isp, and 3v3 would have been better) but only solution I found. Are there any 95xx industrial parts which will run a state machine at 80MHz? (without restricting he fit to local feedback?). Cheers Terry...Article: 13664
Peter Alfke wrote: [deletia] > The proper way to order and buy chips is to contact the local Xilinx > sales office ( In this particular case in Dallas, call 972 960 1043, or > the local Xilinx representative ( Bonser-Philower Sales in Austin, > Houston or Richardson, Texas). [deletia] Hi Peter, Alas, local channels here in Ottawa (Ontario) don't seem to have any in stock, hence the "unproper" approach. Since you recommend I check with the folks in Texas, I'll do so. (I use my io.com account for news stuff because of their sp*m countermeasures) As for employer ID, it's bounty hunting. ;-) Thanks! Andrew, VE3SLG E-mail: tekmage@io.comArticle: 13665
Peter Alfke <peter@xilinx.com> writes:
> The original question was for a specific delay, say 5 ns, and I think
> that the need for this pin-to-pin delay might just have been dictated by
> the simplicity ( lack of logic levels ) of the 22V10 architecture. A
> larger, more complex chip might be able to get the total job done
> faster, even though it might have a longer pin-to-pin delay.
Sure, but often you need fast parts to fix some silly quirks in say a
memory interface. For instance, being able to AND all the byte select
with another signal. A couple of gates like this, and you'll save
board space with a small PLD. And then there's the small thing about
working 0ns after power-on... (reset logic)
Yes, we are also using virtex, don't worry Peter.
Homann
--
Magnus Homann Email: d0asta@dtek.chalmers.se
URL : http://www.dtek.chalmers.se/DCIG/d0asta.html
The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 13666I'm having serious trouble with a constrained clock IOB placement on a XC4010e device. I'm using Synopsys FPGA compiler and Xilinx M1.4. My design needs two different clocks, and they have to be set to two specific IOB pin. I've been trying various method, but none of them works ... I get an error message during the mapping phase. I first tried the set_attribute command within the VHDL synthesis script file : set_attribute clock1 "pad_location" -type string "P4" set_attribute clock2 "pad_location" -type string "P162" Then, I tried to set some constraints in the UCF file for the xilinx M1.4 tools with the follwoing lines NET clock1 LOC=p4; NET clock1 LOC=p162; In both cases, the mapping process fails with the following error message : ERROR:x4kma:82 - Illegal site name used for clock placement: P4. Please consult the "Attributes, Constraints, and Carry Logic" section of the Libraries Guide for information on legal clock placement constraints. ERROR:x4kma:83 - A direct access (dedicated) pad or associated input buffer must be LOC-constrained with a legal pin name. ERROR:x4kma:81 - Primary clock buffer BUFGS symbol "U160" (output signal=n145) has a site name problem. The site name associated with this clock buffer is probably illegal. Please consult the "Attributes, Constraints, and Carry Logic" section of the Libraries Guide for more information. I double checked the XC4010E documentation, however it says that both P4 and P162 pins are "Primary Global Input", which are supposed to be pin dedicated for clocks or other global signals. Any help would be greatly appreciated ... Steven Derrien PHD Student IRISA, FranceArticle: 13667
I looking into loading an Altera EPC2 with configuration data for a Xilinx XC40xx. Does anyone know if this is possible? I'm interested in the ISP capability of Altera's EPC2 using the JTAG bus, but I'm using Xilinx XC40xx devices. I need the ability to reload the configuration EPROM using only the JTAG port. Thanks, Carl Poirier Eastman Kodak Electronic Products Design for TestabilityArticle: 13668
You must insert global clock buffers when you want to use the dedicated clock pins. In fpga_compiler this can be done with the commands set_pad_type -clock clock1 set_pad_type -exact BUFGP_F clock1 before executing the insert_pads command. Usually fpga_compiler determines where to insert clock buffers. This can cause some problems, too. You can the compiler from inserting unwanted buffers by using the command set_pad_type -no_clock <signal_name> I hope this helps. ReneArticle: 13669
Terry Harris wrote in message <36795df2.9923508@news.dial.pipex.com>... >Are there any 95xx industrial parts which will run a state machine at >80MHz? (without restricting he fit to local feedback?). Check out the 95xxXL parts. They've fixed the feedback delay problem. I'm specifying a 9536XL-7 and its faster than a 9536-5! Steve PS: They're estimating sample parts at year end.Article: 13670
Carl Have you any availability info from Altera about the EPC2 ? Samples or production ? They were supposed to be available in October, but I've not seen any yet. I heard there were some production problems... Without _FIRM_ information from Altera I'd be very careful. (Remember the 6502 microprocessor core that never quite made it into Maxplus ? Look in the AHDL manual November 1995 page 130. I'm still waiting.) CPoirier@Kodak.com "Carl R. Poirier" writes: > I looking into loading an Altera EPC2 with configuration data for a Xilinx > XC40xx. Does anyone know if this is possible? > > I'm interested in the ISP capability of Altera's EPC2 using the JTAG bus, > but I'm using Xilinx XC40xx devices. I need the ability to reload the > configuration EPROM using only the JTAG port. > -- Steve Dewey Steve@s-deweynospam.demon.co.uk Too boring to have an interesting or witty .sig file.Article: 13671
Hi, Can anyone please tell me where can I get the specs of 3-wire serial bus. Thanks, vikas -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13672
Would it be practical to implement an MP3 decoder in an FPGA? SteveArticle: 13673
In article <367438F8.215F1CAF@Bjerre-Technology.dk>, Bo Bjerre <Bo@Bjerre-Technology.dk> wrote: >saffary wrote: >> >> Somone know where i can find this cable. >> >> Thanks. >- > >--read the JTAG programmers manual that comes with the M1.5 software, >There is a schematic, telling what to do.. Also, check out http://www.xilinx.com/support/programr/cables.htm there is a link to local representative and distributors. You may also want to take a look at http://www.xilinx.com/isp/isp.htm for answers to your other xilinx related in system programming questions. Matt -- //\/\ Matt Murphy matthew.murphy@xilinx.com \\ / XILINX Main: 408-559-7778 // \ 2100 Logic Drive Direct: 408-879-4666 \\/\/ San Jose, CA 95124 FAX: 408-879-5171Article: 13674
>>Hand drawn schematics are often many times more efficient than what a >>synthesis tool can produce. > >i've seen this said several times in this newsgroup, but i've never >seen an example. in short, it's not true, unless your synthesiser is >brain-damaged. if your synthesiser is producing bad code, then it's >almost certainly because (a) you don't understand your technology, or >(b) because you don't know how to write RTL VHDL. rubbish in, rubbish >out. This is certainly true, but few people jumping into VHDL seem to realise it. I messed with VHDL only a little, but I realised within minutes of starting on a course that this is a language where you really need to understand what types of hardware gets generated by what HDL constructs, and the relationship is often subtle. OTOH schematics are entirely obvious :) As always, you need to be an expert with the tools you use if you want to do good stuff. No way around that. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.
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