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Messages from 15725

Article: 15725
Subject: Re: FPGA testing board
From: msimon@tefbbs.com (M.Simon)
Date: Sat, 10 Apr 1999 07:34:58 GMT
Links: << >>  << T >>  << A >>
Check out my URL.


Simon - http://www.tefbbs.com/spacetime/index.html
Article: 15726
Subject: simulator
From: wathelet <wathelet@spitfire.com.au>
Date: Sat, 10 Apr 1999 20:11:15 +1000
Links: << >>  << T >>  << A >>
hi,

I'm getting interested in FPGA, particularly evolvable type. Is there a
software package that can simulate an FPGA that I could use to do
experiments on, instead of bying the hardware and connecting it to a PC
(which is all I've got).

R. Wathelet


Article: 15727
Subject: FPGA vs CPLD? Any Experts out there?
From: "Gary Desrosiers" <desrosi@pcnet.com>
Date: Sat, 10 Apr 1999 14:24:22 -0400
Links: << >>  << T >>  << A >>
Sure, you can implement a microcontroller design in a FPGA but can you do
the same with CPLDs? Are there any examples?

Also, are all uC's done in VHDL or has anyone done this with ABEL?


Article: 15728
Subject: Consulting Engineers Wanted
From: "Margaret Dailey" <margaret@cyberhighway.net>
Date: Sat, 10 Apr 1999 12:53:50 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

------=_NextPart_000_0018_01BE8351.2E24B5E0
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

The Portland, Oregon office of Oxford Global Resources has long-term =
contract positions for IC designers, and engineers and designers =
proficient with simulation and synthesis tools.  We have openings for =
mid-level designers to project team leaders and managers.  We offer our =
contractors excellent compensation and some of the best benefits in the =
business.

Don't know about the Northwest?   The quality of living is topnotch, and =
there's plenty to do here besides work for some of the country's leading =
high-tech firms.  Take a look at http://www.pova.com.

Respond here, or email margaret_dailey@oxfordcorp.com.  Principals only, =
please.








------=_NextPart_000_0018_01BE8351.2E24B5E0
Content-Type: text/html;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN">
<HTML>
<HEAD>

<META content=3Dtext/html;charset=3Diso-8859-1 =
http-equiv=3DContent-Type>
<META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR>
</HEAD>
<BODY>
<DIV>The Portland, Oregon office of Oxford Global Resources has =
long-term=20
contract positions for IC designers, and engineers and designers =
proficient with=20
simulation and synthesis tools.&nbsp; We have openings for mid-level =
designers=20
to project team leaders and managers.&nbsp; We offer our contractors =
excellent=20
compensation and some of the best benefits in the business.</DIV>
<DIV>&nbsp;</DIV>
<DIV>Don't know about the Northwest?&nbsp;&nbsp; The quality of living =
is=20
topnotch, and there's plenty to do here besides work for some of the =
country's=20
leading high-tech firms.&nbsp; Take a look at <A=20
href=3D"http://www.pova.com">http://www.pova.com.</A></DIV>
<DIV>&nbsp;</DIV>
<DIV>Respond here, or email <A=20
href=3D"mailto:margaret_dailey@oxfordcorp.com">margaret_dailey@oxfordcorp=
.com</A>.&nbsp;=20
Principals only, please.</DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV></BODY></HTML>

------=_NextPart_000_0018_01BE8351.2E24B5E0--

Article: 15729
Subject: Re: FPGA vs CPLD? Any Experts out there?
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Sat, 10 Apr 1999 14:26:10 -0700
Links: << >>  << T >>  << A >>
Gary Desrosiers wrote in message ...
>Sure, you can implement a microcontroller design in a FPGA but can you do
>the same with CPLDs? Are there any examples?
>
>Also, are all uC's done in VHDL or has anyone done this with ABEL?

The control logic of the GNOME CPU from Dave van den Bout's The Practical
Xilinx Designer Lab Book is written in ABEL.  It targets the XC4005XL FPGA
or XC95108 CPLD.

Also, I've done control units in schematics and my netlist generator, when
floorplanning matters.

Jan Gray



Article: 15730
Subject: Re: FPGA vs CPLD? Any Experts out there?
From: "Gary Desrosiers" <desrosi@pcnet.com>
Date: Sat, 10 Apr 1999 18:38:56 -0400
Links: << >>  << T >>  << A >>
Jan,

Thank you very much. I ordered the Xilinx book.  Didn't even realize it
existed. Thank you. Amazingly, it's the XC95108's that I'm working on right
now.

I also checked out your web site. Obviously, your an expert in the uC arena.
Have you ever thought of elaborating on the PPT presentation that's on your
site and giving us beginners a tutorial on uC design?

Gary
----
Jan Gray wrote in message <7eoejo$5gp$1@news-1.news.gte.net>...
>Gary Desrosiers wrote in message ...
>>Sure, you can implement a microcontroller design in a FPGA but can you do
>>the same with CPLDs? Are there any examples?
>>
>>Also, are all uC's done in VHDL or has anyone done this with ABEL?
>
>The control logic of the GNOME CPU from Dave van den Bout's The Practical
>Xilinx Designer Lab Book is written in ABEL.  It targets the XC4005XL FPGA
>or XC95108 CPLD.
>
>Also, I've done control units in schematics and my netlist generator, when
>floorplanning matters.
>
>Jan Gray
>
>
>


Article: 15731
Subject: fpga express stripping out Viewlogic busses
From: "william pawlowski" <bill-jeanne-pawlowski@worldnet.att.net>
Date: 11 Apr 1999 01:33:45 GMT
Links: << >>  << T >>  << A >>
Has anyone ever seen the when in a viewlogic schematic with a bus labeled

		DATA[27:00]

that FPGA Express strips out bits 09 through 00 and all componets?

Bill 
Article: 15732
Subject: Re: FPGAs with ECL-compatible I/Os
From: Tim Davis <timdavis@tdcon.com>
Date: Sat, 10 Apr 1999 19:34:21 -0600
Links: << >>  << T >>  << A >>

--------------977E65411A4A7623F5EE3D1E
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I'm doing an FPGA fibre channel implementation right now. We will probably use the Vitesse 7126 for
SERDES. It accepts a 1.0625 Gb/s data stream and spits out 20 bit words at ~53 Mhz -- not 10 bit
words. The vitesse part has two clock outputs 180 degrees apart. There are 10 bit wide SERDES out
there operating at your 100+ Mhz rate if you look around. I think Triquint may have a few parts as
well.

Some FC manufacturer's implement a  GLM (gigabit link module) which implemented the entire FC-0 plus
some of FC-1 in one module. They come in either 10-bit or 20-bit interfaces so perhaps the
serializers (that ultimately got put in the module) were designed to fit either type interface -
hence the availability of different SERDES components.

At any rate, I'm glad the vitesse part accepts and emits 20-bit words at 53 Mhz because it would be
less fun to work at >100 Mhz with FPGA technology.

>
> Joel Kolstad wrote:
>
> > Speaking of high speed serializer/deserializer interfacing to FPGAs...
> >
> > Can somebody tell me what the Fibre Channel folks were thinking when they
> > came up with the standard that said that all these little PQFP-64 gigabit
> > serializer/deserializer chips (e.g., AMCC S2070 and the bazillion clones
> > thereof) should have 2 ~50MHz clock outputs (with 10 bit encoded parallel
> > outputs) instead of 1 ~100MHz clock output?  Given that the same 8B/10B
> > encoding is used with gigabit Ethernet, all the SerDes vendors optimized
> > their chips for it's 125MHz clock rate and kept the same interface to boot.
> > Grrrr...
> >
> > We're going through some effort at the moment to get back to one 100MHz byte
> > stream.  Since the transmitter side of the SerDes chips want 1 100MHz clock
> > with a bytewide input, my only guess is that the Fibre Channel guys thought
> > you'd design something along the lines of:
> >
> > -- 50MHz dual (parallel) 8B/10B encode of 16 bit data followed by  a simple
> > mux running at 100MHz.  Since the encoding consumes a significant amount of
> > logic, presumably it was hard at some point to build a 100MHz encoder but
> > not so hard to build a 100MHz mux.
> > -- 50MHz dual 10B/8B decode, and we're just going to assume your system
> > interface is 16 or 32 bits wide anyway so there's no need to get a 100MHz
> > clock back.
> >
> > The deserializers go to some effort to guarantee that commas show up on a
> > particular clock phase, so I'm tempted to think my guess here is a good one.
> >
> > ---Joel Kolstad
>

--

Tim Davis
Timothy Davis Consulting

TimDavis@TDCon.com - +1 (303) 426-0800 - Fax +1 (303) 426-1023


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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
I'm doing an FPGA fibre channel implementation right now. We will probably
use the Vitesse 7126 for SERDES. It accepts a 1.0625 Gb/s data stream and
spits out 20 bit words at ~53 Mhz -- not 10 bit words. The vitesse part
has two clock outputs 180 degrees apart. There are 10 bit wide SERDES out
there operating at your 100+ Mhz rate if you look around. I think Triquint
may have a few parts as well.
<p>Some FC manufacturer's implement a&nbsp; GLM (gigabit link module) which
implemented the entire FC-0 plus some of FC-1 in one module. They come
in either 10-bit or 20-bit interfaces so perhaps the serializers (that
ultimately got put in the module) were designed to fit either type interface
- hence the availability of different SERDES components.
<p>At any rate, I'm glad the vitesse part accepts and emits 20-bit words
at 53 Mhz because it would be less fun to work at >100 Mhz with FPGA technology.
<blockquote TYPE=CITE>&nbsp;
<br>Joel Kolstad wrote:
<p>> Speaking of high speed serializer/deserializer interfacing to FPGAs...
<br>>
<br>> Can somebody tell me what the Fibre Channel folks were thinking when
they
<br>> came up with the standard that said that all these little PQFP-64
gigabit
<br>> serializer/deserializer chips (e.g., AMCC S2070 and the bazillion
clones
<br>> thereof) should have 2 ~50MHz clock outputs (with 10 bit encoded
parallel
<br>> outputs) instead of 1 ~100MHz clock output?&nbsp; Given that the
same 8B/10B
<br>> encoding is used with gigabit Ethernet, all the SerDes vendors optimized
<br>> their chips for it's 125MHz clock rate and kept the same interface
to boot.
<br>> Grrrr...
<br>>
<br>> We're going through some effort at the moment to get back to one
100MHz byte
<br>> stream.&nbsp; Since the transmitter side of the SerDes chips want
1 100MHz clock
<br>> with a bytewide input, my only guess is that the Fibre Channel guys
thought
<br>> you'd design something along the lines of:
<br>>
<br>> -- 50MHz dual (parallel) 8B/10B encode of 16 bit data followed by&nbsp;
a simple
<br>> mux running at 100MHz.&nbsp; Since the encoding consumes a significant
amount of
<br>> logic, presumably it was hard at some point to build a 100MHz encoder
but
<br>> not so hard to build a 100MHz mux.
<br>> -- 50MHz dual 10B/8B decode, and we're just going to assume your
system
<br>> interface is 16 or 32 bits wide anyway so there's no need to get
a 100MHz
<br>> clock back.
<br>>
<br>> The deserializers go to some effort to guarantee that commas show
up on a
<br>> particular clock phase, so I'm tempted to think my guess here is
a good one.
<br>>
<br>> ---Joel Kolstad
<br><a href="http://users.ids.net/~randraka"></a>&nbsp;</blockquote>
--
<p>Tim Davis
<br>Timothy Davis Consulting
<p>TimDavis@TDCon.com - +1 (303) 426-0800 - Fax +1 (303) 426-1023
<br>&nbsp;</html>

--------------977E65411A4A7623F5EE3D1E--

Article: 15733
Subject: Re: viterbi/trellis decoder
From: Tim Davis <timdavis@tdcon.com>
Date: Sat, 10 Apr 1999 19:54:41 -0600
Links: << >>  << T >>  << A >>
You should get the book, "Error Coding Cookbook" by C. Britton Rorabaugh (ISBN 0-07-911720-1 approx
$55). It comes with a floppy containing C code for numerous ECC implementations including Viterbi
Decoding.

Since everybody says that C and Verilog are virtually identical you should be able to simply copy
the C into a Verilog module shell and be happy as a clam.

Asif Chowdhury wrote:

> Hi, I'm trying to write some verilog code for a veterbi decoder (Trellis
> decoder) using 256-QAM which to be implemented on FPGA.  It is my 4th
> year Electrical Engineering project.
>
> Is there anyone who has done any work on viterbi/trellis using verilog?
> Please e-mail me ASAP.
>
> Thanks.
> AC

--

Tim Davis
Timothy Davis Consulting

TimDavis@TDCon.com - +1 (303) 426-0800 - Fax +1 (303) 426-1023


Article: 15734
Subject: Free FPGA-HDL Newsletter Release
From: APS <resp@associatedpro.com>
Date: Sat, 10 Apr 1999 23:25:31 -0400
Links: << >>  << T >>  << A >>
The next release of the APS EDA newsletter will soon be released:

The Newsletter will have articles on the following topics:

* PN Sequence Core in XILINX FPGAs

* A rework of a schematic based FIFO in VHDL with C control and
verification code.

* Network Capable FPGA Board.

* Uart core and RS-232 drivers on the APS-X240


Product Focus:

* Essential VHDL book now available with X240 examples
* Prism HDL editor now available

Special Focus on:

ST-111 QPSK Direct Sequence Spread Spectrum Signal Generator from SIGTEK

* Also a look at the X208 Bit Generator Application Core
* VHDL Topic:  two's compliment numbers in VHDL

To subscribe to the newsletter for free just send a reply with the work
SUBSCRIBE in the subject header.

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 15735
Subject: Anyone Use SpeedWave? Help with Simulation Problem
From: "Adam J. Elbirt" <aelbirt@nac.net>
Date: Sat, 10 Apr 1999 23:48:12 -0400
Links: << >>  << T >>  << A >>
Anyone out there a SpeedWave user for VHDL Simulation?  I have a
structural netlist output from FPGA Express for a design I synthesized
into a Xilinx Virtex chip.  I analyzed the VHDL in SpeedWave but when I
go to load the design my top level entity isn't available for me to
choose.  When I examine the VHDL the entity is there.  I have waited 5
days now and Viewlogic tech support can't get the thing to analyze let
alone verify the problem and propose a potential solution (big shock).
Any help would be appreciated.

Adam

Article: 15736
Subject: Re: Does any one want to talk about Dynamic Configuration?
From: "Ahmad Alsolaim" <alsolaim@ieee.org>
Date: Sun, 11 Apr 1999 01:32:03 -0400
Links: << >>  << T >>  << A >>

Jamil Khatib <khatib@ieee.org> wrote in message
news:370E5F48.9B0A3BA@ieee.org...
> Bourguiba Riad wrote:
> >
> > Does any one want to talk about Dynamic Configuration?
> >
> > Here is my ICQ # : 33301195
> >
> > Contact me.
> >
> > Riad Bourguiba
>
> Yes I am very intrested in this topic but I prefer the Email I do not
> like the ICQ

I also would like to talk about this subject.

Ahmad Alsolaim
alsolaim@ieee.org


Article: 15737
Subject: Re: Application Consulting Engineer (ACE)
From: Andre Powell <Andre@firkle.demon.co.uk>
Date: Sun, 11 Apr 1999 11:06:55 +0100
Links: << >>  << T >>  << A >>
In article <37086F56.A96CC87B@cadworx.com>, Jayant Nagda
<jayant@cadworx.com> writes
>
>Les,
>
> We have provided similar services as consultats to other EDA
> companies, and will be intersted to discuss consulting
> opportunities.  
>
> Our brief profile is attached. 
>
>
>Jayant Nagda
>CADWorx.
>
>
>Les Donaldson wrote:
>> 
>> Small, high-quality, up-and-coming Santa Clara based
>> EDA startup seeks a talented Design Engineer for its
>> application services group.
>> 
>> If you have all or some of the following experience:
>> 
>> - IC design using Verilog and/or VHDL
>> - Synthesis (Synopsys, Ambit, FPGA synthesizers)
>> - Simulation (popular Verilog and VHDL simulators)
>> - Excellent comunication skills
>> - Self-starter, self-thinker, motivated and entrepenurial
>> 
>> ....we would like to talk to you.  Principals only please.
>> 
>> Our software is ported on PC-Windows and Unix.
>> 
>> Excellent compensation and stock options.
>> 
>>   ------- >>>>   (408) 654-1651  <<<<------
>[ A MIME application / msword part was included here. ]
>

Hi Jayant,
Do you mind NOT sending your companies brochure with your replies, there
are many people who use their own telephone lines and not their
companies to read this group.
-- 
Andre Powell
Article: 15738
Subject: Re: Does any one want to talk about Dynamic Configuration?
From: "J. Khatib" <khatib@ieee.org>
Date: Sun, 11 Apr 1999 16:06:13 +0300
Links: << >>  << T >>  << A >>
OK
It seems that there are some people want to talk about it.
What do you want to talk about?


Bourguiba Riad wrote:
> 
> Does any one want to talk about Dynamic Configuration?
> 
> Here is my ICQ # : 33301195
> 
> Contact me.
> 
> Riad Bourguiba
Article: 15739
Subject: Lattice
From: (NO-SPAM)md7114@mclink.it (damiano)
Date: 11 Apr 1999 15:09:06 GMT
Links: << >>  << T >>  << A >>
Hi all,
What do you think about lattice?



Damiano Rullo
Trezzano S/N
Milan, Italy
http://members.it.tripod.de/Damianoux/index.html
mailto: dmn@cheerful.com
mailto: damiano@mclink.it

Article: 15740
Subject: Re: FPGAs with ECL-compatible I/Os
From: Ray Andraka <randraka@ids.net>
Date: Sun, 11 Apr 1999 12:11:45 -0400
Links: << >>  << T >>  << A >>
Why is that?  I find pushing the capability of FPGAs is an enjoyable
challenge.  Besides, the current FPGA offerings are quite capable of
100MHz+ data rates in this type of application:  I have a scrambler and
descrambler/framer core set (xilinx 4k) available for SMPTE 292 HDTV
that is designed to work with AMCC's 8401/8501 SerDes chipset for HDTV.
In that case the serial stream is 1.485 GB/s and the AMCC chips do 20
bits, giving a parallel data rate of 74.25MHz.  My macros handle the 75
MHz rate in the slowest speed grades of many of the xilinx 4K families,
and will handle well over 100 MHz in an XLA-09 part.  For more info, see
the data sheet on my website.


> At any rate, I'm glad the vitesse part accepts and emits 20-bit words
> at 53 Mhz because it would be less fun to work at >100 Mhz with FPGA
> technology.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15741
Subject: Re: FPGA vs CPLD? Any Experts out there?
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Sun, 11 Apr 1999 09:52:07 -0700
Links: << >>  << T >>  << A >>
Gary Desrosiers wrote in message ...
>Thank you very much. I ordered the Xilinx book. ...

Note, the book is included with the Xilinx Student Edition package; if you
don't yet have Xilinx tools, you should probably order *that*.  The older
version, 1.3, with schematics and ABEL, has just now been updated to version
1.5, which includes VHDL and Verilog, IIRC.  This new edition is available
from XESS (www.xess.com/fpga); it is not yet available through amazon.com,
although you can place an advance order.

>Have you ever thought of elaborating on the PPT presentation that's on your
>site and giving us beginners a tutorial on uC design?

Yes, I'm working on it, stay tuned.  In the meantime, if you want to learn
FPGA CPU design, I think a good start would be working through the van den
Bout book, and reading "Computer Organization and Design : The
Hardware/Software Interface" by John Hennessy and David Patterson.

Jan Gray




Article: 15742
Subject: Re: FPGA vs CPLD? Any Experts out there?
From: msimon@tefbbs.com (M.Simon)
Date: Sun, 11 Apr 1999 19:12:32 GMT
Links: << >>  << T >>  << A >>
I have a board set designed for FPGA processor development.

See my sig below.


Simon - http://www.tefbbs.com/spacetime/index.html
Article: 15743
Subject: Programming a long daisy-chain Xilinx 4000
From: lzhang@eecg.toronto.edu (Louis Zhang)
Date: 11 Apr 99 19:16:40 GMT
Links: << >>  << T >>  << A >>
Hi,

For programming a long daisy-chain Xilinx 4000 FPGAs,
it seems that CCLK needs to be buffered. Is there any
other signals need to be buffered?  Is there any 
guidelines as how many devices can be programmed without 
buffering?

Thanks for your suggestions in advance.

-----------------------
Louis Zhang
lzhang@eecg.toronto.edu

Article: 15744
Subject: Re: FPGAs with ECL-compatible I/Os
From: Tim Davis <timdavis@tdcon.com>
Date: Sun, 11 Apr 1999 14:49:13 -0600
Links: << >>  << T >>  << A >>
I certainly enjoy the mental exercise of creating fast or small designs. I simply don't enjoy
beating my head against the tools. Xilinx has the best tools around from my experience but EPIC (in
particular) is still a little buggy. Your SMPTE 292 HDTV core datasheet (very nice, professional, ds
by the way) says the RX core is only around 135 CLBs. That small of a design would be fun to work
with.

Ray Andraka wrote:

> Why is that?  I find pushing the capability of FPGAs is an enjoyable
> challenge.  Besides, the current FPGA offerings are quite capable of
> 100MHz+ data rates in this type of application:  I have a scrambler and
> descrambler/framer core set (xilinx 4k) available for SMPTE 292 HDTV
> that is designed to work with AMCC's 8401/8501 SerDes chipset for HDTV.
> In that case the serial stream is 1.485 GB/s and the AMCC chips do 20
> bits, giving a parallel data rate of 74.25MHz.  My macros handle the 75
> MHz rate in the slowest speed grades of many of the xilinx 4K families,
> and will handle well over 100 MHz in an XLA-09 part.  For more info, see
> the data sheet on my website.
>
> > At any rate, I'm glad the vitesse part accepts and emits 20-bit words
> > at 53 Mhz because it would be less fun to work at >100 Mhz with FPGA
> > technology.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka

--

Tim Davis
Timothy Davis Consulting

TimDavis@TDCon.com - +1 (303) 426-0800 - Fax +1 (303) 426-1023


Article: 15745
Subject: URGENT! Need VHDL code for ADPCM decompression on Xilinx FPGA
From: rmishra@ix.netcom.com (Rajeev Mishra)
Date: Sun, 11 Apr 1999 15:27:45 -0800
Links: << >>  << T >>  << A >>
I am trying to find someone who has VHDL source code for decompressing the
Microsoft ADPCM WAV format.

In the past my product used a dedicated Crystal Semi codec, as well as a
micro, to decompress the digital audio.


Given the power of FPGA's today, I'd like to integrate all this
functionality into a single chip.

Any help would be greatly appreciated.

Please email me at "rmishra@ix.netcom.com", as well as to the newsgroup.

Thank you.

Rajeev Mishra
NDirect Technologies



**** Posted from RemarQ - http://www.remarq.com - Discussions Start Here (tm) ****
Article: 15746
Subject: Re: FPGAs with ECL-compatible I/Os
From: Ray Andraka <randraka@ids.net>
Date: Mon, 12 Apr 1999 02:22:48 -0400
Links: << >>  << T >>  << A >>
It is one of my smallest designs.  The documentation took quite a bit longer than design, layout and
verification.
More typical designs are 4028's and 4036's packed 70-90% and running at 50-100 MSPS in radar and
communications systems.  I avoid using EPIC as much as possible (it is the one part of the xilinx tool
suite that still evokes some serious head beating).  I do do extensive floorplanning, but it is done at
the source using RLOCs and FMAPs so that it is a) documented in the design source, b) repeatable without
repeating alot of handwork, and c) reusable.  I try to avoid doing any hand routing for the reasons
stated above.  By keeping my designs very hierarchical, I get a high degree of reuse for pre-placed low
level pieces, so it is relatively rare these days for me to actually add an FMAP.

Tim Davis wrote:

> I certainly enjoy the mental exercise of creating fast or small designs. I simply don't enjoy
> beating my head against the tools. Xilinx has the best tools around from my experience but EPIC (in
> particular) is still a little buggy. Your SMPTE 292 HDTV core datasheet (very nice, professional, ds
> by the way) says the RX core is only around 135 CLBs. That small of a design would be fun to work
> with.
>
> Ray Andraka wrote:
>
> > Why is that?  I find pushing the capability of FPGAs is an enjoyable
> > challenge.  Besides, the current FPGA offerings are quite capable of
> > 100MHz+ data rates in this type of application:  I have a scrambler and
> > descrambler/framer core set (xilinx 4k) available for SMPTE 292 HDTV
> > that is designed to work with AMCC's 8401/8501 SerDes chipset for HDTV.
> > In that case the serial stream is 1.485 GB/s and the AMCC chips do 20
> > bits, giving a parallel data rate of 74.25MHz.  My macros handle the 75
> > MHz rate in the slowest speed grades of many of the xilinx 4K families,
> > and will handle well over 100 MHz in an XLA-09 part.  For more info, see
> > the data sheet on my website.
> >
> > > At any rate, I'm glad the vitesse part accepts and emits 20-bit words
> > > at 53 Mhz because it would be less fun to work at >100 Mhz with FPGA
> > > technology.
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email randraka@ids.net
> > http://users.ids.net/~randraka
>
> --
>
> Tim Davis
> Timothy Davis Consulting
>
> TimDavis@TDCon.com - +1 (303) 426-0800 - Fax +1 (303) 426-1023



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15747
Subject: FPGA board
From: Peter Sels <peter@easics.be>
Date: Mon, 12 Apr 1999 11:39:32 +0200
Links: << >>  << T >>  << A >>
Hello,

I need a FPGA board of 4x4=16 FPGA nodes. Each FPGA has to be able to
hold
about 68k ASIC equivalent gates including some internal RAM.
Practically this means the nodes have to be:
-Altera FLEX 10K, EPF10K200E or bigger or
-Xilinx Virtex XCV200 or bigger
The board also needs an Ethernet connection to be able to steer it from 
any SUN in the ethernet network. Probably Nationals DP83902A ST-NIC chip 
or something similar (any others available?).

http://www.io.com/~guccione/HW_list.html/ is a list of FPGA boards.
But I did not find any boards that satisfy these criteria.
Does anyone know of any that do?

If not, do you know of any company that would be quick in making such a
board
(design + manufacture the prototype, no mass production).

best regards,

Peter
-- 
======================================================================
Peter Sels                   ===              Easics               ===
ASIC Design Engineer         ===  VHDL-based ASIC design services  ===
mailto:peter@easics.be          ===================================
NEW Tel: +32-16-395 605     Interleuvenlaan 86, B-3001 Leuven, BELGIUM
NEW Fax: +32-16-395 619           http://www.easics.com/peter/
Article: 15748
Subject: Regular Expressions in VHDL / FPGA's
From: Christian Geuer-Pollmann <geuer-pollmann@bigfoot.de>
Date: Mon, 12 Apr 1999 13:01:54 +0200
Links: << >>  << T >>  << A >>
Hi,

does anyone here has experience with implementing pattern matching or
regular expressions in VHDL / FPGA's?


Thanks


Christian Geuer-Pollmann
Dipl.-Ing.


-----------------------------------------------------------
Tel: ++49-271-740-2516
Fax: ++49-271-740-2536
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Article: 15749
Subject: SUBSCRIBE
From: George Gallant <ggallant@scuba.ultranet.com>
Date: Mon, 12 Apr 1999 09:49:22 -0400
Links: << >>  << T >>  << A >>




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