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Messages from 15900

Article: 15900
Subject: PIN/PAD files to Schematic Symbols
From: James Jackson <JJackson@bbs.endicor.com>
Date: Tue, 20 Apr 1999 13:10:31 GMT
Links: << >>  << T >>  << A >>
Good morning,

I hope this is not too far off topic for being asked in this forum.

How do most of the folks that use FPGA/CPLD tools create symbols for schematic
capture?

For example, if I use ACCEL EDA Schematic capture, and my engineer uses
Xilinx - or Altera for creating the logic for an FPGA with 403 pins, how am I
supposed to generate my symbol?

If you do not have an answer, then I do.

I use SymbolGen. This is a program that uses PIN or PAD files created by
Altera or Xilinx for input and creates a symbol with pin names and numbers
ready to be placed into ACCEL EDA Schematic capture.

If you are interested, you may download a demo at...

http://www.lonestar.texas.net/~joj

Thank you,

James Jackson

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 15901
Subject: Re: texture mapping hardware
From: Ray Andraka <randraka@ids.net>
Date: Tue, 20 Apr 1999 09:12:40 -0400
Links: << >>  << T >>  << A >>
There was a paper on this subject at FPGA'99.  I think it was work done
by David Lewis at University of Toronto.  It may be up on the ACM site
(www.acm.org) in the digital library, although historically ACM has been
kind of slow getting the publications up there.

You might have better luck David directly at lewis@eecg.toronto.edu

ChangHo Bae wrote:

> Hi.
>
> I'm looking for the paper for texture mapping hardware.
> I want to download this document.
>
> Thanks



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15902
Subject: Re: Question about Statechart
From: Duncan Crowther <duncanc@euro-eda.com>
Date: Tue, 20 Apr 1999 14:26:30 +0100
Links: << >>  << T >>  << A >>
Hi Grzegorz,

We are a European distributor of EDA tools and we supply two products
that may be what you refer to.

BetterState - State chart based system modelling tool that automatically
generates code including C, C++, VHDL, Verilog etc.

StateCAD - Graphical Finite State Machine entry and verification tool,
that automatically generates synthesizable VHDL & Verilog code from
state diagrams. Incorporates StateBench that automatically generates
VHDL & Verilog test benches for design verification.

If you need more details, email me or visit our web site at
http://www.euro-eda.com

Regards
In article <371c9ef7.4103360@news.amu.edu.pl>, Grzegorz Labiak
<G.Labiak@pz.zgora.pl> writes
>Hi!
>
>I'm looking for any information about Statechart. Does anyone have any
>interesting links and info about software releated to Statechart?
>
>Thanks

-- 
Duncan Crowther
EuroEDA Limited

Phone:  +44 (0)1933 676373
Fax:    +44 (0)1933 676372
Email:  duncanc@euro-eda.com
Web:    http://www.euro-eda.com
Article: 15903
Subject: Synopsys & Xilinx 6200
From: "Paul M. Lynch" <P.Lynch@ee.qub.ac.uk>
Date: Tue, 20 Apr 1999 14:44:05 +0100
Links: << >>  << T >>  << A >>
I am using the VCC HotWorks board for the Xilinx XC6200 FPGA. I am
writing in VHDL and using Xilinx's XACTstep 6000 software to read an
EDIF file generated by Synopsys. For some reason, it keeps giving errors
for any blocks which have std_logic_vectors as inputs or outputs. Does
anyone know of any problems along these lines, and more importantly, any
solutions?
-- 
________________________________________________ 
Paul M. Lynch                                   
Dept. of Electrical & Electronic Engineering 
The Queen's University of Belfast            
http://www.ee.qub.ac.uk/dsp/research/telecomms/ 
________________________________________________
Article: 15904
Subject: Question about Statechart
From: G.Labiak@pz.zgora.pl (Grzegorz Labiak)
Date: Tue, 20 Apr 1999 15:40:23 GMT
Links: << >>  << T >>  << A >>
Hi!

I'm looking for any information about Statechart. Does anyone have any
interesting links and info about software releated to Statechart?

Thanks
Article: 15905
Subject: FPGA for PC Cards
From: anurag <anurag@earthling.net>
Date: Tue, 20 Apr 1999 16:57:28 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm looking for info. on the type ( approx. no of gate,
manufacturer  etc... ) of FPGA's deployed in PC Cards
(PCMCIA) being used in the PDA's/laptops. This is
to get a rough estimate on which series of FPGA's which
could be used for these cards.

Any help would be appreciated ! Thanks.........

Anurag

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 15906
Subject: Xilinx Virtex GCLKs
From: Alan Chan <achan@designpr.com>
Date: Tue, 20 Apr 1999 19:14:20 GMT
Links: << >>  << T >>  << A >>
Hi,

I am trying to run my Virtex xcv300 design using Synplify and Xilinx
Alliance. After place and route, I always get the same error message
saying "5 out of 4 GCLKs" used. My design uses only one global clock and
I have instantiated one DLL Macro BUFGDLL in my RTL source. The 50 MHz
clock is connected one of the 4 clock pins, and the rest are used as
normal I/Os. There is also a synchronous reset that is connected to all
flip-flops. Can anyone tell me how to get rid of this error? Many thanks
in advance!

Regards,
Alan

Article: 15907
Subject: Re: Virtex based PCI cards
From: Ray Andraka <randraka@ids.net>
Date: Tue, 20 Apr 1999 15:38:13 -0400
Links: << >>  << T >>  << A >>
You might look at the viper card set from Coreco (formerly Dipix).  That
card is specifically set up for video and imaging applications.  The pixel
processor daughtercard is a Virtex, but I don't recall which one (XCV300
maybe?)
www.coreco.com

Atif Zafar wrote:

> Hello:
>
>     Does anyone know of any development boards (PCI) that use the Virtex
> FPGA? I am interested in a board with preferably several XV800 or XV1000
> devices along with RAM for prototyping a custom graphics pipeline. I
> have heard of the PCI Pamette board, but to my knowledge this does not
> have Virtex silicon. Thanks for any info.
>
> Atif Zafar
> Regenstrief Institute
> Zafar_A@regenstrief.iupui.edu



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15908
Subject: Virtex based PCI cards
From: Atif Zafar <zafar_a@regenstrief.iupui.edu>
Date: Tue, 20 Apr 1999 13:44:35 -0700
Links: << >>  << T >>  << A >>
Hello:

    Does anyone know of any development boards (PCI) that use the Virtex
FPGA? I am interested in a board with preferably several XV800 or XV1000
devices along with RAM for prototyping a custom graphics pipeline. I
have heard of the PCI Pamette board, but to my knowledge this does not
have Virtex silicon. Thanks for any info.

Atif Zafar
Regenstrief Institute
Zafar_A@regenstrief.iupui.edu

Article: 15909
Subject: Okay, a really dumb Xilinx FPGA question.
From: "Gary Desrosiers" <desrosi@pcnet.com>
Date: Tue, 20 Apr 1999 19:49:34 -0400
Links: << >>  << T >>  << A >>
Well, I might feel like an idiot asking this but what 32Kx8 SRAM is used
with a Xilinx XC4000 series?. What makes the config persist? EEPROM? Any
Examples or schematics? Boy, I really feel like a newbie here!

Gary


Article: 15910
Subject: Re: What's the best way to learn about fpga's?
From: martin lytz <ms740990@mindspring.com>
Date: Tue, 20 Apr 1999 20:24:25 -0400
Links: << >>  << T >>  << A >>
if you are doing government designs do vhdl...otherwise learn verilog

Gary Desrosiers wrote:

> I'm just starting out too. I got the Xilinx CPLD  starter kit with the
> Foundation 1.5i series software from www.insight-electronics.com for $99.
>
> It's pretty good because it comes with everything you need including the
> XChecker parallel programming cable and the software as well as a prototype
> board with a XC9536 CPLD. The part comes programmed with a Johnson counter
> program. You will, however need to get a few parts to complete the board
> (this was somewhat disappointing). A LM2940 5v regulator, switch, and 22uF
> cap seems to be missing. Weird.
>
> The software that comes with the kit will program FPGAs as well as the
> CPLDs. The XChecker cable has both the JTAG and the FPGA signals.
>
> The only thing that's missing is support for VHDL. I'm programming using
> ABEL and schematic based designs. They want another $390 for the VHDL
> upgrade. I don't think it's worth it at this point for me.
>
> I needed to get all the patches on the www.xilinx.com site to successfully
> implement a design because the software was getting errors out of the box.
> Xilinx tech support was pretty good diagnosing the problem.
>
> Another thing that I'd suggest is to get "The Practical Xilinx Designers Lab
> Book" that's available at Amazon.com. Thanks to Jan Gray for suggesting
> this. Good book. They have schematics for both CPLD and FPGA development
> boards as well as lots of great projects including microcontoller based
> designs.
>
> I also read "Digital Design using ABEL". Bad book, I don't recommend it.
>
> Gary

Article: 15911
Subject: Re: Okay, a really dumb Xilinx FPGA question.
From: Ray Andraka <randraka@ids.net>
Date: Tue, 20 Apr 1999 21:13:22 -0400
Links: << >>  << T >>  << A >>
The configuration is loaded into registers within the xilinx device.  While
the devices are called SRAM based, the configuration storage inside is
really more like a D flip-flop.  These are strung together in a very long
shift register.  When the device first powers up (or after the program pin
is brought low) an internal state machine tries to load a new configuration
'program' from external storage.  The easiest external storage to use is a
serial EEPROM (Xilinx and Atmel sell these).  Alternatively, the FPGA can be
loaded from a byte wide EEPROM, a microcontroller or anything else that can
produce the required bitstream (I've used SRAM for this too).  For more
detail and schematics, refer to the configuration section in the xilinx data
book.  I think that is what you were asking?

I also often use external RAM on an FPGA to hold intermediate results from
processing that is being done in the FPGA.  In that case, the memory used
depends entirely on you application circuit in the FPGA.

Gary Desrosiers wrote:

> Well, I might feel like an idiot asking this but what 32Kx8 SRAM is used
> with a Xilinx XC4000 series?. What makes the config persist? EEPROM? Any
> Examples or schematics? Boy, I really feel like a newbie here!
>
> Gary



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15912
Subject: Re: What's the best way to learn about fpga's?
From: Ray Andraka <randraka@ids.net>
Date: Tue, 20 Apr 1999 21:17:05 -0400
Links: << >>  << T >>  << A >>
VHDL is also the better choice if you plan to make extensive use of
parameterization in your sub-designs or if you are doing low level design with
placement embedded in the design.  Placement is done by adding component
instantiations (FMAPs and Xilinx primitives in the case of Xilinx) with user
attributes for RLOCs.  Synplicity and Exemplar can pass the user attributes
through to the EDIF netlist.  Fpga Express is no good for this.

martin lytz wrote:

> if you are doing government designs do vhdl...otherwise learn verilog
>
> Gary Desrosiers wrote:
>
> > I'm just starting out too. I got the Xilinx CPLD  starter kit with the
> > Foundation 1.5i series software from www.insight-electronics.com for $99.
> >
> > It's pretty good because it comes with everything you need including the
> > XChecker parallel programming cable and the software as well as a prototype
> > board with a XC9536 CPLD. The part comes programmed with a Johnson counter
> > program. You will, however need to get a few parts to complete the board
> > (this was somewhat disappointing). A LM2940 5v regulator, switch, and 22uF
> > cap seems to be missing. Weird.
> >
> > The software that comes with the kit will program FPGAs as well as the
> > CPLDs. The XChecker cable has both the JTAG and the FPGA signals.
> >
> > The only thing that's missing is support for VHDL. I'm programming using
> > ABEL and schematic based designs. They want another $390 for the VHDL
> > upgrade. I don't think it's worth it at this point for me.
> >
> > I needed to get all the patches on the www.xilinx.com site to successfully
> > implement a design because the software was getting errors out of the box.
> > Xilinx tech support was pretty good diagnosing the problem.
> >
> > Another thing that I'd suggest is to get "The Practical Xilinx Designers Lab
> > Book" that's available at Amazon.com. Thanks to Jan Gray for suggesting
> > this. Good book. They have schematics for both CPLD and FPGA development
> > boards as well as lots of great projects including microcontoller based
> > designs.
> >
> > I also read "Digital Design using ABEL". Bad book, I don't recommend it.
> >
> > Gary



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15913
Subject: Re: Okay, a really dumb Xilinx FPGA question.
From: zule <zule@home.net>
Date: Wed, 21 Apr 1999 01:48:55 GMT
Links: << >>  << T >>  << A >>
Hi Gary,

There are no dumb questions of course.  There are several ways to
configure a Xilinx FPGA.  Byte wide as your thread suggests typically
uses an EPROM ?Kx8 depending on the size of your device.  You could use
an SRAM but you would have to load it at power up which if you did that
you could also just directly load the FPGA as a Async peripheral.  You
can also use serial proms which Xilinx has sized for your device.  

FPGA's are SRAM based devices.  The configuration downloaded to them is
the genetic code that builds the circuits inside.  This genetic code is
retained as long as power holds up and no re-program is issued.

As for configuration the data sheet for every Xilinx device has small
circuit examples.  You can also search the Xilinx support web site @
support.xilinx.com.

Best Regards
Terry

Gary Desrosiers wrote:
> 
> Well, I might feel like an idiot asking this but what 32Kx8 SRAM is used
> with a Xilinx XC4000 series?. What makes the config persist? EEPROM? Any
> Examples or schematics? Boy, I really feel like a newbie here!
> 
> Gary
Article: 15914
Subject: Re: How to use TDO pin of Xilinx4000 in Exemplar ?
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Tue, 20 Apr 1999 20:15:27 -0700
Links: << >>  << T >>  << A >>
Instantiate an OBUF and connect it to a TDO.  Obvious huh?  This worked in
Synopsys, seems like it would work for Exemplar

   //Do the TDO thing (not in Xilinx documentation)
   TDO rclk(.O (regclkout));   //regclk uses the TDO pin P181
   OBUF rclko (.O (regclkout), .I (regclk));

bruce

Ingmar Hohmann wrote in message <7fhg5k$59g$1@circle.bicos.de>...
>Does anybody has instantiated a TDO pin for output with Exemplar ?
>
>
>
>


Article: 15915
Subject: Re: Any good book suggestions
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Tue, 20 Apr 1999 20:17:19 -0700
Links: << >>  << T >>  << A >>
HDL Chip Design by Douglas Smith

Side by side VHDL and Verilog examples of synthesizable  code for things
people want to synthesize.  No PLI.

bruce
edwinpark@my-dejanews.com wrote in message
<7fbk3d$8ga$1@nnrp1.dejanews.com>...
>There seems to be a lot of people asking about learning about FPGAs.  I
want
>to start a discussion about good books.  In the short term, I personally
have
>a need for a good book describing Verilog (I did VHDL in the past) and PLI.
>
>Any other related categories are welcome.
>- VHDL
>- FPGA programming
>etc.
>
>-Edwin
>
>-----------== Posted via Deja News, The Discussion Network ==----------
>http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own


Article: 15916
Subject: Re: FPGA for PC Cards
From: Nicolas Matringe <nicolas@dot.com.fr>
Date: Wed, 21 Apr 1999 09:31:24 +0200
Links: << >>  << T >>  << A >>
anurag wrote:
> 
> Hi,
> 
> I'm looking for info. on the type ( approx. no of gate,
> manufacturer  etc... ) of FPGA's deployed in PC Cards
> (PCMCIA) being used in the PDA's/laptops. This is
> to get a rough estimate on which series of FPGA's which
> could be used for these cards.

2 years ago I worked on a PCMCIA card... We used a Xilinx 4013 E,
running at 20MHz. I think the design took about 70% (I don't remember
very well...)

Hope this helps...

Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
mail reply : remove one dot from the address
Article: 15917
Subject: Re: Zero power gals won't wake up on slow input transitions?
From: aimsir@hotmail.com
Date: Wed, 21 Apr 1999 07:41:39 GMT
Links: << >>  << T >>  << A >>
I'm just posting this again in case the Guru wasn't in that day....

In article <7f6rao$941$1@nnrp1.dejanews.com>,
  aimsir@hotmail.com wrote:
> I'm using a 16v8Z gal from AMD/ VANTIS. Its a zero-power device - sleeping
> when no input activity is sensed(50ns timeout) and waking up when any input
> transition is detected.
>
> After a few days trying to debug some inexplicable behaviour shown by a
> straightforward bit of combinational logic in it - basically during some
> system states certain input transitions were not 'coming through' to  the
> outputs - I am now beginning to think that during the zero power mode this
> device will not reliably respond (ie wakeup and 'turn-on' the logic) to an
> input with a slow rise-time (say >200ns).
>
> The slow rise was from the o/p of a voltage comparator. I was able to speed up
> its rise-time  to c100ns and found that the mis-behaviour was noticeably less
> frequent.
>
> I contacted the manufacturer and after a long wait got a less than explicit
> affirmation of this. For example they wouldn't say what was a suitable
> 'wakeup' rise time. Rien ca change.
>
> Maybe this 'phenomenon' is old hat but I have never seen any mention of it in
> the data sheets or app. notes. Yet one would think that it is a real caveat
> when interfacing these devices to comparators - hardly a rare
> application.
>
> Anyone else seen similar behaviour?
>
> regds
> Mike
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own
>

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 15918
Subject: Re: Zero power gals won't wake up on slow input transitions?
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Wed, 21 Apr 1999 08:35:12 GMT
Links: << >>  << T >>  << A >>
Mike,
	I've seen similar behaviour on CMOS UV EPROMs.  Certain parts
will detect a transition on the address or CS inputs, perform a read
cycle, latch the result and go back to sleep.

I once used one as a standalone lookup table on a board.  The value
that appeared on the output pins after power on would be incorrect,
until a transition was made on one of the address inputs.  This was
only a problem for slow rise time power supplies.

(I fixed it by connecting the power-on-reset signal to the chip select
input.  This doesn't help you though - sorry.)

I think you'll find that most logic datasheets specify either a
maximum input transition time or a minimum input slew rate - and you
are violating this.

Try a schmitt trigger [sp].

Regards,
Allan.

On Wed, 21 Apr 1999 07:41:39 GMT, aimsir@hotmail.com wrote:

>I'm just posting this again in case the Guru wasn't in that day....
>
>In article <7f6rao$941$1@nnrp1.dejanews.com>,
>  aimsir@hotmail.com wrote:
>> I'm using a 16v8Z gal from AMD/ VANTIS. Its a zero-power device - sleeping
>> when no input activity is sensed(50ns timeout) and waking up when any input
>> transition is detected.
>>
>> After a few days trying to debug some inexplicable behaviour shown by a
>> straightforward bit of combinational logic in it - basically during some
>> system states certain input transitions were not 'coming through' to  the
>> outputs - I am now beginning to think that during the zero power mode this
>> device will not reliably respond (ie wakeup and 'turn-on' the logic) to an
>> input with a slow rise-time (say >200ns).
>>
>> The slow rise was from the o/p of a voltage comparator. I was able to speed up
>> its rise-time  to c100ns and found that the mis-behaviour was noticeably less
>> frequent.
>>
>> I contacted the manufacturer and after a long wait got a less than explicit
>> affirmation of this. For example they wouldn't say what was a suitable
>> 'wakeup' rise time. Rien ca change.
>>
>> Maybe this 'phenomenon' is old hat but I have never seen any mention of it in
>> the data sheets or app. notes. Yet one would think that it is a real caveat
>> when interfacing these devices to comparators - hardly a rare
>> application.
>>
>> Anyone else seen similar behaviour?
>>
>> regds
>> Mike
>>
>> -----------== Posted via Deja News, The Discussion Network ==----------
>> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own
>>
>
>-----------== Posted via Deja News, The Discussion Network ==----------
>http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    

Article: 15919
Subject: Re: Virtex based PCI cards
From: thor@sm.luth.se.NoSpam (Jonas Thor)
Date: Wed, 21 Apr 1999 10:22:22 GMT
Links: << >>  << T >>  << A >>
Hello,

Annapolis Micro System have a new family of cards based on the Virtex
Series. For example The Wildstar PCI card have 3 XCV1000. You can
attach differnet IO card such as digital/analog camera cards. 

http://www.annapmicro.com

/ Jonas Thor

On Tue, 20 Apr 1999 13:44:35 -0700, Atif Zafar
<zafar_a@regenstrief.iupui.edu> wrote:

>Hello:
>
>    Does anyone know of any development boards (PCI) that use the Virtex
>FPGA? I am interested in a board with preferably several XV800 or XV1000
>devices along with RAM for prototyping a custom graphics pipeline. I
>have heard of the PCI Pamette board, but to my knowledge this does not
>have Virtex silicon. Thanks for any info.
>
>Atif Zafar
>Regenstrief Institute
>Zafar_A@regenstrief.iupui.edu

Article: 15920
Subject: Re: PIN/PAD files to Schematic Symbols
From: husby@fnal.gov (Don Husby)
Date: Wed, 21 Apr 1999 13:58:06 GMT
Links: << >>  << T >>  << A >>
I also have a pinout tool for Lucent Orca chips.
It can be downloaded from:
   http://www-ese.fnal.gov/eseproj/trigger/pinout.zip

An example output can be found at
   http://www-ese.fnal.gov/eseproj/trigger/hit_pin.htm


The documentation page for this tool follows:
=====================================================================
pinout:
  This program does several things:
  It scans a .ncd file and extracts its pinout.
  It checks the pinout against placement directives in the .prf file.
  It updates the .prf file to reflect the .ncd pinout (if -u option is used)
  It creates a color-coded html pin list that includes power pins and
  configuration pins.

Other features include the ability to assign or prohibit specific
configuration pins such as Mode pins.

Usage:
  pinout [-u] ncdfile   [prffile]       ! .ncd extension is optional

Options:
  -u   Allows the .prf file to be updated with the new pinout

Files:
  %AWKS%\pinout.exe 
  %AWKS%\*.pkg                ! Package files
  ncdread.exe                 ! Neocad ncd reader
  *.ncd                       ! input file
  *.prf                       ! Corresponding preference file
  *_pin.htm                   ! Pinout listing
  *_pin.lis                   ! Error listing and alias listing

When invoked before PAR, pinout.exe extends the .prf syntax to
allow you to specify how confiuration pins such as INIT, DIN,
HDC, LDC, and M0-M3 are used by PAR.

When invoked after PAR with the -u option, the .prf file is
updated to reflect the newly placed pinout.

When invoked without the -u option, the .ncd pinout is checked
against the .prf pinout and any differences are noted.  This
is used to check that newly routed devices match an existing pinout.

The pinout tool uses several delimiters in the .prf file to mark
items that it should interpret.  These delimiters begin with a
"#" in the first column and are interpreted by the Lucent Foundry
tools as comments.  Delimters include:

# pinout begin            ! Mark beginning of pinout section (optional)
                          ! This currently has no syntactical relevance.

# autoplaced              ! Mark beginning of pins that were placed by PAR
# pinout end              ! Mark end of pinout section.
                          ! This must terminate the Autoplaced section

# cfgmode <n> <c>         ! Specify which configuration mode is used.
                          ! This determines which config pins are included
                          ! in the pinout listing.
                          ! Mode 0: Master Serial
                          ! Mode 1: Slave Parallel
                          ! Mode 3: Sync Peripheral
                          ! Mode 4: Master Parallel Up
                          ! Mode 5: Async Peripheral
                          ! Mode 6: Master Parallel Down
                          ! Mode 7: Slave Serial
                          ! The pinout includes VDD5 pins unless the
                          ! C parameter is specified.

# cfgpin <name> <comp>    ! Assign a configuration pin to a comp
# cfgpin <name> prohibit  ! Prohibit use of a configuration pin
# alias <pattern> <name>  ! Replace comp names with a different pin name
# gsub <pattern> <text>   ! Modify comp names that match a pattern

================================================================
Example:  The following lines are part of a .prf file:
================================================================
# Pinout Begin             ! Mark start of pinout-relevent stuff
# CfgMode 7                ! We are using serial-slave mode on a 2Txx device
# CfgPin INIT Prohibit     ! Prevent PAR from using INIT pin
prohibit site "98" ;       ! Translation of previous line
# CfgPin DIN  Prohibit     ! Prevent PAR from using DIN
prohibit site "191" ;      ! Translation of previous line
# CfgPin DOUT Prohibit     ! etc.
prohibit site "195" ;
# CfgPin HDC  Prohibit
prohibit site "89" ;
# CfgPin LDC  Prohibit
prohibit site "94" ;
# CfgPin M0 Prohibit
prohibit site "108" ;
# CfgPin M1 Prohibit
prohibit site "112" ;
# CfgPin M2 REGS/ADR_PAD14                  ! Assign ADR14 to M2 pin
locate comp "REGS/ADR_PAD14" site "117" ;
# CfgPin M3 REGS/ADR_PAD10
locate comp "REGS/ADR_PAD10" site "121" ;

locate comp "K/PAD" site "167";             ! User pre-placed pins
locate comp "REGS/ADR_PAD2" SITE "140" ;

# AutoPlaced                                ! Pins that were placed by PAR
LOCATE COMP       "ALE/PAD" SITE "68";
LOCATE COMP "DBUS/CPD/PAD0" SITE "16";
LOCATE COMP "DBUS/CPD/PAD1" SITE "15";
LOCATE COMP "DBUS/CPD/PAD2" SITE "14";
LOCATE COMP "DBUS/CPD/PAD3" SITE "13";
.. etc ...
# pinout end                                ! end of pinout section
================================================================


Placement:
  Placement is specified using standard Lucent "locate comp"
directives.  Placement directives are treated differently
depending on whether they are inside or outside of the "Autoplaced"
block.  If they are outside, then they cannot be modified by
pinout.exe.  In this case, if the .ncd pinout differs from a
"locate comp" it will be flagged as an error, even if the
-u option is used.

  If a placement directive is inside the Autoplaced block,
and if the -u option is used, then the directive will be updated
to reflect the actual .ncd pinout.

Aliasing:
  When creating the pinout listing, a best-guess algorithm is
used to shorten a heirarchichal pin name to a usable pin name.
For example, the name "C6X/CPD/PAD10" is converted to "CPD10"
You can override the default re-naming algorithm using the
ALIAS or GSUB directives.  ALIAS will find names that match
a pattern (unix regular expression) and substitute a new name.
GSUB will find names that match a pattern and substitute new
text for the pattern.

  For example:
  # ALIAS GX_Q0_WT WAIT 
  will substitute the name WAIT for any pin that matches GX_Q0_WT
  # GSUB PAD
  will remove the word PAD from all pin names.


Package Files:
  In order to use the cfgpin options, pinout.exe requires a
package file.  The package file is simply a list of pins taken
from the Lucent documentation.  It consists of a header line
that specifies the package type (PGA, BGA, QFP), the number of
pin rows, and the number of pin columns.  All remaining lines
consist of a pin number followed by a pin name.  Currently, I
have only created package files for those packages that I am
actually using.  However, it's easy to create your own by 
cutting the text from the Lucent pinout documentation (a .pdf file)
and pasting it into a text file.    

Article: 15921
Subject: Cadence Europractice System Package
From: Carsten Trinitis <Carsten.Trinitis@in.tum.de>
Date: Wed, 21 Apr 1999 15:39:11 +0000
Links: << >>  << T >>  << A >>
Hi,

does anyone know some details about the components that are part
of Cadence's System Package that comes with the Europractice program?
The information we get from Europractice's WWW pages is somewhat
scarce!
Thanks in advance

   Carsten

-- 
===========================================================
Dr.-Ing. Carsten Trinitis
Lehrstuhl fuer Rechnertechnik und Rechnerorganisation
Institut fuer Informatik, Technische Universitaet Muenchen
Arcisstr. 21, D-80290 Muenchen, Germany
Tel.: +49/89/289-25771, FAX:  +49/89/289-28232
email: Carsten.Trinitis@in.tum.de
WWW:   wwwbode.in.tum.de/~trinitic
============================================================
Article: 15922
Subject: Re: High speed reconfigurability
From: Vicente Baena <baena@gte.esi.us.es>
Date: Wed, 21 Apr 1999 19:30:01 +0200
Links: << >>  << T >>  << A >>
Hi all,

try the following link:

http://www.sidsa.es/fipsoc.htm

FIPSOC (Field Programmable System On Chip) is a new kind of device with an
analog part (programmable DACs, programmable ADCs and programmable
amplifiers), a microprocessor (8051), and an FPGA. All this stuff in only
one chip, and fully reconfigurable.

You can reconfigure the chip "on the fly" while it is working without
stopping the clock, or you can download two different configuration to the
chip and swap between them in any moment (this swapping can be done
externally or programmed internally (by the micro or the logic part)). For
example suppose you have a system that need to multiply two numbers and do
something with the result, you can configure the FPGA as a multiplier in one
context (say context 0: C0) and as the rest of the system in context 1 (C1),
then the FIPSOC work like a time multiplexed  FPGA, with two different
functionalities in time (C0,C1,C0,C1,....)

The software is very user friendly, it has all you need:
you enter with a schematic capture or VHDL, you can configure very quickly
and easily the analogic part, you have an 8051 emulator, a wave analyser (to
see what happen internally in the FPGA), you can use breakpoints when using
the 8051...etc

by now it is only a prototype, but I'm sure there will be a commercial
version in a few months. See the link above for more information.

--
Vicente Baena Lecuyer
baena@gte.esi.us.es




Mark wrote:

> I like to possibilities offered by reconfigurable FPGAs, but it seems
> most of the devices around are designed to be loaded once on power up,
> and maybe reconfigured to do something different if the designer is
> being really ingenuitive.
>
> I've heard talk of some new FPGAs from Xilinx which alow partial
> reconfigurability (6000 series?), but i don't see these as being
> particularly more useful.... ? Anyone disagree here ?
>
> What i think would be really interesting, is being able to re-configure
> an entire FPGA really quickly (say 1 system clock period ideally).  This
> translates into the idea of having 'layers' of FPGA config data which
> can be latched into the FPGA config area.  The inactive 'layers' being
> updated or replaced while not in use -> pretty much like a video display
> where an image is built up in the off screen buffer before the active
> video buffer is toggled.
>
> The implications of such an architecture are of course ghastly amounts
> of configuration data flying around and a squadron of PentiumIV's
> working overtime trying to place, route and load all this into our
> liquid cooled UltraFPGA.  But if applied to a pretty small block of
> reconfigurable logic i think the creative designer could do some really
> neat things.
>
> ....any comments ?
>
> Are there any such devices out there already ?
>
> Regds,
> Mark K.
>
> -- Life is about wanting what you don't know you don't want. --



Article: 15923
Subject: Asynchronous Logic in Altera 10K devices
From: ja2mills@novice.uwaterloo.ca (J Mills)
Date: 21 Apr 1999 19:10:29 GMT
Links: << >>  << T >>  << A >>
Hello,

I am investigating the feasibility of using Altera 10K20 FPGA's in some 
undergrad labs.  One of the labs that may be moving to FPGA's involves 
the design and implementation of fundamental mode circuits, and I have 
some concerns:

1) Will the lookup tables behave well from an asynchronous point of view.
   ie. a single transition at an input causes one or zero transitions at
   the output.  I seem to remember that Xilinx 4000-series devices had such a
   specification, but the Altera documentation I have doesn't say.

2) Is there any possibility of damaging the chip by downloading a
   pathological oscillating design?  It must be student-proof.  (Or at least
   student-resistant)

I would greatly appreciate any other advice you might have on this topic.  
In case someone's interested, the full part number of the device being used
is EPF10K20RC240-4.  There is also an EPM7128SLC84-7 on the boards we are
using.

Many thanks,

Jason Mills


Article: 15924
Subject: Re: Virtex based PCI cards
From: "Ahmad Alsolaim" <alsolaim@ieee.org>
Date: Wed, 21 Apr 1999 16:07:25 -0400
Links: << >>  << T >>  << A >>
Or you may use  Ballynuey Virtex FPGA Based PCI card for DSP and Image
Processing from Nalltech
There web:
http://www.nallatech.com/dime/ballynuey/ballynuey.htm



Atif Zafar <zafar_a@regenstrief.iupui.edu> wrote in message
news:371CE733.7CF952B0@regenstrief.iupui.edu...
> Hello:
>
>     Does anyone know of any development boards (PCI) that use the Virtex
> FPGA? I am interested in a board with preferably several XV800 or XV1000
> devices along with RAM for prototyping a custom graphics pipeline. I
> have heard of the PCI Pamette board, but to my knowledge this does not
> have Virtex silicon. Thanks for any info.
>
> Atif Zafar
> Regenstrief Institute
> Zafar_A@regenstrief.iupui.edu
>


--
_____________
Ahmad Alsolaim
School of Electrical Engineering and Computer Science
Ohio University
Athens, OH 45701
Voice: 740-594-2165
Fax:  978-477-8915
email: alsolaim@ieee.org
http://www.ent.ohiou.edu/~alsolaim
_____________________________






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