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Gary Desrosiers wrote: > Sure, you can implement a microcontroller design in a FPGA but can you do > the same with CPLDs? Are there any examples? I did an 8-bit RISC uC in VHDL in a Cypress 512 macrocell CPLD. The actual uC took up about 384 macrocells, and most of that was the register file (16 registers of 8 bits = 128 macrocells). It ran at about 22 MHz/22 MIPS on their -83 speed grade part. I tried to do a 6502 clone in a CPLD. This turned out to be a futile effort. I did one in an FPGA and tried to port it to a CPLD. It would not fit into a 512 macrocell part. It appears that the largest part of the problem is the microcode ROM. It's just too large to be put into macrocells. David Kessner davidk@peakaudio.comArticle: 15751
Svana, A QuickLogic QL4016 will also do the trick. You can use the FIFO wizard to create a synthesizable FIFO in Verilog or VHDL. 8 of the 10 RAM blocks on this small device would be used to create a 9-bit x 1024 FIFO. Each RAM block would be configured as a 9-bit x 128 Duel Port RAM. In addition, you will have 250+ logic cells available for other glue logic. - Brian Small QuickLogic Design Center vanan wrote in message <7ebvi8$1vb$1@newton.pacific.net.sg>... >Hi! > >Anyone know about 8bit x 1K FIFO can implemented in FPGA ? > >If yes , Pls give me the vendor and part number. > >Any application note ? will be great . > >Thanks > >Svana > >Article: 15752
It works great leaned up against the house for growing ivy. :-) NO-SPAM damiano wrote: > > Hi all, > What do you think about lattice? > > Damiano Rullo > Trezzano S/N > Milan, Italy > http://members.it.tripod.de/Damianoux/index.html > mailto: dmn@cheerful.com > mailto: damiano@mclink.it -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 15753
Hello I don't know if this scenario is exactly related to what you whant to talk about, but let's suppose that you have an FPGA that can reconfigure itself from a serial EPROM. There are four bitstreams in the EPROM and, depending on the application inputs, one of the bitstreams is selected to be loaded (FPGA's new configuration). From Xilinx databook, an application in an FPGA can select a bitstream from an parallel EPROM, by saving in a register the bitstream start address, and after that putting the PROGRAM pin in 0. Is it possible to have something similar using serial EPROMs? And what about serial RAMs? Can I use a serial RAM to store FPGA bitstreams? Eduardo. "J. Khatib" wrote: > > OK > It seems that there are some people want to talk about it. > What do you want to talk about? > > Bourguiba Riad wrote: > > > > Does any one want to talk about Dynamic Configuration? > > > > Here is my ICQ # : 33301195 > > > > Contact me. > > > > Riad BourguibaArticle: 15754
Louis Zhang wrote: > Hi, > > For programming a long daisy-chain Xilinx 4000 FPGAs, > it seems that CCLK needs to be buffered. Is there any > other signals need to be buffered? Is there any > guidelines as how many devices can be programmed without > buffering? > You seem to think that the CCLK output is not strong enough to drive a capacitive load. That is really not the problem. The CCLK drive impedance is better than 30 Ohms, so even a 1000 pF load will still give a rise time of less than 50 ns. If you use the slower ( default ) option for the CCLK clock rate ( nominally 1 MHz ) this obviously is ok. You can have more problems with reflections on the CCLK line due to a rise/fall time that is too fast. But extra buffering is not the cure for that. Dynamic termination at the far end may be necessary ( 50 Ohm and 1000 pF in series, to ground ). Peter Alfke, Xilinx ApplicationsArticle: 15755
Hi Jan,
I have been following this thread very closely. I am designing a RISC
CPU based on the MIPS 2000 from Computer Organization and Design : The
Hardware/Software Interface" by John Hennessy and David Patterson onto an
ORCA2C40 FPGA. Obviously I have that book. I also have the new Michael Celitti
book on Verilog that has the Xilinx Student Edition (I don't have the book
right now with me to quote the exact version #.) I am doing this design in
Verilog with two main design goals 1. Describe the entire design at a
behavioral level in Verilog
2. Get the entire 32-bit design to fit onto
the ORCA2C40.
I would appreciate any help...like book/link suggestions.
Thank you.
Weri.
In article <7eqien$pnt$1@news-2.news.gte.net>,
"Jan Gray" <jsgray@acm.org.nospam> wrote:
> Gary Desrosiers wrote in message ...
> >Thank you very much. I ordered the Xilinx book. ...
>
> Note, the book is included with the Xilinx Student Edition package; if you
> don't yet have Xilinx tools, you should probably order *that*. The older
> version, 1.3, with schematics and ABEL, has just now been updated to version
> 1.5, which includes VHDL and Verilog, IIRC. This new edition is available
> from XESS (www.xess.com/fpga); it is not yet available through amazon.com,
> although you can place an advance order.
>
> >Have you ever thought of elaborating on the PPT presentation that's on your
> >site and giving us beginners a tutorial on uC design?
>
> Yes, I'm working on it, stay tuned. In the meantime, if you want to learn
> FPGA CPU design, I think a good start would be working through the van den
> Bout book, and reading "Computer Organization and Design : The
> Hardware/Software Interface" by John Hennessy and David Patterson.
>
> Jan Gray
>
>
-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
Article: 15756Eduardo Augusto Bezerra wrote: > Hello > > I don't know if this scenario is exactly related to what you > whant to talk about, but let's suppose that you have an FPGA that > can reconfigure itself from a serial EPROM. There are four > bitstreams in the EPROM and, depending on the application inputs, > one of the bitstreams is selected to be loaded (FPGA's new > configuration). From Xilinx databook, an application in an FPGA > can select a bitstream from an parallel EPROM, by saving in a register > the bitstream start address, and after that putting the PROGRAM pin > in 0. Is it possible to have something similar using serial EPROMs? > And what about serial RAMs? Can I use a serial RAM to store FPGA > bitstreams? You cannot select any one of severalserial bitstreams stored in an SPROM. You can, of course, sequentially configure first from the first bitstream, then reconfigure without resetting the SPROM, etc. Really tedious, and I don't see why anybody would do this. You can obviously connect four SPROM in parallel and select externally between them. If you can find a serial RAM, you could use it also, but I have never seen one. Of course, you could emulate one, controlled bt a CPLD. Peter Alfke, Xilinx ApplicationsArticle: 15757
Hi
Has anyone experienced problems with one hot FSM's not getting there
initial state
set? I'm useing Xilinx Alliance 1.5i and Synplicity. Seems that a reset
ff is being selected
instead of a preset.
Thanks
--
George Smith
Avalex Technologies
Atlanta, Ga.
404.256.3010
I.R.S. We have what it takes to take what you have.
-- Support the national sales tax.
Article: 15758On Fri, 09 Apr 1999 13:23:56 -0700, Peter Alfke <peter@xilinx.com> wrote: >Peter Alfke wrote: > >> Not really "a lot of logic".For 16 states, it takes five 4-input LUTs = less >> than three CLBs to detect all 65000+ illegal states, and flag the error on one >> >> common output. > >Sorry, I was off by a factor of two: >You need 6.5 CLB to monitor 16 inputs: > >Each group of 4 inputs drives two parallel LUTs, one detects zero active inputs, >the other one detects exactly one active input. >On the next level, you do the same, and the third level gives you the result. > >Sorry for the overenthusiastic error. >Look-up table are powerful, nevertheless. The amount of logic required to detect an illegal state isn't really the problem. The problem is that the base fsm can generally be coded in one CLB level, and so is fast, but the error detection circuit may take several CLB levels, and so is the critical path. With this example, the machine may run at only a half or a third of the original speed, and so any advantage you got from one-hot coding has probably been lost. EvanArticle: 15759
william pawlowski wrote in message <01be83be$37a5f300$d7364f0c@newmicronpc>... >Has anyone ever seen the when in a viewlogic schematic with a bus labeled > > DATA[27:00] > >that FPGA Express strips out bits 09 through 00 and all componets? Sounds like those bits weren't used, and the tools optimized them away. -- a ------------------------------------------ Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters@noao.edu Don't waste apostrophes! The plural of the acronym for "personal computers" is PCs, NOT PC's.Article: 15760
Hello to everyone who can help. I would like to implement a PAL cinescope (PAL monitor 75% color BAR) using a PLD alone or in conjunction with an EPROM, does any experienced programmer of such devises know how to implement such a thing? could you help in this "to me" very important matter ? the second Q. may be stupid. any one knows what is the differences between microcontrollers and EPROMs, which is better? reply to following emails: alcasert@tin.it Alessandro.Caserta@orbit.net solong and onece again thanks.Article: 15761
Thanks for the input. Unfortunately there was not much comment from different people. In summary it looks like Xilinx is the better architecture, although Altera has a FIR filter generation tool and good software tools. **** Posted from RemarQ - http://www.remarq.com - Discussions Start Here (tm) ****Article: 15762
Anyone know of any differences between the Viewlogic offering of FPGA Express and the Xilinx offering of FPGA Express? Thanks, Austin Franklin austin@darkroom.comArticle: 15763
Weri Kuolstad wrote in message <7etaf5$1ev$1@nnrp1.dejanews.com>... >Hi Jan, > I have been following this thread very closely. I am designing a RISC >CPU based on the MIPS 2000 from Computer Organization and Design : The >Hardware/Software Interface" by John Hennessy and David Patterson onto an >ORCA2C40 FPGA. Obviously I have that book. I also have the new Michael Celitti >book on Verilog that has the Xilinx Student Edition (I don't have the book >right now with me to quote the exact version #.) I am doing this design in >Verilog with two main design goals 1. Describe the entire design at a >behavioral level in Verilog > 2. Get the entire 32-bit design to fit onto >the ORCA2C40. > >I would appreciate any help...like book/link suggestions. >Thank you. >Weri Be careful. An ill-prepared behavioral design may be much larger or slower than necessary. To achieve a feasible, fast, and/or small FPGA implementation of a RISC processor, or anything else, you must first determine how your datapath maps to FPGA device primitives, e.g. 4-LUTs, FFs, BUFTs, RAMSs, CYs, etc. I think this is crucial. You must study and internalize your FPGA data sheets, and, if available, review exemplary implementations. Only when you understand where (and how and how many of) your rams, adders, registers, muxes, etc. should fall on the die, only then, should you write your first line of Verilog or draw your first FDCE. For the specific case of an instruction set compatible processor implementation: only when you understand what should be implemented in hardware, what in state machines, and what should trap to software, only then should you "break out the Verilog". For example, MIPS-I implies a 32-bit barrel shifter. These are expensive to implement in an FPGA, comparable in area to a modest I-cache. If you thought about how a barrel shifter would map to device primitives, you might instead profitably design a small, multi-cycle shifter, perhaps one which only does 1- and 4-bit shifts each cycle, saving LOTS of chip area for other things. Another example. MIPS-I implies a 1-cycle branch delay. In a straightforward implementation of the pipelined datapath sketched in Hennessey and Patterson, this would require 2 PC adders, one for PC+4 and one for PC+branch-displacement, and a MUX selecting between them. Instead, if you can accept a 2-cycle branch latency (e.g. one branch delay slot and one annulled cycle on branch taken), you can build a circuit in about 1/3 the area (PC + cheap-mux(4,sign-ext(branch-disp))). Sooo, once you have decided what you expect the tools to output in the end, then it's a simple matter of "pushing on a rope" to get your particular elaboration tools to map your design specification into the right inputs to your FPGA vendor's implementation tools. Schematics give you more direct control, HDLs more parameterization, netlist generators, the best of both worlds (at the expense of incompatibility with anything else). If you take this advice to heart, you should have no trouble fitting your design into a 2C40. IIRC that has 30x30 4-bit PFUs. My first 32-bit pipelined RISC, which did most of the MIPS-I integer instructions, had a datapath that was 16x11 2-bit CLBs, e.g. only about 5% of a 2C40. See my datapath floorplan slide (in www3.sympatico.ca/jsgray/j32.ppt or at www3.sympatico.ca/jsgray/sld021.htm) for an example. If you can figure out how to make your behavioral Verilog source code compile to the desired device primitives, I would use that. Otherwise I would try to specify the datapath (only) in structural Verilog. I experimented with this last year using Foundation / FPGA Express Verilog with good results, although I had a little helper script to generate a UCF file to constrain the resulting primitives' LOCs to my desired floor plan. I look forward to using other Verilog compilers which reportedly can pass FMAP and RLOC attributes through to the FPGA implementation tools. I had not heard of this Celitti book w/ XSE, can you provide more information? Jan GrayArticle: 15764
I think they screwed up when they had the lead in ISP technology 6-7 years ago and didn't capitalize on it. NO-SPAM damiano wrote: > > Hi all, > What do you think about lattice? > > Damiano Rullo > Trezzano S/N > Milan, Italy > http://members.it.tripod.de/Damianoux/index.html > mailto: dmn@cheerful.com > mailto: damiano@mclink.itArticle: 15765
Brian Small wrote: > > Svana, > > A QuickLogic QL4016 will also do the trick. You can use the FIFO wizard to > create a synthesizable > FIFO in Verilog or VHDL. 8 of the 10 RAM blocks on this small device would > be used to create > a 9-bit x 1024 FIFO. Each RAM block would be configured as a 9-bit x 128 > Duel Port RAM. BTW ... RAM/ROM/FIFO Wizard is available in version 7.11 of FREE QuickChip tools :-)Article: 15766
Synopsys owns Viewlogic. They are the same. XILINX may be a rev back. Also the viewlogic can do multiple vendors. Austin Franklin wrote: > Anyone know of any differences between the Viewlogic offering of FPGA > Express and the Xilinx offering of FPGA Express? > > Thanks, > > Austin Franklin > austin@darkroom.com -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 15767
Sure - they don't peacefully coexist on the same machine. Whichever one was installed last works, the other gets hosed since they don't have independent registry entries. Otherwise, if the version #s match they are the same although the Xilinx version only targets Xilinx FPGAs. Adam Austin Franklin wrote: > Anyone know of any differences between the Viewlogic offering of FPGA > Express and the Xilinx offering of FPGA Express? > > Thanks, > > Austin Franklin > austin@darkroom.comArticle: 15768
Jan Gray wrote in message <7ettgk$ddr$1@news-2.news.gte.net>... >Only when you understand where (and how and how many of) your rams, adders, >registers, muxes, etc. should fall on the die, only then, should you write >your first line of Verilog or draw your first FDCE. I don't like my own advice here, so let me try again. Implementing a processor or other substantial design is an iterative process with subproblems which require analysis and experimentation. The more expert you are with your tools and with the device architecture, the less experimentation you'll need. If you're new to FPGA design, I think taking some time to try out different solutions to the subproblems will help to save time overall and achieve a better result. Some of the subproblems to investigate include: * how to implement a register file? a 2 read / 1 write port register file? * how to source an operand from a register or an immediate field * how to implement an ALU? a shifter? * how to multiplex the many results (incl. ALU, shifts, loads, sign exts (lbs), jal's) * how to implement zero/negative/carry/overflow detect? * what is the external memory or on-chip bus interface like? * how to implement load/store byte lane alignment logic? * how to implement an instruction register? a program counter? incrementing it? branch displacements? * how to pipeline the design? how many stages are beneficial? how to stall pipe? how to annul insns? * how to deal with pipeline hazards? memory not ready? branch/jump shadows? data hazards? * where to implement the effective address adder? * should memory be 1- or 2- ported? how to mux eff. addr. with PC? * how to do interrupts and return from interrupt? * what is the clock discipline? rising or both edges? 1 or multiple clocks per insn? * what are the critical paths? what is the feasible cycle time? what is the required cycle time? * is any retiming needed? Some of these analyses will benefit from actually designing the subunit and observing what the tools produce, including layouts and delays (EPIC / static timing analysis). And trying some alternatives. Then you'll know approximately how much area and time it takes to do a register file writeback and read vs. an add vs. a wide-mux vs. a 32-bit zero detector and will be able to make intelligent tradeoffs. Have fun! Jan.Article: 15769
Tim Davis wrote in message <371000E0.D3905047@tdcon.com>... [Error coding algorithms] >Since everybody says that C and Verilog are virtually identical you should be able to simply copy >the C into a Verilog module shell and be happy as a clam. Not to mention as slow as a clam if you decide to just turn all those C variables into VHDL/Verilog variables (as opposed to signals). :-)Article: 15770
Hi George, When presetting a flipflop, Leonardo and I presume Synplify still use the reset signal, but insert an inverter at the input and output of the flipflop. It may not be durectly obvious if there is logic at the input or output, because in that case the inverter is embedded in the function at the input or output. If the output of the flipflop is directly connected to an output pin (in which case an IOB flipflop is not used), you'll actually see the inverter on the schematic viewer. you can verify this by doing a post-synthesis simulation. I hope this helps. Dr Yves Tchapda ASIC and Protocol Design Engineer Power X EnglandArticle: 15771
Though true a little while ago, I believe that has recently changed and Viewlogic is a separate company. Thanks, Austin APS <resp@associatedpro.com> wrote in article <3712ACB8.65695A01@associatedpro.com>... > Synopsys owns Viewlogic. They are the same. XILINX may be a rev back. > Also the viewlogic can do multiple vendors. > > Austin Franklin wrote: > > > Anyone know of any differences between the Viewlogic offering of FPGA > > Express and the Xilinx offering of FPGA Express? > > > > Thanks, > > > > Austin Franklin > > austin@darkroom.com > > -- > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ > > Richard Schwarz, President EDA & Engineering Tools > Associated Professional Systems (APS) http://www.associatedpro.com > 3003 Latrobe Court richard@associatedpro.com > Abingdon, Maryland 21009 > Phone: 410.569.5897 Fax:410.661.2760 > > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ > > >Article: 15772
Is there any FPGA with documented bit stream?Article: 15773
Hi, is it possible to have more control over the placement of the LOGIBLOX instances using placement constraints (LOC/RLOC) in the .UCF file? I've made a 256x8 RAM with LOGIBLOX and after P&R, the thing is all over the place. I know that it is possible to put constraints on the MEMx_y portion of the RAM, but the rest of the logic consists of gates and you can't put constraints on gates. After studying the structure of the RAM in the .xnf file, I tried to fiddle with the .xnf file and put some FMAP's in there. Unfortunately, this .xnf file is not used in the mapping phase since the tool does a "LogiBlox expansion" on the instance, completely skipping the .xnf file and, hence, my RLOC'ed FMAPs. Any suggestions? -- name : Jo Depreitere | University of Ghent e-mail : jdp@elis.rug.ac.be | Electronics and Information Systems Dept. Phone : ++32+9/264 34 09 | Sint-Pietersnieuwstraat 41, B-9000 Ghent Fax : ++32+9/264 35 94 | http://www.elis.rug.ac.be/~jdpArticle: 15774
Is there an application note or some other information about using the temperature sensing diode on the Virtex chip? Specifically, we want to implement a failsafe cutoff if the temperature goes too high. -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z