Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 18175

Article: 18175
Subject: Re: Multiplierless FIR filters in FPGAs
From: Ray Andraka <randraka@ids.net>
Date: Tue, 05 Oct 1999 09:40:28 -0400
Links: << >>  << T >>  << A >>
Although its response shape is limited, The cascaded integrator comb
filter is one you might find useful.  See E.B. Hogenauer, “An Economical
Class of Digital Filters for Decimation and Interpolation”, IEEE Trans
on ACSSP vol ASSP-29 no.2 April 1981

I haven't seen too much on designing FIR filters with power of two
coefficients.  If you find anything, please post it for the rest of us.
What is the complete citation for the H. Samueli paper?

flavioas@my-deja.com wrote:

>     Hi,
>
>     We are looking for some papers on how to
> implement multiplierless filter structures in
> FPGAs. Papers like "Design of multiplierless
> digital data transmission filters with
> powers-of-two coefficients" H. Samueli. and others
> talking about "CSD coefficients" will be helpfull.
> Can any one help?
>    We are trying to subscribe to this newsgroup,
> using outlook express to connect to the server :
> nntp-serv.cl.cam.ac.uk, and getting the message:
> "you have no permission to talk to this server".
> So, How to subscribe?
>
>      Thanks in advance,
>
>      Flávio Andrade
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18176
Subject: Designers wanted
From: "Margaret Dailey" <margaret@cyberhighway.net>
Date: Tue, 5 Oct 1999 07:29:08 -0700
Links: << >>  << T >>  << A >>
FPGA designers needed in Portland, Oregon.  Requires 3+ years' experience
including recent experience designing FPGAs.  Must be proficient with
Verilog and VHDL.  These positions are full time and require the designer to
work onsite at the client's facility in Portland.  Please respond with your
resume.  Principals only.


Article: 18177
Subject: Re: Multiplierless FIR filters in FPGAs
From: "Andy Peters" <apeters.nospam@nospam.noao.edu.nospam>
Date: Tue, 5 Oct 1999 11:41:18 -0700
Links: << >>  << T >>  << A >>
flavioas@my-deja.com wrote in message <7tcsra$rkh$1@nnrp1.deja.com>...

>   We are trying to subscribe to this newsgroup,
>using outlook express to connect to the server :
>nntp-serv.cl.cam.ac.uk, and getting the message:
>"you have no permission to talk to this server".
>So, How to subscribe?

you need to talk to the sysadmin for the server in order to get permission
to use it.


--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Creation Science" is oxymoronic.



Article: 18178
Subject: Re: Multiplierless FIR filters in FPGAs
From: mush@slip.net (Dave Decker)
Date: Tue, 05 Oct 1999 18:48:12 GMT
Links: << >>  << T >>  << A >>
On Tue, 05 Oct 1999 09:21:44 GMT, mush@slip.net (Dave Decker) wrote:

>On Tue, 05 Oct 1999 13:01:38 GMT, flavioas@my-deja.com wrote:
>
>>
>>
>>    Hi,
>>
>>    We are looking for some papers on how to
>>implement multiplierless filter structures in
>>FPGAs. Papers like "Design of multiplierless
>>digital data transmission filters with
>>powers-of-two coefficients" H. Samueli. and others
>>talking about "CSD coefficients" will be helpfull.
>>Can any one help?
>>   We are trying to subscribe to this newsgroup,
>>using outlook express to connect to the server :
>>nntp-serv.cl.cam.ac.uk, and getting the message:
>>"you have no permission to talk to this server".
>>So, How to subscribe?
>>
>>     Thanks in advance,
>>
>>     Flávio Andrade
>>
>>
>>Sent via Deja.com http://www.deja.com/
>>Before you buy.
>
>
>There are some interesting papers at the U of K. on automatic filter
>generation using sparce numbers of ones in the coefficients to
>minimize the size of the constant multipliers.
>try:
>ftp://ftp.tisl.ukans.edu/pub/projects/DSP/FPGA/Filters_and_CAD.pdf
>
>for one.
>
>Dave Decker
Also look at:
http://www.ittc.ukans.edu/projects/FPGA/
This page seems to have moved since the last time I tried to find it.
Webmaster Doug Herbers was kind enough to point me to it's new puka.
Thanks Doug

Cheers,
Dave Decker
Article: 18179
Subject: Board Designers required
From: Ravi Singh <rsingh@comptelinc.com>
Date: Tue, 05 Oct 1999 16:04:38 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------00806641D7476D06B694E93A
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

We require Sr. Design engineers who are willing to work in a high tech
company in the Maryland area on a contract basis. The job requires to
work on Board design candidate should be proficient in ASIC/ FPGA,
Verilog should have worked on Altera. Please provide your contact
details also with the resume. Thanks
--------------00806641D7476D06B694E93A
Content-Type: text/x-vcard; charset=us-ascii;
 name="rsingh.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Ravi Singh
Content-Disposition: attachment;
 filename="rsingh.vcf"

begin:vcard 
n:Singh;Ravi
tel;cell:(703) 582 7819
tel;work:(703) 556 0033
x-mozilla-html:FALSE
org:Comptel, Inc.
version:2.1
email;internet:rsingh@comptelinc.com
title:Director - Business Development
adr;quoted-printable:;;2102 C, Gallows Road,=0D=0ASouth Office Tyson Park,=0D=0A;Vienna;VA ;22182;U.S.A
fn:Ravi Singh
end:vcard

--------------00806641D7476D06B694E93A--

Article: 18180
Subject: Re: Free Hardware "CPLD board"
From: "Mahmut C. Genceli" <yunus@AdvancedRelay.com>
Date: Tue, 05 Oct 1999 13:39:03 -0700
Links: << >>  << T >>  << A >>


Jamil Khaib wrote:
> 
> Hi,
> Have you ever imagined that you could build hardware with ZERO design
> cost?
> Do you want to test your digital designs?
> Do you want to have your own CPLD prototyping board?
> 
> You can check our project at
> http://www.openip.org/oc/projects/board/board.html
> 
> The design is available for free under the openip license. It is based
> on free and only free software tools and design methodology.
> 
> The site contailn links to lot of free EDA tools
> 
> for more information about the openip organization you can visit our
> site at
> http://www.openip.org
> or contact our mailing list at openip@egroups.com or
> http://www.egroups.com/group/openip/ on the web
> 
> Please give us your comment on the design itself and the methodology we
> are using
> 
> Thanks
> Jamil Khatib
> khatib@openip.org
> OpenIP Organization
> http://www.openip.org

Article: 18181
Subject: Re: Producing 60/40 clock in vhdl
From: thompson@ren.eecis.udel.edu (Tyrone Thompson)
Date: 5 Oct 1999 21:04:28 GMT
Links: << >>  << T >>  << A >>
I will give this a try. Is there some information on how to do this in VHDL
somewhere? I haven't seen in the documentation. In case it's not obvious yet
this is my first real project with FPGA's and VHDL.

Tyrone

In article <37F7F87E.186502C3@ids.net>, Ray Andraka  <randraka@ids.net> wrote:
>Presumably, the reference clock is stable as is the device parameters
>that affect the
>delay.   If the output ratio is constant, then I would expect the delay
>to try to stay
>at one point until the temperature, voltage or reference change.  That
>point may be (is
>probably) between two of the taps in the delay line, but since the exact
>duty cycle is
>probably not critical you could set it up with enough filtering
>(basically hysterisis)
>to keep it from jumping back and forth.  Basically, the DLL picks the
>tap in a delay
>line that is closest to the delay that give the desired output.  The
>finer the delay
>increment the less the size of the jump (which is why I was suggesting
>the carry logic
>might make a good tapped delay line).
>
>Alvin E. Toda wrote:
>
>> On Sun, 3 Oct 1999, Ray Andraka wrote:
>>
>> > Depending on delays in FPGAs is generally a bad practice, as the
>design becomes
>> > very sensitive to routing, as well as to process improvements.  You
>might be able
>> > to reliably use the FPGA circuit delays by constructing a delay lock
>loop in the
>> > FPGA logic.  It uses feedback to adjust how many delay elements are
>in the signal.
>> > You could probably use the carry chain as the delay line, as it has
>relatively
>> > short and consistent delays for each "tap".  You will have to be
>careful about the
>> > routing off the taps though. I haven't tried this to see how well it
>works, but at
>> > 25 MHz, you might be able to pull it off.
>>
>> It would seem that another consideration would be the amount of
>> jitter on the clock edge that could be tolerated, since it would
>> seems that switching between taps would produce such behavior.
>> Perhaps since the clocking is only needed for a special device,
>> that specific asynchronous logic be designed so that the sequencing
>> of signals is always correct and IAW whatever signals come
>> back from the device.
>>
>> --al toda
>>
>> ###########################################################
>> Alvin E. Toda              aet@lava.net
>> sr. engineer               Phone: 1-808-455-1331
>> 2-Sigma          WEB: http://www.lava.net/~aet/2-sigma.html
>> 1363-A Hoowali St.
>> Pearl City, Hawaii, USA
>
>
>
>--
>-Ray Andraka, P.E.
>President, the Andraka Consulting Group, Inc.
>401/884-7930     Fax 401/884-7950
>email randraka@ids.net
>http://users.ids.net/~randraka
>
>


-- 
--------------
thompson@eecis.udel.edu				University of Delaware
Tyrone Thompson					EE Graduate Student

Article: 18182
Subject: Xilinx post route simulation
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 06 Oct 1999 00:09:00 +0100
Links: << >>  << T >>  << A >>
Has anybody manged to get post route simulation to work using Xilinx's
Verilog
simprim libraries ?

As far as I can tell the M1.5i LUT models are broken at least as far as
ModelSim is concerned. I've had to fix both these and, to get
compatibility with Synplify synthesis , the sync set/reset FF model as
well. There are also compatibility problems between the timing checks in
the sync. RAM models and the way SDF backannotation is done.


Article: 18183
Subject: Re: Producing 60/40 clock in vhdl
From: Ray Andraka <randraka@ids.net>
Date: Tue, 05 Oct 1999 21:24:55 -0400
Links: << >>  << T >>  << A >>
I recommend doing your first FPGA projects in schematics rather than VHDL for the
simple reason that schematics don't insulate you from the device architecture.
Once you become familiar with what works and doesn't work, then you can move on to
trying to get VHDL to produce the circuit and layout you now know is the best.
Yes, it can be done with VHDL, but with something like this, I think you'll find
that placement is critical to the success.  Doing placement within VHDL is not
much fun and is not well documented.



Tyrone Thompson wrote:

> I will give this a try. Is there some information on how to do this in VHDL
> somewhere? I haven't seen in the documentation. In case it's not obvious yet
> this is my first real project with FPGA's and VHDL.
>
> Tyrone
>
> In article <37F7F87E.186502C3@ids.net>, Ray Andraka  <randraka@ids.net> wrote:
> >Presumably, the reference clock is stable as is the device parameters
> >that affect the
> >delay.   If the output ratio is constant, then I would expect the delay
> >to try to stay
> >at one point until the temperature, voltage or reference change.  That
> >point may be (is
> >probably) between two of the taps in the delay line, but since the exact
> >duty cycle is
> >probably not critical you could set it up with enough filtering
> >(basically hysterisis)
> >to keep it from jumping back and forth.  Basically, the DLL picks the
> >tap in a delay
> >line that is closest to the delay that give the desired output.  The
> >finer the delay
> >increment the less the size of the jump (which is why I was suggesting
> >the carry logic
> >might make a good tapped delay line).
> >
> >Alvin E. Toda wrote:
> >
> >> On Sun, 3 Oct 1999, Ray Andraka wrote:
> >>
> >> > Depending on delays in FPGAs is generally a bad practice, as the
> >design becomes
> >> > very sensitive to routing, as well as to process improvements.  You
> >might be able
> >> > to reliably use the FPGA circuit delays by constructing a delay lock
> >loop in the
> >> > FPGA logic.  It uses feedback to adjust how many delay elements are
> >in the signal.
> >> > You could probably use the carry chain as the delay line, as it has
> >relatively
> >> > short and consistent delays for each "tap".  You will have to be
> >careful about the
> >> > routing off the taps though. I haven't tried this to see how well it
> >works, but at
> >> > 25 MHz, you might be able to pull it off.
> >>
> >> It would seem that another consideration would be the amount of
> >> jitter on the clock edge that could be tolerated, since it would
> >> seems that switching between taps would produce such behavior.
> >> Perhaps since the clocking is only needed for a special device,
> >> that specific asynchronous logic be designed so that the sequencing
> >> of signals is always correct and IAW whatever signals come
> >> back from the device.
> >>
> >> --al toda
> >>
> >> ###########################################################
> >> Alvin E. Toda              aet@lava.net
> >> sr. engineer               Phone: 1-808-455-1331
> >> 2-Sigma          WEB: http://www.lava.net/~aet/2-sigma.html
> >> 1363-A Hoowali St.
> >> Pearl City, Hawaii, USA
> >
> >
> >
> >--
> >-Ray Andraka, P.E.
> >President, the Andraka Consulting Group, Inc.
> >401/884-7930     Fax 401/884-7950
> >email randraka@ids.net
> >http://users.ids.net/~randraka
> >
> >
>
> --
> --------------
> thompson@eecis.udel.edu                         University of Delaware
> Tyrone Thompson                                 EE Graduate Student



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18184
Subject: Altera 10K50V in-rush/temp problem...
From: "Dave Krueger" <dave@kruegerphoto.com>
Date: Tue, 5 Oct 1999 20:50:00 -0500
Links: << >>  << T >>  << A >>
We are using an Altera 10K50V and have noticed that, at power up, it will
sometimes suck as much as 600mA off the 3.3V supply.  Warming the part will
make the inrush problem disappear, while cooling the part makes the problem
happen every time.

Our on-board supply is good for about 500mA and, looking at the ramp up of
the 3.3V, it is clearly being limited to a 1.2V level even as the current
increases.  A more powerful lab supply overcomes the current problem and the
current will suddenly drop to normal (about 20mA) allowing the 3.3V to climb
to it's full value.

Note that the Altera part is the only thing powered by the 3.3V supply and
this occurs before any attempt at programming the part.  The 3.3V is derived
from the on-baord 5V supply through a three-terminal regulator.

This problem seems to be worse with some date codes and other date codes
don't show the problem at all.

I'd be very grateful to hear from anyone who has experienced this problem.

-Dave Krueger
----------------------------------------------------------
WEB: http://www.kruegerphoto.com
MAIL:  dave@kruegerphoto.com


Article: 18185
Subject: Re: Multiplierless FIR filters in FPGAs
From: Ray Andraka <randraka@ids.net>
Date: Tue, 05 Oct 1999 22:11:33 -0400
Links: << >>  << T >>  << A >>
While you are looking at multiplierless filters, you might also look
carefully at the distributed arithmetic approach.  I've done some
sizeable and fast filters using this technique.  Some benchmarks:

a 1024 tap FIR filter with 12 bit inputs and 12 bit coefficients will
fit in a Xilinx XCV600 (virtex) and will run at 12 MS/S in a -4 part or
15.5 MS/S in a -6 using serial distributed arithmetic.

a 32 tap SDA FIR filter with 12 bit coefficients can fit inside a 10x10
CLB (virtex) area.

a 32 tap FIR filter with 12 bit inputs and 12 bit coefficients using
parallel distributed arithmetic will run at 140 MS/S in a Virtex
XCV300-4 or at around 180 MS/S in a -6 speed grade.

The advantages of the DA filters are 1) data rate is relatively
independent of the number of taps, 2) serial implementations can reduce
the size of the hardware considerably for data rates below 10-15 MHz, 3)
Conventional filter design programs can be used to generate the
coefficients.

Dave Decker wrote:

> On Tue, 05 Oct 1999 13:01:38 GMT, flavioas@my-deja.com wrote:
>
> >
> >
> >    Hi,
> >
> >    We are looking for some papers on how to
> >implement multiplierless filter structures in
> >FPGAs. Papers like "Design of multiplierless
> >digital data transmission filters with
> >powers-of-two coefficients" H. Samueli. and others
> >talking about "CSD coefficients" will be helpfull.
> >Can any one help?
> >   We are trying to subscribe to this newsgroup,
> >using outlook express to connect to the server :
> >nntp-serv.cl.cam.ac.uk, and getting the message:
> >"you have no permission to talk to this server".
> >So, How to subscribe?
> >
> >     Thanks in advance,
> >
> >     Flávio Andrade
> >
> >
> >Sent via Deja.com http://www.deja.com/
> >Before you buy.
>
> There are some interesting papers at the U of K. on automatic filter
> generation using sparce numbers of ones in the coefficients to
> minimize the size of the constant multipliers.
> try:
> ftp://ftp.tisl.ukans.edu/pub/projects/DSP/FPGA/Filters_and_CAD.pdf
>
> for one.
>
> Dave Decker



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18186
Subject: Re: Xilinx post route simulation
From: "Austin Franklin" <austin@darkroom77.com>
Date: 6 Oct 1999 03:56:24 GMT
Links: << >>  << T >>  << A >>
> Has anybody manged to get post route simulation to work using Xilinx's

Why do you want to do a post route simulation?

Why not just do a functional (unit delay) simulation and then make your
static timing when routing the design?

Article: 18187
Subject: Re: ATM srambler
From: rseglie@my-deja.com
Date: Wed, 06 Oct 1999 07:05:55 GMT
Links: << >>  << T >>  << A >>
In article <37F8A4B9.8196E368@ids.net>,
  Ray Andraka <randraka@ids.net> wrote:
> Actually, the output can be taken from after any register.  The output
from
> any register is just a copy of the input to the first register delayed
by a
> number of clocks.
>
> rseglie@my-deja.com wrote:
>
> > Tank you for your help
> >
> > Norm is for "standard" (sometimes I forget my basic english).
> >
> > I solve the problem on friday. The polynom is ok, I've done a
mistake
> > about where to get the output.
> >
> > A few answers to your email :
> > About degree : I start from 0 (d0 for Q0) so there's, of course, 43
> > registers.
> > The + means xor.
> >
> > Standards always show serial scrambler so I thought that it's easier
to
> > talk about them.
> > In my FPGA, I transform the "serie" version in 8 bits parallel
"version"
> > , looking the content of all registers after 8 clock cycles. Of
course
> > you can use this method for 16 bits version.
> >
> > My mistake was to take the output after the register but it must be
> > taken before ! (when I wrote this message I have any idea and I
thought
> > the diagram was wrong).
> > I test it and it's ok !!
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
>
>
I thought too that I can take the output from any register (and it's
better to take output after register rather after combinational
logic) but it wasn't work !
In fact I think that because scrambling it's only for the payload (48
last bytes of the 53) of the ATM cell (the scrambler is stop during the
first 5 bytes), the payload was shift of one bit and the PSA don't
pass...
I think there's no problem of taking output after registers for
scramblers won't stop or for device won't worked with scrambling data
and non scrambling at the same time.
Greeting.



Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18188
Subject: I/O Interface for Xilinx FPGA
From: Tomasz Pinkiewicz <tomaszp@postoffice.newham.utas.edu.au>
Date: Wed, 06 Oct 1999 07:26:27 GMT
Links: << >>  << T >>  << A >>
Hi!

I'm desinging a 32-bit ALU on a FPGA (XC4010) using Foundation Series.
It has a 32-bit control word and 32-bit data word. What I'm trying to do
is to send these commands via 8-bit parallel port. Could you help me how
to design a ciruit that will accept four 8-bit words (the control word),
followed by four 8-bit words(input or output data) going the the ALU or
from the ALU. This is part of my Honours thesis and I'm running out of
time and the solutions I have so far are not very advanced and probably
not working. Have you got any material (schematics) that I could use. I
would be greatful if you could help me.

I'm using Xilinx Foundation Series and implementation is on XC4010E.

Article: 18189
Subject: 1ST IEEE LATIN-AMERICAN TEST WORKSHOP
From: Eduardo Augusto Bezerra <E.A.Bezerra@sussex.ac.uk>
Date: Wed, 06 Oct 1999 10:15:47 +0100
Links: << >>  << T >>  << A >>

For those working with test procedures for FPGAs and fault-tolerant
FPGA systems:

           *****************************************************
                  1ST IEEE LATIN-AMERICAN TEST WORKSHOP

               Marina Palace Hotel, Rio de Janeiro, Brazil
                           March 13 - 15, 2000
           *****************************************************
 
                             CALL FOR PAPERS

The 1st IEEE Latin-American Test Workshop provides a forum for
specialists 
from all over the world, especially from Latin America, to present and 
discuss various aspects of system, board, and component testing with
design, 
manufacturing and field considerations in mind. The best papers of the 
workshop will be invited to re-submit to a special issue of the Journal
of 
Electronic Testing: Theory and Applications, published by Kluwer. 


*** TOPICS OF INTEREST INCLUDE, BUT ARE NOT LIMITED TO:
- Analog Mixed Signal Test            - Fault-Tolerant Systems
Applications
- Autom. Test Gen./Fault Simulation   - IDDQ Test
- Built-In Self-Test                  - On-Line Testing
- Defect & Failure Analysis           - Process Characterization,
Reliability
- Dependability Estimation            - Process Control and Measurement
- Distributed Fault-Tolerant Systems  - Simulation and Design
Verification
- E-Beam Testing and Thermal Testing  - SW Testing/SW Design for Test
- Economics of Test                   - Synthesis for Testability/DFT
- Fault Modeling & Diagnosis          - System-on-Chip Test
- Fault-Tolerance in HW/SW            - Yield Learning and Enhancement
- Fault-Tolerant Architectures


*** PAPER SUBMISSION INFORMATION:
To encourage and facilitate informal discussions participation will be 
limited. Those interested in presenting recent results at the workshop 
please submit four copies of an extended abstract, one to three pages 
long, or full length paper to one of the Program Chairs below:

Victor Champac                        Marcelo Soares Lubaszewski   
Inst. Nacional de Astrofisica,        Univ. Federal do Rio Grande do Sul
Optica y Electronica (INAOE)          Departamento de Engenharia
Eletrica   
Apdo. Postal 51 y 216                 Av. Osvaldo Aranha- Sar. Leite,
103
Puebla, 72000 Mexico                  Porto Alegre, 90035-190 Brazil
champac@inaoep.mx                     luba@iee.ufrgs.br

Authors should include the complete address, phone/fax numbers and
e-mail 
address, and designate a contact person and a presenter. The Program
Committee also welcome proposals for panels and special topic sessions.
Alternatively, it is strongly encouraged Post-Script or PDF electronic 
submissions via the workshop web page:

                 www.epo.pucrs.br/~la-tttc/latw00.html

*** SUBMISSION DEADLINE:        November 15th, 1999.  
*** NOTIFICATION OF ACCEPTANCE: December 30th, 1999.

*** SPONSORED BY:
IEEE Computer Society Test Technology Technical Council (TTTC)

*** IN COOPERATION WITH: Brazilian Computer Society (SBC),   
                         Brazilian Microelectronics Society (SBMicro)
                         Catholic University (PUCRS),   
                         Federal Brazilian Research Agencies CNPq-CAPES
                         Federal University of RGS (UFRGS),   
                         Federal University of Rio de Janeiro (UFRJ)

GENERAL CHAIRS:
    Fabian Vargas,  PUCRS - Brazil,     vargas@computer.org
    Yervant Zorian, LogicVision - USA,  y.zorian@computer.org

PROGRAM CHAIRS:
    Victor Champac, INAOE - Mexico
    Marcelo S. Lubaszewski, UFRGS - Brazil

PUBLICITY CHAIRS:
    Bernard Courtois, TIMA/INPG - France
    Ingrid Jansch-Porto, UFRGS - Brazil

LOCAL ARRANGEMENTS CHAIR:
    Vladimir Castro Alves, UFRJ - Brazil

BRAZILIAN COMPUTER SOCIETY LIAISON:
    Ingrid Jansch-Porto, UFRGS - Brazil

BRAZILIAN MICROELECTRONICS SOCIETY LIAISON:
    Wilhelmus Van Noije, USP - Brazil

EUROPE LIAISON:
    J. Paulo Teixeira, INESC/IST - Portugal

ASIA LIAISON:
    Kozo Kinoshita, Osaka Univ. - Japan

NOTRH AMERICA LIAISON:
    Alex Orailoglu, UC San Diego - USA

PROGRAM COMMITTEE:

J. Abraham - U. of Texas at Austin, USA
V. D. Agrawal - Lucent Tech., USA
E. Barros - UFPE, Brazil
B. Bennetts - Bennetts Assoc., England
E. A. Bezerra - PUCRS, Brazil
A. M. Brochi - TELEBRAS, Brazil
O. Calvo - UNLP, Argentina
H. Castro - UFC, Brazil
S. Demidenko - Singapore P., Singapore
R. Duarte - UFMG, Brazil
G. Espinosa - INAOE, Mexico
A. O. Fernandes - UFMG, Brazil
J. Figueras - UPC, Spain
J. L. Huertas - U. of Sevilla, Spain
A. Ivanov - UB Columbia, Canada
B. Kaminska - OPMAXX, USA
J. A. Martino - FEI/FCA-LSI/USP, Brazil
E. Martins - UNICAMP, Brazil
M. Marzouki - LIP6 Lab., France
P. C. Maxwell - Hewlett Packard, USA
J. V. Medina - UDV, Colombia
M. Nicolaidis - TIMA/INPG, France
A. R. Paula Jr. - UNIVAP, Brazil
D. Pradhan - Texas A&M U., USA
P. Prinetto - Politec. di Torino, Italy
E. Randon - USB, Venezuela
M. Renovell - LIRMM, France
A. J. L. Ribeiro - TELEBRAS, Brazil
J. M. Santos - FEUP, Portugal
M. Sarmiento - INAOE, Mexico
M. Strum - USP, Brazil
L. E. Toledo - UCC, Argentina
R. Velazco - TIMA/INPG, France
T. W. Williams - Synopsys Inc., USA
H. J. Wunderlich - U. Stuttgart, Germany

*****************************************************************
*****************************************************************

Fabian Vargas
LA-TTTC Chair

___________________________
Catholic University - PUCRS
Electrical Engineering Dept.     Email: vargas@computer.org
Av. Ipiranga, 6681               Phone: +55 51 320.3540
90619-900 Porto Alegre           FAX:   +55 51 320.3625
Brazil
Article: 18190
Subject: Re: Xilinx post route simulation
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Wed, 06 Oct 1999 15:29:35 +0300
Links: << >>  << T >>  << A >>

Rick Filipkiewicz wrote:

> Has anybody manged to get post route simulation to work using Xilinx's
> Verilog
> simprim libraries ?
>
> As far as I can tell the M1.5i LUT models are broken at least as far as
> ModelSim is concerned. I've had to fix both these and, to get
> compatibility with Synplify synthesis , the sync set/reset FF model as
> well. There are also compatibility problems between the timing checks in
> the sync. RAM models and the way SDF backannotation is done.

 Hi,

 Simulator: Verilog-XL 2.6.36
 My Synthesis tool: Synplify v5.21
 My P&R tool: Design Manager M1.5

 I am using $XILINX/verilog/data for postsynthesis simulations and
 $XILINX/verilog/src/simprims for postlayout (or post-route, according to your
 terminology) simulations. This is the recommended method by Xilinx. You
 can find this information at http://support.xilinx.com software manuals.
 We have not observed any incompatibility between the gate-level and
 postlayout-level. The only timing violations occur during reset insertion
 but not any abnormal difference observed between RTL (synthesizable)
 model and postlayout model. Target is XC40150XV.

 I think Austin is completely right since the postlayout simulations are
 aggressively long. For example our minimal 20 ms. postlayout simulation
 lasts 38 hours on a Sun Ultra-10/256MB/300 MHz UltraSPARC. Static
 Timing Analyzer TRACE can give practicaly faster results. Despite that
 we perform postlayout simulations.

 Utku

--
I feel better than James Brown.





Article: 18191
Subject: Re: ATM srambler
From: Ray Andraka <randraka@ids.net>
Date: Wed, 06 Oct 1999 10:03:43 -0400
Links: << >>  << T >>  << A >>
You need to match the delays for the scrambled and non-scrambled paths.
Don't put the not-to-be scrambled data into the shift register at all (in
other words, don't turn off the scrambling by breaking the feedback path,
that will break it).  It will work if the delays are matched and you don't
upset the contents of the shift register while passing non-scrambled data.

rseglie@my-deja.com wrote:

> In article <37F8A4B9.8196E368@ids.net>,
>   Ray Andraka <randraka@ids.net> wrote:
> > Actually, the output can be taken from after any register.  The output
> from
> > any register is just a copy of the input to the first register delayed
> by a
> > number of clocks.
> >
> > rseglie@my-deja.com wrote:
> >
> > > Tank you for your help
> > >
> > > Norm is for "standard" (sometimes I forget my basic english).
> > >
> > > I solve the problem on friday. The polynom is ok, I've done a
> mistake
> > > about where to get the output.
> > >
> > > A few answers to your email :
> > > About degree : I start from 0 (d0 for Q0) so there's, of course, 43
> > > registers.
> > > The + means xor.
> > >
> > > Standards always show serial scrambler so I thought that it's easier
> to
> > > talk about them.
> > > In my FPGA, I transform the "serie" version in 8 bits parallel
> "version"
> > > , looking the content of all registers after 8 clock cycles. Of
> course
> > > you can use this method for 16 bits version.
> > >
> > > My mistake was to take the output after the register but it must be
> > > taken before ! (when I wrote this message I have any idea and I
> thought
> > > the diagram was wrong).
> > > I test it and it's ok !!
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email randraka@ids.net
> > http://users.ids.net/~randraka
> >
> >
> I thought too that I can take the output from any register (and it's
> better to take output after register rather after combinational
> logic) but it wasn't work !
> In fact I think that because scrambling it's only for the payload (48
> last bytes of the 53) of the ATM cell (the scrambler is stop during the
> first 5 bytes), the payload was shift of one bit and the PSA don't
> pass...
> I think there's no problem of taking output after registers for
> scramblers won't stop or for device won't worked with scrambling data
> and non scrambling at the same time.
> Greeting.
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18192
Subject: Re: Xilinx post route simulation
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 06 Oct 1999 15:47:21 +0100
Links: << >>  << T >>  << A >>


Utku Ozcan wrote:

> Rick Filipkiewicz wrote:
>
> > Has anybody manged to get post route simulation to work using Xilinx's
> > Verilog
> > simprim libraries ?
> >
> > As far as I can tell the M1.5i LUT models are broken at least as far as
> > ModelSim is concerned. I've had to fix both these and, to get
> > compatibility with Synplify synthesis , the sync set/reset FF model as
> > well. There are also compatibility problems between the timing checks in
> > the sync. RAM models and the way SDF backannotation is done.
>
>  Hi,
>
>  Simulator: Verilog-XL 2.6.36
>  My Synthesis tool: Synplify v5.21
>  My P&R tool: Design Manager M1.5
>
>  I am using $XILINX/verilog/data for postsynthesis simulations and
>  $XILINX/verilog/src/simprims for postlayout (or post-route, according to your
>  terminology) simulations. This is the recommended method by Xilinx. You
>  can find this information at http://support.xilinx.com software manuals.
>  We have not observed any incompatibility between the gate-level and
>  postlayout-level. The only timing violations occur during reset insertion
>  but not any abnormal difference observed between RTL (synthesizable)
>  model and postlayout model. Target is XC40150XV.
>
>  I think Austin is completely right since the postlayout simulations are
>  aggressively long. For example our minimal 20 ms. postlayout simulation
>  lasts 38 hours on a Sun Ultra-10/256MB/300 MHz UltraSPARC. Static
>  Timing Analyzer TRACE can give practicaly faster results. Despite that
>  we perform postlayout simulations.
>
>  Utku
>
> --
> I feel better than James Brown.

Yes in general I agree with this argument BUT the M1.5 s/w was sufficiently buggy
both at the place and route and timing analysis levels for the Virtex parts that
post route, or at least, post MAP simulation was essential. For example post
synthesis simulation would not have found the wonderful MAP bug that silently
threw away any inverter after a output FF that was placed in an IOB. This meant
that my initial build had all the DRAM control signals inverted. The same bug
affected TriFFs and also inverters placed before InFFs, so that the PCI output
enables were also upside down.

In terms of the simprims I'm not surpised they work for you since the models say
something like:

// Applicable version Verilog-XL 1.6c.5 (??)

but at least the LUT ones do not work on ModelSim [Sorry about the obvious signs
of poverty here but $60K for XL was a bit more than we could afford]. An example
of the problem lies in the LUT2 simprim statement [approx]

assign out = INIT[{a1,a0}]

If the LUT is configured as an and gate with INIT = 4'b1000 and a1, a0 = 2'b0x
then the output is `x' instead of `0'.
What does XL produce under these conditions ?

There is another problem caused by incompatibility between the sync set/reset
model in UNIVIRTEX libs and
the one in the simprims lib. This means that post-synth & post-route simulations
can
differ.

Maybe this has all been fixed up in Synplify 5.1.5a+ & M2.1i. If so it has been
done very silently.



Article: 18193
Subject: Re: Altera 10K50V in-rush/temp problem...
From: jjlarkin <jjlarkin_99NOjjSPAM@yahoo.com.invalid>
Date: Wed, 06 Oct 1999 11:53:04 -0700
Links: << >>  << T >>  << A >>
Dave,

I don't use this part, but I've seen lots of CMOS parts go into SCR
latchup mode on powerup if any of their input protection diodes are
foreward-biased. This happens if any i/o pin is pulled below ground or
above Vcc. 'Above Vcc' can happen if the fpga is being driven by
incoming logic inputs that pull up before the fpga supply is up.

John

ps - nice photos.


* Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
The fastest and easiest way to search and participate in Usenet - Free!

Article: 18194
Subject: will Xlilnx jtag cable work with as a replacement for Altara's BitBlaster
From: "colin cook" <colin@intel.com>
Date: Wed, 6 Oct 1999 14:00:24 -0600
Links: << >>  << T >>  << A >>
I already have the Xilinx JTAG cable and was wondering if anyone knows if I
can use it from MAX+Plus II.
I think The BitBlaster Cable is supposed to be a JTAG cable.

CC :)



Article: 18195
Subject: Re: Xilinx post route simulation
From: Paulo Dutra <paulo@xilinx.com>
Date: Wed, 06 Oct 1999 14:05:31 -0700
Links: << >>  << T >>  << A >>

> In terms of the simprims I'm not surpised they work for you since the models say
> something like:
> 
> // Applicable version Verilog-XL 1.6c.5 (??)

In 2.1i, the Verilog models are tested/sqa against the defined
supported simulators at the time.  Verilog-XL 2.7.5, Modelsim 5.2, and
VCS 5.0.  The above comment is no longer listed in the model
header files.

> but at least the LUT ones do not work on ModelSim [Sorry about the obvious signs
> of poverty here but $60K for XL was a bit more than we could afford]. An example
> of the problem lies in the LUT2 simprim statement [approx]
> 
> assign out = INIT[{a1,a0}]
> 
> If the LUT is configured as an and gate with INIT = 4'b1000 and a1, a0 = 2'b0x
> then the output is `x' instead of `0'.
> What does XL produce under these conditions ?

This is fixed in 2.1i.  All bugs fixed in 2.1i, were documented in a solution
record. There was no silence involved.

http://www.xilinx.com/techdocs/5270.htm
http://www.xilinx.com/techdocs/5262.htm

> There is another problem caused by incompatibility between the sync set/reset
> model in UNIVIRTEX libs and
> the one in the simprims lib. This means that post-synth & post-route simulations
> can
> differ.


What type incompatibilty?
-- 
Paulo                                      //\\\\ 
                                           | ~ ~ |
                                          (  O O  )
 __________________________________oOOo______( )_____oOOo_______
|                                             .                 |
| / 7\'7 Paulo Dutra (paulo@xilinx.com)                         |
| \ \ `  Xilinx                              hotline@xilinx.com |
| / /    2100 Logic Drive                    (800) 255-7778     |  
| \_\/.\ San Jose, California 95124-3450 USA                    | 
|                                                  Oooo         |
|________________________________________oooO______(  )_________|
                                         (  )       ) /
                                          \ (      (_/
                                           \_)
Article: 18196
Subject: HOT II PCI Development System
From: Roger Yau <rogeryau@casilrd.com.hk>
Date: Thu, 07 Oct 1999 11:16:31 +0800
Links: << >>  << T >>  << A >>
Hi,
Any one tried to order the HOT II Development System from
Virtual Computer Corporation ( www.vcc.com )? How long
is need for waiting the PCI core netlist file from them after you
sign the LogiCORE "PCI Master and Slave interface" License
Agreement and fax it back? I had fax it back to Xilinx/VCC at
27/09/1999 but seem that isn't any response from them up to
now (06/10/1999). Is there any problems?

Roger Yau
rogeryau@casilrd.com.hk
CASIL R&D Co., Ltd.


Article: 18197
Subject: Re: Xilinx post route simulation
From: "Austin Franklin" <austin@darkroo9m.com>
Date: 7 Oct 1999 03:23:02 GMT
Links: << >>  << T >>  << A >>
> Yes in general I agree with this argument BUT the M1.5 s/w was
sufficiently buggy
> both at the place and route and timing analysis levels for the Virtex
parts that
> post route, or at least, post MAP simulation was essential. 

I believe you can still do unit delay simulation post route...  I
understand your (er, or at least the Xilinx) problem ;-)

Article: 18198
Subject: Virtex and PCI 5V?
From: wq998@yahoo.com
Date: Thu, 07 Oct 1999 05:15:05 GMT
Links: << >>  << T >>  << A >>
Xilinx claims that Virtex is compliant with PCI 5V.
Virtex is 3.3V IO, without 5V clamping diodes on its IO pins, which is
required by PCI Spec.
Somebody comment it?


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18199
Subject: Re: Altera 10K50V in-rush/temp problem...
From: "Dave Krueger" <dave@kruegerphoto.com>
Date: Thu, 7 Oct 1999 06:05:26 -0500
Links: << >>  << T >>  << A >>
John,

Thanks for your response, but I don't think this is quite the same.  The
problem persists even when the FPGA is the only part with power applied.
Since it's the only device powered by 3.3V (the rest of the board is 5VB),
it was a simple matter to power just the FPGA and leave the 5V shut down.
Since the FPGA I/O isn't being driven by other circuits, I don't see how it
could be a latchup issue.

The limiting effect at 1.2V does seem like some kind of  "zernering" effect,
though.

-Dave




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search