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Messages from 18200

Article: 18200
Subject: External Cloking of Altera MAX 7000S
From: "Moussa A. Ba" <babs@eng.umd.edu>
Date: Thu, 07 Oct 1999 07:26:04 -0400
Links: << >>  << T >>  << A >>
Good day, I am very new to FPGA design so excuse my ignorance.  I just
finished simulating my first FPGA design.  The simulated is based on a
4Mhz clock.  After burning the circuit on the chip and supplying my
external clock through a 4 Mhz crystal, the clock gets totally messed up
as soon as it is connected to the fpga clock input, am I suffering from
loading problem?  Is there any other way to provide a reliable clock to
the system.  By the way, the board I am using is the UP1 board
university program.
Thank you in advance



Article: 18201
Subject: Re: Multiplierless FIR filters in FPGAs
From: flavioas@my-deja.com
Date: Thu, 07 Oct 1999 12:16:28 GMT
Links: << >>  << T >>  << A >>


    Hi people,

    I found very interesting things, with your answers. Thanks to you
all.
    I got good articles from ftp.ukans.edu, but could not find the URL
www.ukans/projects/fpga, Doug this time was not there to redirect me :)
    About multiplierless FIR I have the following references, but not
the material yet.
  1)  H.Samueli "The design of multiplierless digital data transmission
filters with powers-of-two coefficients" in Proc. SBT/IEEE Int.
Telecomm. Symp., Sept 1990, pp 425-429
  2)  Q.Zhao and Y.Tadokoro "A simple design of FIR filters with
powers-of-two coefficients" IEEE Trans. Circuits Syst. vol 35, pp
566-570, May 1988
  3)  K.Hwang "Computer Arithmetic, Principles, Architecture and Design"
New York:Wiley,1979.

     Ray, your benchmarks sounds good to me, now I´m looking for
articles on distributed arithmetic too.
     But I couldn´t find a news server, like bbs.circuitcellar, to
subscribe comp.arch.fpga.

     Regards,

     Flávio



In article <37f9c1fb.431859@news.slip.net>,
  mush@slip.net (Dave Decker) wrote:
> On Tue, 05 Oct 1999 13:01:38 GMT, flavioas@my-deja.com wrote:
>
> >
> >
> >    Hi,
> >
> >    We are looking for some papers on how to
> >implement multiplierless filter structures in
> >FPGAs. Papers like "Design of multiplierless
> >digital data transmission filters with
> >powers-of-two coefficients" H. Samueli. and others
> >talking about "CSD coefficients" will be helpfull.
> >Can any one help?
> >   We are trying to subscribe to this newsgroup,
> >using outlook express to connect to the server :
> >nntp-serv.cl.cam.ac.uk, and getting the message:
> >"you have no permission to talk to this server".
> >So, How to subscribe?
> >
> >     Thanks in advance,
> >
> >     Flávio Andrade
> >
> >
> >Sent via Deja.com http://www.deja.com/
> >Before you buy.
>
> There are some interesting papers at the U of K. on automatic filter
> generation using sparce numbers of ones in the coefficients to
> minimize the size of the constant multipliers.
> try:
> ftp://ftp.tisl.ukans.edu/pub/projects/DSP/FPGA/Filters_and_CAD.pdf
>
> for one.
>
> Dave Decker
>


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Before you buy.
Article: 18202
Subject: Re: Altera 10K50V in-rush/temp problem...
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Thu, 07 Oct 1999 13:31:36 GMT
Links: << >>  << T >>  << A >>
On Thu, 7 Oct 1999 06:05:26 -0500, "Dave Krueger"
<dave@kruegerphoto.com> wrote:

>John,
>
>Thanks for your response, but I don't think this is quite the same.  The
>problem persists even when the FPGA is the only part with power applied.
>Since it's the only device powered by 3.3V (the rest of the board is 5VB),
>it was a simple matter to power just the FPGA and leave the 5V shut down.
>Since the FPGA I/O isn't being driven by other circuits, I don't see how it
>could be a latchup issue.
>
>The limiting effect at 1.2V does seem like some kind of  "zernering" effect,
>though.

The 10K50V parts have multiple supply rails?  (I'm guessing - I've
never used a 10k50V).

If these supply inputs aren't sequenced correctly, the chip might
latch up, regardless of what's connected to the I/O.

Check that all supply pins are reliably connected to the same plane.
Check that all ground pins are reliably connected to the same plane.

I've seen other parts (from Motorola, not FPGAs) that would latch up
when an analog VCC and digital VCC didn't track within a few hundred
mV, even though the datasheet said that there was no need for
sequencing.  The fault only happened at low temperatures (< 0 degrees
C).
We connected the rails together and didn't have any more problems.

When Motorola were queried, they said there was no requirement for
sequencing.  They probably still believe it.

Allan.
Article: 18203
Subject: Re: External Cloking of Altera MAX 7000S
From: Brad Ree <brad.ree@programmable-products.com>
Date: Thu, 07 Oct 1999 09:45:47 -0400
Links: << >>  << T >>  << A >>
Not to be picky, but the 7000 family is not an FPGA.  This device is
actually an EPLD (Altera terms) or CPLD(Xilinx terms).  The reason for this
is that this device has a PLD structure, which is the AND/OR array feeding
into registers.

These EPLDs and FPGAs can not work with a crystal as the clock source.  You
should use an oscillator for the clock.  I am not familiar with the UP1
board, but would expect that there would be a location for an oscillator.

"Moussa A. Ba" wrote:

> Good day, I am very new to FPGA design so excuse my ignorance.  I just
> finished simulating my first FPGA design.  The simulated is based on a
> 4Mhz clock.  After burning the circuit on the chip and supplying my
> external clock through a 4 Mhz crystal, the clock gets totally messed up
> as soon as it is connected to the fpga clock input, am I suffering from
> loading problem?  Is there any other way to provide a reliable clock to
> the system.  By the way, the board I am using is the UP1 board
> university program.
> Thank you in advance

Article: 18204
Subject: Free SPARC VHDL model available
From: jgais@ws.estec.esa.nl
Date: Thu, 07 Oct 1999 14:07:47 GMT
Links: << >>  << T >>  << A >>
LEON-1 VHDL model

Background

The LEON core is a SPARC compatible integer unit developed at ESTEC. It
has been implemented as a highly configurable, synthesisable VHDL model.
To promote the SPARC standard and enable development of system-on-a-chip
(SOC) devices using SPARC cores, the full source code is made freely
available under the GNU GPL license.

Architecture

LEON-1 is a SPARC compatible processor targeted for embedded
applications. It features the following functions:

       LEON SPARC compatible integer unit
       separate instruction and data caches
       32-bit memory bus with EDAC, PROM and SRAM support
       interrupt controller,
       two  24-bit timers
       two UARTs
       16-bit I/O port
       write protection
       power-down function
       watchdog.

Synthesis

The VHDL model is fully synthesisable and contains synthesis scripts for
Synopsys-DC and Synplify. Targeting a 0.35 um CMOS process (gate-array
or std-cell), approximately 100 MHz can be reached with a gate count of
35 Kgates. The processor also fits in an Altera 10K200E FPGA, utilising
65% of the device and running at 15 MHz.

Simulation

The model comes with a generic testbench and test program, and includes
support files for the Modelsim simulator. It also features a built-in
disassembler for debug purposes.

Software tools

Currently, software for LEON can be developed by reusing the ERC32CCS
compiler for ERC32. However, no support exists for the LEON peripherals
(timers, UARTs) limiting the usability of the compiler. An adaptation of
ERC32CCS for LEON is in progress and will
be made available in Q1 2000.

Download

Documentation and VHDL source code can be obtained at:

http://www.estec.esa.nl/wsmwww/leon/


Jiri Gaisler
European Space Agency


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Before you buy.
Article: 18205
Subject: Re: DSP in FPGA
From: pmolson@my-deja.com
Date: Thu, 07 Oct 1999 16:06:16 GMT
Links: << >>  << T >>  << A >>
Hi Ray,

Altera has just released the FIR Compiler 1.1
which is a complete FIR design environment (HDL
and Matlab integration).

The key features of this tool are :
- Multirate Filter capabilities
(Interpolation/Decimation)
- Any number of taps
- Multiple architectures : Serial Parallel for
Apex or Flex.
- Floating Point Coefficient to Fixed Point
Coefficient scaling and analysis capabilities.

For more infos :
http://www.altera.com/html/tools/mc-fir.html

Hope this helps,

Philippe

In article <37E3BB2B.5A2E4170@ids.net>,
  Ray Andraka <randraka@ids.net> wrote:
>
>
> Cemal Coemert wrote:
>
> > Hi ,
> > some questions from a beginner.
> >
> > - did I have enough controll with VHDL to
implement High Speed Designs
> > (DSP)
> >    or should I use e.g Schematic entry ?
>
> VHDL does have the hooks to successfully pull
off high speed DSP designs,
> but it can involve a substantial amount of
"pushing on a rope" to get the
> tools to produce exactly what you want,
especially when you are doing
> floorplanning.  If you are starting out with
FPGAs I recommend starting
> with schematics until you are very comfortable
with the FPGA architecture
> and what circuit structures make for high
speeds.  VHDL intentionally hides
> the architectural details from the designer, so
it is very easy to turn out
> designs that fall short of the mark because
they fight the FPGA
> architecture rahter than play with it.  For
high speed designs, you will
> want to floorplan the design as well as tailor
your design to the FPGA
> architecture.
>
> >
> >
> > - the FPGA Vendors provide complete core
solutions like Filter,
> > Correlator, Transformer...
> >     Now, what is the challenge for me if I
have ready to use components
> > ?
>
> Most of the time, these cores either don't do
exactly what you want or are
> not optimized to your needs.  Many of the
available cores are ports from
> ASIC cores that have not really been optimized
to the FPGA architecture so
> they are bigger and slower than a design done
from the bottom up for a
> particular FPGA family.  Also, in DSP, there is
usually more than one way
> to skin the cat.  Often this involves modifying
a function to perhaps do
> two steps at once.  The CORES are generally
"closed" so you are stuck with
> what you get.  Hardware DSP design is more than
just glueing blocks
> together.  I've found that most of the time,
the algorithm given to me to
> implement is one that came from a software
solution.  More than likely, the
> port from software to hardware is not a one-to-
one. The relative costs of
> resources in each realm is different so the
best solution is also
> different.  A good hardware DSP designer has to
be prepared to dig into the
> algorithm to understand the motivation for the
approach presented, and then
> come up with alternate approaches to solving
the problem.
>
> > - which FPGA is "better" suited for DSP :
Xilinx - Atmel
> >
>
> DSP designs generally contain alot of
arithmetic, so you want a device with
> a capable carry chain.  That puts Atmel chips
at a considerable
> disadvantage for most serious DSP applications
(bit serial designs are an
> exception since the carry chain isn't needed
there).  The carry chain
> allows you to make very fast arithmetic
elements without resorting to area
> intensive speedups for the carry inherent in
artihmetic.A more viable
> alternative to Xilinx for DSP applications are
the Altera 10K and Apex
> families, as these parts do have carry chains.
I do prefer Xilinx 4K and
> Virtex over the Altera devices for DSP for
several reasons however:  first,
> the Altera carry logic reduces the LE cell to a
three input function, one
> of which is for the carry input.  THat means
that arithmetic functions are
> limited to two inputs if the logic is to stay
in a single level (desirable
> for speed)...accumulators with load or clear,
adder-subtractors etc need to
> use two levels of logic in Altera 10K, also the
clock enable uses one of
> the LUT inputs, so clock-enabled arithmetic has
only one input in Altera
> 10K. APEX improves the situation slightly by
adding dedicated clock enable
> and synchronous load/clear controls to the cell.
> DSP designs also typically require many delay
queues - filtering for
> example depends on delaying the signal.  The
xilinx 4K and virtex chips
> allow you to use the CLB as a delay queue or
shift register so you can
> delay a bit up to 16 clocks in one LUT (half a
4K CLB or half a virtex
> slice), leading to area efficient delays.
Altera does not have this
> capability, so delay queues have to be
constructed from the registers in
> the LE's (logic elements), which will quickly
eat up the logic resource for
> even modest word-wide delay queues.  Also,
altera's I/) cell can only be
> registered in one direction at a time, so
interfaces to high speed external
> memory or other bidirectional devices is
handicapped and can have timing
> that is sensitive to the place an route.
> Given the choice, I'll take the Xilinx over
Altera for DSP applications.
> Altera is still quite capable (and I've done a
number of those designs),
> but just not as capable as the Xilinx
architecture.  Most of the other
> players don't have carry chains, which for me
is a non-starter in DSP apps.
>
> > Greetinx, Cemal
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
>
>



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Before you buy.

Article: 18206
Subject: Re: Virtex and PCI 5V?
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 07 Oct 1999 09:39:12 -0700
Links: << >>  << T >>  << A >>


wq998@yahoo.com wrote:

> Xilinx claims that Virtex is compliant with PCI 5V.
> Virtex is 3.3V IO, without 5V clamping diodes on its IO pins, which is
> required by PCI Spec.
> Somebody comment it?
>

Last time I looked at the PCI specification,
5V PCI explicitly did NOT require a diode clamp to 5 V,
( 3V PCI, on the other hand, demands such a diode.)

Peter Alfke, Xilinx Applications

Article: 18207
Subject: Re: Multiplierless FIR filters in FPGAs
From: jjlarkin <jjlarkin_99NOjjSPAM@yahoo.com.invalid>
Date: Thu, 07 Oct 1999 09:49:44 -0700
Links: << >>  << T >>  << A >>
Hi,

we've done a 4-pole IIR almost-besel response lowpass filter using just
shifts and adds. It's coded in assembly for the 68K, but could be
easily converted to an FPGA. We didn't use a lot of theory: we just
designed an analog state-variable lowpass filter, simulated it in
software, and tweaked the shift coefficients until the response was
about right.

I can post the source if there's overwhelming demand...

John


,,,,jjlarkin,,,,at,,,,highlandtechnology,,,dot,,,com,,,email,,,address


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Article: 18208
Subject: FPGA ???
From: "TalentLab Inc." <jobs@talentlab.com>
Date: Thu, 07 Oct 1999 18:00:56 GMT
Links: << >>  << T >>  << A >>
Hi this is Stuart Musson and I am contacting you for two reasons, I would
like to inform you of our weekly e-letter on career tips and hot jobs, you
can subscribe at http://www.talentlab.com and I am also currently searching
for a Hardware Engineer for a client. I don’t know if you are someone that I
should be speaking with about this interesting opportunity but it is my hope
that you may be able to help me out in this search. Our client can offer a
friendly team-oriented environment, the opportunity to see your work go from
beginning to end and the opportunity to work on very intriguing products. I
have taken the liberty to attach the job description for your perusal, if
you are interested in this opportunity or if you know of anyone who is
currently looking to further their career.

Hardware Engineer

Core job

Design, develop, test and document (through to manufacturing sign-off)
digital hardware used in ground and airborne satellite communications
products and systems.  Typical boards incorporate embedded controllers,
FPGAs, TI or Analog Devices DSPs, miscellaneous peripherals and a host bus
interface.  Target systems include PCI and Compact PCI platforms.
May also be responsible for the hardware design of low-cost wireless
consumer products.

Core skills

digital circuit design
schematic and VHDL-based FPGA design
design-for-manufacture, design-for-test
EMI/EMC compliance
communications concepts (understanding of communications signal chain)

 Desirable skills

PCI / Compact PCI (including hot-swap)
avionics hardware design and familiarity with avionics standards (e.g.,
ARINC-429)
telephony interface design
analog hardware design (baseband)
RF (10 MHz to 450 MHz or beyond) hardware design
system design (requirements analysis/definition, architectural design,
interface specifications)
mobile satellite communications systems (e.g., Inmarsat, Globalstar)
modulation techniques
PC programming
Micro-controller programming
project management
documentation

To find out more about this position, I can be reached at the co-ordinates
below.

Stuart Musson
(613) 271-2342
stuartm@talentlab.com



Article: 18209
Subject: Re: External Cloking of Altera MAX 7000S
From: "Andy Peters" <apeters.nospam@nospam.noao.edu.nospam>
Date: Thu, 7 Oct 1999 12:47:43 -0700
Links: << >>  << T >>  << A >>
Moussa A. Ba wrote in message <37FC834C.E6B5FF55@eng.umd.edu>...
>Good day, I am very new to FPGA design so excuse my ignorance.  I just
>finished simulating my first FPGA design.  The simulated is based on a
>4Mhz clock.  After burning the circuit on the chip and supplying my
>external clock through a 4 Mhz crystal, the clock gets totally messed up
>as soon as it is connected to the fpga clock input, am I suffering from
>loading problem?  Is there any other way to provide a reliable clock to
>the system.  By the way, the board I am using is the UP1 board
>university program.

You can't use a crystal by itself, like you can on some microcontrollers.
Crystals do not have TTL (or CMOS) outputs.  You need to buffer it (the
common trick is to use unbuffered CMOS inverters; I forget the part number).
Save yourself some grief and buy a 4 MHz TTL-out oscillator.


-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Creation Science" is oxymoronic.



Article: 18210
Subject: Re: Multiplierless FIR filters in FPGAs
From: Ray Andraka <randraka@ids.net>
Date: Thu, 07 Oct 1999 16:44:51 -0400
Links: << >>  << T >>  << A >>
How many shifts and adds are in the feedback paths, especially the first order
feedbacks?  That delay path will determine the maximum sample rate in an FPGA
implementation, as it cannot be pipelined.

jjlarkin wrote:

> Hi,
>
> we've done a 4-pole IIR almost-besel response lowpass filter using just
> shifts and adds. It's coded in assembly for the 68K, but could be
> easily converted to an FPGA. We didn't use a lot of theory: we just
> designed an analog state-variable lowpass filter, simulated it in
> software, and tweaked the shift coefficients until the response was
> about right.
>
> I can post the source if there's overwhelming demand...
>
> John
>
> ,,,,jjlarkin,,,,at,,,,highlandtechnology,,,dot,,,com,,,email,,,address
>
> * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
> The fastest and easiest way to search and participate in Usenet - Free!



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18211
Subject: Token-Ring MAC in FPGA?
From: PJD <pjdecker@my-deja.com>
Date: Thu, 07 Oct 1999 21:30:41 GMT
Links: << >>  << T >>  << A >>
TI's TI380C30A Token-Ring MAC/PHY costs $56 (1k).
Their TI380C60A PHY costs $10 (1k).  Ergo, the MAC costs $46.

Can the MAC be synthezised in an FPGA for a lower recurring cost?
If so, what non-recurring costs are involved?
Are there any sources of Token Ring IP?
Which level of Viewlogic/Synopsis FPGA Express would be required for a
design of that size?

--
Philip Decker
Sarasota, Florida, USA


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Before you buy.
Article: 18212
Subject: Re: External Cloking of Altera MAX 7000S
From: Moussa Ba <babs@eng.umd.edu>
Date: Thu, 07 Oct 1999 18:23:01 -0400
Links: << >>  << T >>  << A >>
Thank you for your reply.  I forgot to mention in my email that I did use a TTL
crystal oscillator.  And I still get a messed up signal as soon as I connect the

clock to the clock input of the MAX chip.

P.S.:  I am an alumni of University of Arizona, currently in Maryland, how is
Tucson?


>
> You can't use a crystal by itself, like you can on some microcontrollers.
> Crystals do not have TTL (or CMOS) outputs.  You need to buffer it (the
> common trick is to use unbuffered CMOS inverters; I forget the part number).
> Save yourself some grief and buy a 4 MHz TTL-out oscillator.
>
> -- a
> -----------------------------------------
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) noao \dot\ edu
>
> "Creation Science" is oxymoronic.




Article: 18213
Subject: Re: Altera 10K50V in-rush/temp problem...
From: "Dave Krueger" <dave@kruegerphoto.com>
Date: Thu, 7 Oct 1999 19:59:32 -0500
Links: << >>  << T >>  << A >>
Thanks, guys.

Allan, we have both the I/O and internal VCC supplies connected to the same
3.3V supply, so it's not a sequencing problem.

I had a reply in e-mail that I think explains what's going on.  If, at power
up, the internal latches come up in some random state, there will be
contension on the INTERNAL busses that account for the excessive current on
the VCC.  The part apparently clears these latches, but only if the power
supply is capable of producing enough current to operate the part.  With
some lot codes and temperatures, it draws as much as 700 mA.  Our supply was
capable of about 500 mA.  After the latches are cleared, the current drops
to about 20 mA (big difference!).

Upon beefing up the supply, the parts still show the current spike, but the
device always comes out of it and the current drops to normal.

If this were a latch-up issue, the part would not recover like that.  That's
primarily why I referred to the problem as an "in-rush" problem rather than
a latch-up problem.

I appreciate all the responses.

-Dave


Article: 18214
Subject: Re: HOT II PCI Development System
From: Jim McManus <jim.mcmanus@xilinx.com>
Date: Thu, 07 Oct 1999 22:43:00 -0700
Links: << >>  << T >>  << A >>
Roger, the licensing is now done on-line. Go to
http://www.xilinx.com/pci and select the Overview and Registration link. 

Jim McManus
Xilinx PCI Applications Engineer

Roger Yau wrote:
> 
> Hi,
> Any one tried to order the HOT II Development System from
> Virtual Computer Corporation ( www.vcc.com )? How long
> is need for waiting the PCI core netlist file from them after you
> sign the LogiCORE "PCI Master and Slave interface" License
> Agreement and fax it back? I had fax it back to Xilinx/VCC at
> 27/09/1999 but seem that isn't any response from them up to
> now (06/10/1999). Is there any problems?
> 
> Roger Yau
> rogeryau@casilrd.com.hk
> CASIL R&D Co., Ltd.
Article: 18215
Subject: Re: Virtex and PCI 5V?
From: Jim McManus <jim.mcmanus@xilinx.com>
Date: Thu, 07 Oct 1999 23:07:02 -0700
Links: << >>  << T >>  << A >>
The required clamping for 5 V PCI is the lower clamp diode. This is a
standard feature for most CMOS devices. The upper clamp diode is
optional for 5 V PCI signaling environment.

From the V2.2 PCI Spec, page 120 (5 V signaling):
"Inputs are required to be clamped to ground. Clamps to the 5V rail are
optional, but may be needed to protect 3.3V input devices."

The PCI spec recommends it under the assumption that this is the best
way to protect a 3.3 V device against the up to 11 V overshoot of the 5
V PCI bus. 

From the PCI V2.2 Specification, page 114:
"While the primary goal of the PCI 5V to 3.3V transition strategy is to
spare vendors the burden and expense of implementing 3.3V parts that are
"5V tolerant," such parts are not excluded."

But Xilinx 3.3 V parts are 5 V PCI tolerant without an upper clamp
diode; the XLA, SpartanXL, and Virtex FPGA families are certified to
withstand this overshoot. In fact, we require you to turn off the upper
clamp diode when using this in a 5 V PCI system. We do not certify these
devices to take 11 V *DC*; only that they will withstand the 5 V PCI AC
specification. 


Jim McManus
Xilinx PCI Applications Engineer

wq998@yahoo.com wrote:
> 
> Xilinx claims that Virtex is compliant with PCI 5V.
> Virtex is 3.3V IO, without 5V clamping diodes on its IO pins, which is
> required by PCI Spec.
> Somebody comment it?
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.
Article: 18216
Subject: Re: What are the Virtex REV connections?
From: simon_bacon@my-deja.com
Date: Fri, 08 Oct 1999 07:30:13 GMT
Links: << >>  << T >>  << A >>
Thanks everyone.  In summary, unless PA disagrees,

  INIT gets you the INITialisation value of the FF.
  REV gets you the REVERSE of the initialisation value of the FF.

As Evan pointed out, this can be seen in FPGA Editor.  More
accurately, it can be seen with the eye of faith.

Simon


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Before you buy.

Article: 18217
Subject: UK or Europe Des. Engs for California jobs
From: "Anthony Quigley" <anthony.quigley@virgin.net>
Date: Fri, 8 Oct 1999 12:06:20 +0100
Links: << >>  << T >>  << A >>
Are you looking for a job in the sunshine?

Design Engineers, Senior Des Eng's, Lead Des Eng's, -  permanent positions
in California.
Relocation package available which includes Airfares, one month corporate
accommodation, one month car hire, full medical and dental cover, visa
costs, sponsorship for 'Green Card'

Lead Digital Engineer
Electrical Engineering Degree. 5 years sub micron VLSI digital design. C
RTL HW code.
VLSI log sim. Synopsis nice. Man Management. To work for premier
semiconductor company on exciting graphics projects.
Type: Permanent position Location: San Jose, California Salary: $70 - $75 K

ASIC Senior Design Engineer
To design and develop micro cells/micro functions (and then integrate them
at various levels of micro controllers) you will need good system
design experience with VHDL & synthesis of Digital Logic. Experience of
assembler and high level languages a plus
Type: Permanent Location: San Jose,California Start: ASAP Salary: $68 - $73K

ASIC Design Engineer
Must have excellent commercial experience as an ASIC engineer with 2 - 3
years experience in VHDL design. Must have 1st or 2nd degree with ideally
some telecoms background. FPGA experience is useful but VHDL is essential.
Type: Permanent Location: California Salary: $ 60 - $65

Send cv/resume to

Tony Quigley
Strategic Recruitment Solutions Ltd
Fax: +44-113-250-1553
E-mail: anthony.quigley@virgin.net




Article: 18218
Subject: RAM in xilinx FPGAs.
From: "Robert Larkin" <rlarkin@iee.org>
Date: Fri, 8 Oct 1999 12:12:15 +0100
Links: << >>  << T >>  << A >>
Hello,

I need to create a block of 3*64 memory in an 4005XLPC84. I have
been informed that this has to be done via 12 lookup tables. Does
any one know of an application note demonstrating how this can be
implemented? Also does any one have an example VHDL model that
either infers or instantiates RAM in this manner?

Thanks
Rob Larkin




Article: 18219
Subject: Re: RAM in xilinx FPGAs.
From: "Rémi SEGLIE" <rseglie@celogic.com>
Date: Fri, 8 Oct 1999 13:49:40 +0200
Links: << >>  << T >>  << A >>

Robert Larkin <rlarkin@iee.org> a écrit dans le message :
7tkknc$n7$1@news6.svr.pol.co.uk...
> Hello,
>
> I need to create a block of 3*64 memory in an 4005XLPC84. I have
> been informed that this has to be done via 12 lookup tables. Does
> any one know of an application note demonstrating how this can be
> implemented? Also does any one have an example VHDL model that
> either infers or instantiates RAM in this manner?
>
> Thanks
> Rob Larkin
>
>
>
>

You can download the application note 53 at
http://www.xilinx.com/apps/memory.htm, I think it answer to your question.

You can look too at Parameterizable "Distributed RAM for Virtex (VHDL)" at
http://www.xilinx.com/ipcenter/reference_designs/index.htm#Memory


Article: 18220
Subject: Preconfigured pull ups
From: "Daryl Bradley" <dwb105@nospam.ohm.york.ac.uk>
Date: Fri, 8 Oct 1999 13:04:32 +0100
Links: << >>  << T >>  << A >>
Could anyone advise me on the difference between configuring a Virtex FPGA
with preconfigured pull-ups or not?

Other than the fact of having pull up resistors - what is the relevance of
having pull ups or no pull ups for the configuration bit stream?

What should it be for a typical download via JTAG or Selectmap cables
connected directly to a PC

Many thanks

Daryl Bradley


Article: 18221
Subject: Re: RAM in xilinx FPGAs.
From: Ray Andraka <randraka@ids.net>
Date: Fri, 08 Oct 1999 08:48:58 -0400
Links: << >>  << T >>  << A >>
Xilinx has a couple of app notes on the RAM features of the 4K family.
I think the one you want to look at is xapp053, which you can get from
http://www.xilinx.com.  Synplicity will infer RAM correctly.  There is
application information with examples in the Synplicity help.  I am sure
Exemplar also does this by now.  You can also directly instantiate using
black-boxes to instantiate RAM16x1S components.  Instantiation gives you
the capability to add placement and initialization attributes to the RAM
if you so desire.

Robert Larkin wrote:

> Hello,
>
> I need to create a block of 3*64 memory in an 4005XLPC84. I have
> been informed that this has to be done via 12 lookup tables. Does
> any one know of an application note demonstrating how this can be
> implemented? Also does any one have an example VHDL model that
> either infers or instantiates RAM in this manner?
>
> Thanks
> Rob Larkin



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18222
Subject: Re: RAM in xilinx FPGAs.
From: "Watts" <jim.watts@worldnet.att.net>
Date: Fri, 8 Oct 1999 08:58:30 -0400
Links: << >>  << T >>  << A >>
Rob,
  Your best bet is to use the Core Generator tool that comes with both
Foundation and Alliance software packages from Xilinx.

  Using the Core Generator tool, you select your device family (4k) and any
other options you desire.  CoreGen will output several files, the main one
being a netlist to be used during Place and Route.  Also produced is a
".vhi" file that has the component declaration and instantiation template.

  As far as inferring RAM, both Leonardo Spectrum (Exemplar) and Synplify
(Synplicity) will infer memories.  You should check their web site(s) for
examples if you are using those synthesis tools.

  Good luck,

  Jim

Robert Larkin <rlarkin@iee.org> wrote in message
news:7tkknc$n7$1@news6.svr.pol.co.uk...
> Hello,
>
> I need to create a block of 3*64 memory in an 4005XLPC84. I have
> been informed that this has to be done via 12 lookup tables. Does
> any one know of an application note demonstrating how this can be
> implemented? Also does any one have an example VHDL model that
> either infers or instantiates RAM in this manner?
>
> Thanks
> Rob Larkin
>
>
>
>


Article: 18223
Subject: Can't detect Flex 10K Altera device through JTAG port
From: "Mike" <mmatusov@ics-ltd.com>
Date: Fri, 08 Oct 1999 13:27:24 GMT
Links: << >>  << T >>  << A >>
Hi all,

We are having troubles in programming Altera 10K30A device via JTAG port.
Altera software does not detect the device at all. Everything is configured
according to their datasheet for the case of JTAG only programming. There is
only one device in the chain. We are using standard ByteBlaster.

Our only guess is that two pins nCONFG and nTRST of the device that should
be tied high for this to work according to Altera, are connected in our case
to 3.3v plane. 3.3v in its turn is generated on our board and there is about
3ms delay on power-up before it goes up. In other words on power up these
two pins are essentially tied low and if their condition is latched at that
moment then that would explain weird behaviour we see. But is it actually
being latched at all?

Can anybody shed some light on this matter?

Thank you in advance.


Mikhail Matusov


Article: 18224
Subject: Announcement: VHDL/FPGA Development Boards (up to 400.000 Gates)
From: lothar_brodbeck@my-deja.com
Date: Fri, 08 Oct 1999 13:36:01 GMT
Links: << >>  << T >>  << A >>
Hello reader,

I would announce two development boards. The two boards are useful for
ASIC prototyping and simulation as well as for other purposes.
We and some other companies (Alcatel, Rhode&Schwarz, Siemens,
Wandel&Goltermann, ...) already used the boards to verify our
designs.

Examples:

- DSP algorithms written in VHDL
- behaviour of PLL circuits
- building of complex test equipment
- call simulator for 480 subscribers
- etc.


Short description of the boards:

Altera FLEX10K development board:

- up to 400.000 logical gates
- 2 slots for external memory (standard SIMM modules)
- PBA size 233mm*210mm
- 5V or 3.3V operation voltage (depending on used FPGAs)
- breadboard area for user applications
- on board reset circuit
- ...


Altera FLEX8K development board:

- up to 20.000 logical gates
- PBA size 233mm*160mm
- board splittable into 2 times 100mm*160mm
- 5V operation voltage
- breadboard area for user applications
- on board reset circuit
- ...

For more information about the development boards use one of
the possibilities listed below.

Web-Site:   1st page:
http://www.tzkom.de

                     development boards page:
http://www.tzkom.de/kompetenz/nt/devboard.htm

                     (English: sorry not the final version
http://www.tzkom.de/kompetenz/nt/devboard_e.htm)

Email:        Lothar.Brodbeck@tzkom.de .


Kind Regards

Lothar Brodbeck


p.s.:

An user wrote:    ... we successfully used the Altera FLEX10K board to
                         verify our complex signal processing algorithm.
... The
                         programming and the handling of the evaluation
board
                         stands out. ...


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Before you buy.


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