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Messages from 18450

Article: 18450
Subject: interface effort
From: Gerd Rausch <Gerd.Rausch@eed.ericsson.se>
Date: 25 Oct 1999 15:11:11 +0200
Links: << >>  << T >>  << A >>

Hi,

beeing a bloody newcomer in the FPGA area, 
can anyone tell me how much effort it is to learn & use
both PCI and PCMCIA (once they are available) FPGA cards
in a software package, provided I don't have to write the
FPGA parts myself (``only'' loading the algorithms and
interfacing them is required).
* It probably includes learning how FPGA works in general
* Writing or using FPGA glue code (to download the software,
  and interfacing the algorithms running on the FPGA)

Maybe someone who has faced the same problem some time ago
can share his experience.
I wonder wether we're talking about days, months, years...

Best Regards,

   Gerd Rausch

-- 
voice: +49-2407-575-353
email: Gerd.Rausch@ericsson.com
Article: 18451
Subject: unknown in real life
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 25 Oct 1999 17:28:31 +0300
Links: << >>  << T >>  << A >>

I observe some signals keep unknown value in some simulation steps.
When I program an FPGA where some signals keep unknown values
in some executions, does it harm the device? I have heard that unknown
value corresponds to an excessive current from GND or VDD.

Utku

--
I feel better than James Brown.



Article: 18452
Subject: Altera newbie simulation problem
From: Pat Hennessy <pat.hennessy@gsfc.nasa.gov>
Date: Mon, 25 Oct 1999 12:01:07 -0400
Links: << >>  << T >>  << A >>
Hi,

I am trying to simulate a very simple circuit with MAX+plus II:

74161 counter, 10 MHz clock, clear input driven high (i.e., inactive),
all other inputs floating (defaults to:  count inputs grounded, load
input inactive, count enables active).

The count outputs count properly but, the RCO output indicates an
undefined state at all count values.  It should be low except when the
count value is fifteen.  Oddly enough, when the RCO is gated through an
AND gate, the AND gate's output shows the undefined state during the
time when the RCO should be high.

I've selected a FLEX 6K device.

Any ideas what I'm doing wrong?


TIA,

Pat
Article: 18453
Subject: Re: XILINX: XDL - is this a secret?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 25 Oct 1999 17:15:13 +0100
Links: << >>  << T >>  << A >>


Andreas Doering wrote:

> Hi,
> more by accident I found the program XDL in my Alliance distribution.
> XDL is a program that converts a XILINX design between ncd
> (binary undocumented internal) and XDL an ASCII format.
> Beside of two work around answers in the data base I have not yet found
> any hint or documentation on this.
> I think this is a great thing, because it is much easier
> finding things, you can use grep/wc/perl what you like
> to check things.
> Without xdl the only way back to a processable text file is pre-map with
> ngd2vhdl/ngd2edif and the like.
> Only timing information can added.
> I think that such open interfaces are a big win,
> especially for reconfigurable computing because access
> to very low end features are possible without re-engineered
> bit-stream manipulation.
> (Of course, meanwhile there is also JavaBits).
> Andreas
>
> -----------------------------------------------------------------
>                         Andreas C. Doering
>                         Medical University Luebeck, Germany
>                         Home: http://www.iti.mu-luebeck.de/~doering
>                              quiz, papers, VHDL, music
> "The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
> ----------------------------------------------------------------

I sent this request in to Xilinx a few months ago and got the answer that
the docs will be included in the 2.1i release.
Unpacking my 2.1i and there they were in $(XILINX)\userware\doc. They are in
HTML format and nowhere near as good as the main tool descriptions but just
about useable. Looking at the xdl-ucs-ext file it appears that there are a
lot of undocumented ``hidden flags''.  One real omission is that XDL cannot
convert the .ngd type files produced by ngdbuild and ngdanno.

Article: 18454
Subject: Re: Xilinx Orientation Question
From: fliptron@netcom.com (Philip Freidin)
Date: 25 Oct 1999 16:23:47 GMT
Links: << >>  << T >>  << A >>
In article <01bf1cf6$834c2000$207079c0@drt1>,
Austin Franklin <austin@darkr00m.com> wrote:
>
>
>Allan Herriman <allan.herriman.hates.spam@fujitsu.com.au> wrote in article
><380fdc19.6028487@newshost.fujitsu.com.au>...
>> On Thu, 21 Oct 1999 17:55:14 -0400, Ray Andraka <randraka@ids.net>
>> wrote:
>> 
>> [snip]
>> >Someone asked offline what
>> >constitutes "up" on the chips.  A good question, so I'll repeat the
>answer here.
>> >Up is what shows as up when you open the floorplanner.  IIRC, the quad
>flatpacks
>> >have pin one  on the top edge.  The best way to make sure you get it
>right is to
>> >open the floorplanner for the chip and package you are using and look at
>the pin
>> >numbers - they are printed on the floorplan screen.
>
>Is there a way to do this without having to create a blank design for it to
>'read' in?

Yes. Fliptronics ChipView creates floorplanning templates with all pin
numbers shown, and it can even print them so you can use it.
No input file required. Works for All XC4000 and Spartan products.

>OR better yet, why they don't have either an Adobe Acrobat (preferred) or
>PostScript printable and legible document for each package/die combination.
> It gets VERY tedious making these for the new Virtex chips....

Use ChipView, send to a postscript printer, set "print to a file"

Philip Freidin
Fliptronics


You know, I wouldn't have to post these blatant commercials, if you all 
bought a copy.

Article: 18455
Subject: Re: FPGA Timing Problem
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 25 Oct 1999 17:36:05 +0100
Links: << >>  << T >>  << A >>


Kai Troester wrote:

> the first thing you should do is a static timing analysis. static timing
> analysis means every possible path (pad to ff, ff to pad and ff to ff)
> will be checked. if you are using the M1 Foundation Tool of Xilinx than
> you have a timing analyzer. the timing analyzer uses your timing
> constraints and reports which paths fails the constraints. you should
> have timing constraints for every clock and for the delay time at the
> pads. if you have multiple clocks in your design you should design the
> crossing from one clock to an other very carefully.
>
> this are the general things i can suggest you.
>
> --
>

If you have access to an HDL simulator it might be worth trying some post
Place&Route simulation. This  has helped me find missing constraints before.
It can be a bit tedious to set up and work through a few bugs in the Xilinx
``gate-level'' model generation but once you are there you can play with
different clock speeds and see if you can trigger set/hold violations.


Article: 18456
Subject: Basut-error in Foundation F1.5 / JTAG Programmer M.1.5.25
From: "Alain Cloet" <alain_cloet@hotmail.com>
Date: Mon, 25 Oct 1999 19:02:23 +0200
Links: << >>  << T >>  << A >>
Hello all,
I'm having the following problem:
In a new product I have to program a Xilinx CPLD (XC95216) with Boundary
Scan.  As we have the Parallel Cable and Xilinx Foundation Series available,
we want to program with this tool.
As long as we 'isolate' the CPLD, and make a one-element chain, we are
capable of programming it (so the tool is ok, as well as the CPLD).
However, if we define a chain with more elements (the normal case will be 7,
maybe 9), then we always get a basut error for everything we want to do with
CPLD (programming, ID-check, erase, etc).
We tried to make the chain already in two ways:
a. Starting from the one-element-chain that is capable of programming, and
adding elements by loading their BSDL-files
b. Initializing the chain with the programmer itself (Seven elements are
found, but just the CPLD is recognized), loading the jedec-file for the
CPLD, and linking BSDL-files to the others.
If I'm not completelly wrong, the only thing the programmer needs to know is
how to put the other elements in bypass, as the other functions don't
matter...

Did anyone succeed in making a chain of several elements yet (of which some
aren't Xilinx-parts), and did this need some tricks ???

I give you an example of the errors I get (here a chain with two elements is
defined, first device is the CPLD XC95216, which is linked with jedec-file
top_cpld ; the second element is a Motorola 68360 QUICC-ÁP, linked with
bsdl-file quicc240.bsd)

>JTAG Programmer Started 1999/10/25 15:39:49
>Loading Boundary-Scan Description Language (BSDL) file
>'C:/fndtn/data/xc95216.bsd'.....completed successfully.
>Loading Boundary-Scan Description Language (BSDL) file
>'c:\DIR1\quicc240.bsd'.....completed successfully.
>Checking boundary-scan chain integrity...done.
>Verifying device positions in boundary-scan chain...
>Instance 'top_cpld(Device1)' at position '1'...verified.ERROR:basut -
>Boundary scan chain has >been improperly specified.  Please check your
>configuration and re-enter the boundary-scan chain information.
>Boundary-scan chain validated unsuccessfully.
>ERROR:basut - : The boundary-scan chain has not been declared correctly.
> Verify the syntax and correctness of the device BSDL files, correct the
> files, reset the cable and retry this command.


(BTW, I already posted an article simular to this one in May, but we didn't
succeed then, even with the hints given ; and due to priorities it didn't
matter for a while, but now it's there again...)

TIA,
Alain Cloet








Article: 18457
Subject: Problem solved?
From: "Khaled BENKRID" <kbenkrid@microsoft.com>
Date: Mon, 25 Oct 1999 19:41:11 +0100
Links: << >>  << T >>  << A >>
Hello,

I have used a more compact instance naming, and 'Map' worked fine. It seems
it is a string length overflow. I do not know if it is possible to overcome
this limitation since my designs might be even bigger in the future.

Khaled.


Article: 18458
Subject: Re: Problem solved?
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 25 Oct 1999 23:25:47 +0300
Links: << >>  << T >>  << A >>
Khaled BENKRID wrote:

> Hello,
>
> I have used a more compact instance naming, and 'Map' worked fine. It seems
> it is a string length overflow. I do not know if it is possible to overcome
> this limitation since my designs might be even bigger in the future.
>
> Khaled.

 Khaled,

 if it is possible, generate the instance name suffixes in hexadecimal numbers.
Like

 "inst_1/inst_11/inst_111/inst_1111/inst_11112/inst_111121/inst_1111211/...."

 might be

 "inst_0/inst_1/inst_3/inst_F/inst_1F/.."

 This will reduce the instance name length by at least four.

 Utku

--
I feel better than James Brown.



Article: 18459
Subject: Re: Problem solved?
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 25 Oct 1999 23:30:44 +0300
Links: << >>  << T >>  << A >>

in addition, drop out "inst_"... why don't you use just a "i" for instance?

--
I feel better than James Brown.



Article: 18460
Subject: Xilinx WebPACK tutorial
From: Dave Vanden Bout <devb@xess.com>
Date: Mon, 25 Oct 1999 18:03:03 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------F5CD52424994BBFBA72F0792
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Given the number of people who ask for a way to get started with programmable logic, we put together a tutorial on CPLD design using Xilinx's free WebPACK suite of tools.  You can find it at

    http://www.xess.com/webpack.pdf

The tutorial shows how to get and install the WebPACK software, and it shows how to use the software to do a simple combinational logic design and a hierarchical, sequential design using VHDL.  It covers all the phases from design entry, logic synthesis, fitting, bitstream generation, and downloading into the CPLD.

This tutorial will not make you an expert FPGA/CPLD designer and it is specific to Xilinx's tools, but it will get you started with a minimum investment of time and money.

--------------F5CD52424994BBFBA72F0792
Content-Type: text/x-vcard; charset=us-ascii;
 name="devb.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
 filename="devb.vcf"

begin:vcard 
n:Vanden Bout;David
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard

--------------F5CD52424994BBFBA72F0792--

Article: 18461
Subject: Re: Delta-Sigma DAC
From: "peter dudley" <padudle@worldnet.att.net>
Date: Mon, 25 Oct 1999 17:55:08 -0600
Links: << >>  << T >>  << A >>
Child

Your posting got me interested in the delta sigma DAC of XAPP154 so I read
it over. It looks to me that the ideas are basically sound and should work
well as shown. I think the important points are to follow the RC filter with
a high impedance load and to use their oversampling recommendations.

It occurred to that two FPGA outputs could be used generating the
complements of the same bit stream and then you would have a differential
signal to low pass filter. The two pins would form a pair that have a
constant current and this could reduce ground bounce related distortion.

My guess is that their single ended solution would work great however.

    Pete Dudley

Child K.L. Sun <u8713501@cc.nctu.edu.tw> wrote in message
news:38131eb8.344767491@netnews.nctu.edu.tw...
> Dear Guys,
>
> I am thinking of using Xilinx FPGA to implement a DAC.
> From the provided application notes XAPP154 (9/1999), an RC
> LPF has to be added. Could any one tell me if such a DAC can
> performs as well as an ordinary DAC (e.g. Rise/Fall Time,
> speed...)?
>
> Thankx.
>
> Child


Article: 18462
Subject: Re: Delta-Sigma DAC
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Tue, 26 Oct 1999 01:51:57 GMT
Links: << >>  << T >>  << A >>
On Mon, 25 Oct 1999 17:55:08 -0600, "peter dudley"
<padudle@worldnet.att.net> wrote:

>Child
>
>Your posting got me interested in the delta sigma DAC of XAPP154 so I read
>it over. It looks to me that the ideas are basically sound and should work
>well as shown. I think the important points are to follow the RC filter with
>a high impedance load and to use their oversampling recommendations.

I read it over too, but I wouldn't say that *all* of the ideas are
basically sound.

"For example, the 16-bit audio DACs in a CD system
would require a clock frequency of 2.9 GHz for full resolution of the
highest frequencies. In practice, a much lower clock frequency is
used."

Audio converters generally aren't 1st order DSMs, so these figures
don't apply.

Regards,
Allan.

>It occurred to that two FPGA outputs could be used generating the
>complements of the same bit stream and then you would have a differential
>signal to low pass filter. The two pins would form a pair that have a
>constant current and this could reduce ground bounce related distortion.
>
>My guess is that their single ended solution would work great however.
>
>    Pete Dudley
>
>Child K.L. Sun <u8713501@cc.nctu.edu.tw> wrote in message
>news:38131eb8.344767491@netnews.nctu.edu.tw...
>> Dear Guys,
>>
>> I am thinking of using Xilinx FPGA to implement a DAC.
>> From the provided application notes XAPP154 (9/1999), an RC
>> LPF has to be added. Could any one tell me if such a DAC can
>> performs as well as an ordinary DAC (e.g. Rise/Fall Time,
>> speed...)?
>>
>> Thankx.
>>
>> Child
Article: 18463
Subject: Xilinx BGA pinout issue.....
From: "Austin Franklin" <austin@darkroom0.com>
Date: 26 Oct 1999 03:22:35 GMT
Links: << >>  << T >>  << A >>
I have been working on pinning out a Virtex in a 432 BGA....so, for
resources, I was using the pin diagram shown in the Xilinx data
book....along with the Floor Planner and the FPGA Editor.

Well, I noticed a major discrepancy.  The data book showed pin C30 in the
upper right, and both the Floor Planner, and the FPGA Editor showed C30 in
the upper LEFT!

What turns out to be the 'discrepancy' is....the die is UPSIDE DOWN in the
BGA, and they don't reflect that in either the FPGA Editor or the Floor
Planner...so...the left edge in the Floor Planner and the FPGA Editor is
actually the RIGHT edge of the physical package.

The problem this can create, is if I was to use just the Floor Planner as
my guide for physical pinning of the device, I would end up with pins on
the wrong side of the device which would create a PCB routing mess. 

The data flow of the 4k series used to work best going from left to
right...because of the horizontal routing between CLBs...and the carry
chain ran bottom to top...but it appears that in the Virtex parts (at least
according to the physical layout viewed in FPGA Editor), there is no real
advantage to data flow going left to right, or right to left, since all the
inputs to the CLBs are on the bottom, and outputs are on the top.  The
Floor Planner shows a DIFFERENT story, though....it has all the elements
looking like they flow from left to right (though, they are really from
right to left in the BGA because the die is mounted upside down...).  I
have chosen to believe the FPGA Editor...unless someone else knows
otherwise...

Anyone have any notes on data flow in the Virtex parts that I missed (like
something is better going from left to right or right to left)?  The carry
chain appears to only run up...so I'll keep that in mind while doing my
floor planning, and bit ordering.

Comments?



Article: 18464
Subject: Comparison between Altera and Xilinx
From: u8713501@cc.nctu.edu.tw (Child K.L. Sun)
Date: Tue, 26 Oct 1999 06:09:34 GMT
Links: << >>  << T >>  << A >>

	Have you tried both of the chips/software from these two
	companies?
	What's the difference between them?

							Child
Article: 18465
Subject: Re: Delta-Sigma DAC
From: u8713501@cc.nctu.edu.tw (Child K.L. Sun)
Date: Tue, 26 Oct 1999 06:18:50 GMT
Links: << >>  << T >>  << A >>
On Tue, 26 Oct 1999 01:51:57 GMT,
allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman) wrote:

>"For example, the 16-bit audio DACs in a CD system
>would require a clock frequency of 2.9 GHz for full resolution of the
>highest frequencies. In practice, a much lower clock frequency is
>used."
>
>Audio converters generally aren't 1st order DSMs, so these figures
>don't apply.
>
>Regards,
>Allan.
>

For my applications, I just wanna turn a demultiplexed(1:4) bit stream
(of bit rate 155Mbps) into 16-PAM signals. So I want to know if such
a fpga DAC structure can perform as well as a tranditional DAC does.

Child :~]
Article: 18466
Subject: WICKED WILD WILD WEST 8795
From: qvhqlm@aerosmith.net
Date: 26 Oct 1999 08:11:06 GMT
Links: << >>  << T >>  << A >>
Will Smith Totally Lost It AT

http://www.hardcore.tmfweb.nl/

Article: 18467
Subject: FPGA Starter Kit
From: holosapien@my-deja.com
Date: Tue, 26 Oct 1999 08:17:34 GMT
Links: << >>  << T >>  << A >>
Hi,

Atmel / Kanda Systems have just produced a new low cost FPGA Starter
Kit which is available to purchase online.  More information can be
found at:

http://www.kanda.com

There is also an FPGA book which can be bought separately (but is
included in the kit).

Hope that helps.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18468
Subject: Re: XILINX: XDL - is this a secret?
From: Joni Dambre <jdambre@elis.rug.ac.be>
Date: Tue, 26 Oct 1999 11:31:41 +0200
Links: << >>  << T >>  << A >>
Andreas Doering wrote:

> more by accident I found the program XDL in my Alliance distribution.
> XDL is a program that converts a XILINX design between ncd
> (binary undocumented internal) and XDL an ASCII format.
> Beside of two work around answers in the data base I have not yet found
> any hint or documentation on this.
> I think this is a great thing, because it is much easier
> finding things, you can use grep/wc/perl what you like
> to check things.
> Without xdl the only way back to a processable text file is pre-map with
> ngd2vhdl/ngd2edif and the like.
> Only timing information can added.
> I think that such open interfaces are a big win,
> especially for reconfigurable computing because access
> to very low end features are possible without re-engineered
> bit-stream manipulation.
> (Of course, meanwhile there is also JavaBits).
> Andreas

Hi,

Does this tool (XDL) actually convert the binary format to something legible? And does it work both ways? What phase of the design trajectory is this ncd format? Can you also use XDL to interface
between say tech mapping and placement?
And what is JavaBits?


Joni (feeling stupid)

-- 
Department of Electronics and Information Systems,
Faculty of Applied Sciences, University of Ghent,  
St. Pietersnieuwstraat 41,               
B-9000 Ghent, Belgium                 99999  
work phone: +32-9-264.34.09          9 o - 9   
email: jdambre@elis.rug.ac.be        9  |  9     
                                       \_/
Article: 18469
Subject: Re: Delta-Sigma DAC
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Tue, 26 Oct 1999 10:15:03 GMT
Links: << >>  << T >>  << A >>
On Tue, 26 Oct 1999 06:18:50 GMT, u8713501@cc.nctu.edu.tw (Child K.L.
Sun) wrote:

>On Tue, 26 Oct 1999 01:51:57 GMT,
>allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman) wrote:
>
>>"For example, the 16-bit audio DACs in a CD system
>>would require a clock frequency of 2.9 GHz for full resolution of the
>>highest frequencies. In practice, a much lower clock frequency is
>>used."
>>
>>Audio converters generally aren't 1st order DSMs, so these figures
>>don't apply.
>>
>>Regards,
>>Allan.
>>
>
>For my applications, I just wanna turn a demultiplexed(1:4) bit stream
>(of bit rate 155Mbps) into 16-PAM signals. So I want to know if such
>a fpga DAC structure can perform as well as a tranditional DAC does.

In this case you would *not* want to use a DSM DAC, as you wouldn't be
able to get the (over)sampling rate high enough.

Allan.
Article: 18470
Subject: Pc system requirment for Foundation Series
From: Oh Sheau Pyng <ASSPOh@ntu.edu.sg>
Date: Tue, 26 Oct 1999 18:16:10 +0800
Links: << >>  << T >>  << A >>
hi,

  I have some question regarding the PC system that run the Xilinx
Foundation series. 

  Will a multi-processor pc speed up the place and route process or
memory is more important?
  Can the Xilinx foundation software benefit from multi-processor
environment? ( o/s most likely will have to be NT)

  from my own observation during PNR ( which take up the most time ),
CPU Utilitization is 100 % and memory usage is < 256 Mbytes. No much
swapping is occuring as the HardDisk LED is not flashing.
  
  The design is about 1000 CLB , going to about 3000 ~ 3500 when the
design is complete
  clock = 40 MHz.
  o/s = win 98
  ram = 196 Mbyte
  swapdisk = 256 Mbyte
  CPU = PII 400

  Because we are looking into a upgrade of the PC system that run the
Xilinx Foundation s/w.
  Ram :  512 Mbyte or 1 GByte of system ram 
  Processor : PIII 600 , single or multi-processors.
  

  Any recommendation?? or where can I find the information ???

Thanks alot

Sheau Pyng


Article: 18471
Subject: Re: Announcing Free VHDL Simulator for Windows
From: Matthias Fuchs <matthias.fuchs@esd.h.uunet.de>
Date: Tue, 26 Oct 1999 13:15:43 +0200
Links: << >>  << T >>  << A >>
"Haneef D. Mohammed" wrote:
> 
> > Are you planning on a Linux release?  How about source code -- that would
> > really be no-strings-attached. :-)
> 
> Linux release? Maybe, maybe soon (no promises).
> Source-code? Maybe not :-)
Linux would be very good ! My main OS is linux. If I have to do some
fpga designing, I have to switch to bill's toys. So I am glad about any
linux EDA tool that will be available.

Matthias
Article: 18472
Subject: BlockRAM of VIRTEX
From: rgadea@eln.upv.es (Rafael Gadea Girones)
Date: 26 Oct 1999 11:40:10 GMT
Links: << >>  << T >>  << A >>
Hi,

What is the difference between the BlockRAM of a VIRTEX and the BlockRAM of 
VIRTEX-E?

In the Features of VIRTEX-E (Advance Product Specification version 1.0) XILINX 
say that this Family has True Dual Read/Write Port Block RAM capability. What 
is the mean of True?

thanks in advance!

Regards,

Rafael Gadea
Departamento Ingenieria Electronica
Universidad Politecnica de Valencia
Spain


Article: 18473
Subject: generating power on initialisation
From: "Daryl Bradley" <dwb105@nospam.ohm.york.ac.uk>
Date: Tue, 26 Oct 1999 15:05:12 +0100
Links: << >>  << T >>  << A >>
Does anyone have any suggestions on how I can create a power on reset type
signal so that I can initialise signals/ variables to a set of default
values within a Virtex?

The requirement is to ensure that on boot up a set of commands are issued to
an external display to initialise it.

Either VHDL or schematic entry methods are suitable, although VHDL
preferable

many thanks

Daryl


Article: 18474
Subject: Re: generating power on initialisation
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Tue, 26 Oct 1999 17:57:24 +0200
Links: << >>  << T >>  << A >>
Hi

Xilinx 4000 parts have a power-on reset capability, I suppose the Virtex
ones have it too.
You have to instantiate the startup component:

COMPONENT startup
PORT(gsr : IN std_logic);
END COMPONENT;
...
startup_inst : startup
  PORT MAP(gsr => rst); -- where rst is your reset signal
...

(you might have to tell your synthesis tool not to remove this component
with no output)
This will automatically set or reset your design on power on.


Daryl Bradley wrote:
> 
> Does anyone have any suggestions on how I can create a power on reset type
> signal so that I can initialise signals/ variables to a set of default
> values within a Virtex?
> 
> The requirement is to ensure that on boot up a set of commands are issued to
> an external display to initialise it.
> 
> Either VHDL or schematic entry methods are suitable, although VHDL
> preferable
> 
> many thanks
> 
> Daryl

-- 
Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE


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