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Messages from 22100

Article: 22100
Subject: Re: Virtex-E and LVDS
From: Greg Neff <gregneff@my-deja.com>
Date: Sat, 22 Apr 2000 18:06:01 GMT
Links: << >>  << T >>  << A >>
In article <3900a40c.168130437@client.sw.news.psi.net>,
  steve@sk-tech.com wrote:
> Hello all,
> Does anyone know if the LDVS I/O on the Virtex-E family is compatible
> with LVD Ultra2 SCSI? They are close, and LVD is derived from EIA-644
> but I'm not quite sure if they are 100% compatible.
>
> Thank you,
> Steve
>

They look close enough to me, but you should verify that yourself.
Take a look at:

http://www.ti.com/sc/docs/products/analog/sn75lvdm976.html
http://www.ti.com/sc/docs/psheets/abstract/apps/slla035.htm
http://www.xilinx.com/products/virtex/techtopic/lvds.htm

also, spi3r13b.pdf at ftp://ftp.t10.org/t10/drafts/spi3/

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22101
Subject: High Speed LVDS or HSTL
From: louis-zhang <louis-zhang@home.com>
Date: Sat, 22 Apr 2000 22:37:50 GMT
Links: << >>  << T >>  << A >>
Hi,

Is anyone designing Virtex or Apex with high-speed LVDS(at 622Mbps)
or HSTL (at 200MHz) I/Os?  I was wondering if they work well.

Thanks a lot for sharing your experience.


-Louis Zhang
Article: 22102
Subject: Please Help with SBC's
From: rudy munguia <rmunguia@globalcenter.net>
Date: Sun, 23 Apr 2000 12:49:57 -0700
Links: << >>  << T >>  << A >>
Hi all,

I read the posts daily but don't post a whole lot myself, I am in a
tight spot and have to bend policy a little bit here, Please don't laugh

I need to sell my toys, here they are:

Qty (2) 486DX266 Single-Board Computers each equiped with
-32megs of RAM
-Opti Chipset
-award BIOS
-on-board UART
-on-board IDE
-14 slot passive ISA backplane
-1meg trident video card
-10meg SMC ethernet card
-300watt p/s
-Industrial 19" Rack Mount Chassis

These are my babies, I have run SCO Unix, FreeBSD, WinNT3.5/4.0, DOS6.2,
Debian Linux, and BeOS, succesfully on these for many different
applications ranging from simple coding to 32dof servo control systems.

Put simply, these are the all-time greatest hardware/software
experimentation platforms available.

Willing to sell in whole or part, serious inquiries only please.

I have a baby boy on the way and need to clear out my home lab.

Please direct all correspondence to my home email rudogATprimenetDOTcom
(replace the AT + DOT)
-- 
Rudolfo X. Munguia 

If you're not living on the edge, you're taking up too much space.
Article: 22103
Subject: CLKDLL
From: Sreedhar Sampath <sreedhar@capsl.udel.edu>
Date: Sun, 23 Apr 2000 17:34:29 -0400
Links: << >>  << T >>  << A >>
Could someone tell me how to instantiate CLKDLL in VHDL.

I used library virtex.component.all
When I use it as a component and port map it accordingly.

I get an error saying that the library is not mapped to the current
directory.
I am confused.

Thanks
-Sreedhar

Article: 22104
Subject: Re: CLKDLL
From: "JWKIM" <edward8@hanmail.net>
Date: Mon, 24 Apr 2000 10:25:58 +0900
Links: << >>  << T >>  << A >>
Problem Title:
SYNPLIFY: How to instantiate CLKDLL in HDL? (VHDL/Verilog)


Problem Description:
Urgency: Standard

General Description:
CLKDLL is a clock delay locked loop used to minimize clock skew.
The most simple configuration of clockdll (BUFGDLL) can be inferred
with a Xilinx specific attribute in Synplify (Xilinx Solution 688).

Otherwise, CLKDLL need to be instantiated as described below.
For further information on CLKDLL usages, please reference Xilins
Application Note 132: http://www.xilinx.com/xapp/xapp132.pdf

Note: tested in Synplify 5.2.2a.


Solution 1:

// Verilog example
// In this example ACLK's frequency is doubled, used inside and
// outside the chip.
// BCLK and OUTBCLK are connected in the board outside the chip.


`include "<path_to>/virtex.v"


module clock_test(ACLK, DIN, QOUT, BCLK, OUTBCLK, BCLK_LOCK, RESET);
  input ACLK, BCLK;
  input RESET;
  input [1:0] DIN;
  output [1:0] QOUT;
output OUTBCLK, BCLK_LOCK;

reg [1:0] QOUT;

IBUFG CLK_ibufg_A
       (.I (ACLK),
       .O(ACLK_ibufg)
       );

BUFG ACLK_bufg
       (.I (ACLK_2x),
        .O (ACLK_2x_design)
       );



IBUFG CLK_ibufg_B
      (.I (BCLK),     // connected to OUTBCLK outside
      .O(BCLK_ibufg)
      );


CLKDLL ACLK_dll_2x   // 2x clock
      (.CLKIN(ACLK_ibufg),
      .CLKFB(ACLK_2x_design),
      .RST(1'b0),
      .CLK2X(ACLK_2x),
      .CLK0(),
      .CLK90(),
      .CLK180(),
      .CLK270(),
      .CLKDV(),
      .LOCKED(ACLK_lock)
      );

CLKDLL BCLK_dll_OUT // off-chip synchronization
       (.CLKIN(ACLK_ibufg),
       .CLKFB(BCLK_ibufg), // BCLK and OUTBCLK is connected outside the
chip.
       .RST(1'b0),
       .CLK2X(OUTBCLK), file://connected to BCLK outside
       .CLK0(),
       .CLK90(),
       .CLK180(),
       .CLK270(),
       .CLKDV(),
       .LOCKED(BCLK_LOCK)
       );

always @(posedge ACLK_2x_design or posedge RESET)
begin
if (RESET)
  QOUT[1:0] <= 2'b00;
else if (ACLK_lock)
  QOUT[1:0] <= DIN[1:0];
end

endmodule



Solution 2:

-- VHDL example

library IEEE;
use IEEE.std_logic_1164.all;

library virtex;
use virtex.components.all;

entity CLOCK_TEST is
   port(
     ACLK : in std_logic;

     -- off chip feedback, connected to OUTBCLK on the board.
     BCLK : in std_logic;

     --OUT CLOCK
     OUTBCLK : out std_logic;


    DIN   : in  std_logic_vector(1 downto 0);
    RESET  : in  std_logic;
    QOUT  : out std_logic_vector (1 downto 0);


    -- CLKDLL lock signal
    BCLK_LOCK  : out std_logic
    );
end CLOCK_TEST;

architecture RTL of CLOCK_TEST is

   component IBUFG
     port (
       I : in std_logic;
       O : out std_logic);
   end component;

   component BUFG
     port (
       I : in std_logic;
       O : out std_logic);
   end component;


  component CLKDLL
    port (
      CLKIN  : in std_logic;
      CLKFB  : in std_logic;
      RST    : in std_logic;
      CLK0   : out std_logic;
       CLK90 : out std_logic;
       CLK180 : out std_logic;
       CLK270 : out std_logic;
       CLKDV : out std_logic;
       CLK2X : out std_logic;
       LOCKED : out std_logic);
   end component;

   -- Glock signals
   signal ACLK_ibufg : std_logic;
   signal BCLK_ibufg : std_logic;
   signal ACLK_2x : std_logic;
   signal ACLK_2x_design : std_logic;
   signal ACLK_lock : std_logic;

begin

   ACLK_ibufg : IBUFG
     port map (
       I => ACLK,
       O => ACLK_ibufg
       );

   BCLK_ibufg : IBUFG
     port map (
       I => BCLK,
       O => BCLK_ibufg
       );

   ACLK_bufg : BUFG
     port map (
       I => ACLK_2x,
       O => ACLK_2x_design
       );

   ACLK_dll : CLKDLL
     port map (
       CLKIN => ACLK_ibufg,
       CLKFB => ACLK_2x_design,
       RST => '0',
       CLK2X => ACLK_2x,
       CLK0 => OPEN,
       CLK90 => OPEN,
       CLK180 => OPEN,
       CLK270 => OPEN,
       CLKDV => OPEN,
       LOCKED => ACLK_lock
       );


    BCLK_dll_out : CLKDLL
      port map (
        CLKIN => ACLK_ibufg,
        CLKFB => BCLK_ibufg,
        RST => '0',
        CLK2X => OUTBCLK,
        CLK0 => OPEN,
        CLK90 => OPEN,
        CLK180 => OPEN,
        CLK270 => OPEN,
        CLKDV => OPEN,
        LOCKED => BCLK_lock
        );


process (ACLK_2x_design, RESET)
begin
  if RESET = '1' then
   QOUT <= "00";
  elsif ACLK_2x_design'event and ACLK_2x_design = '1' then
   if ACLK_lock = '1' then
    QOUT <= DIN;
   end if;
  end if;
end process;

END RTL;





Sreedhar Sampath <sreedhar@capsl.udel.edu>이(가) 아래 메시지를
news:Pine.GSO.3.96.1000423173243.21672A-100000@altman.capsl.udel.edu에
게시하였습니다.
> Could someone tell me how to instantiate CLKDLL in VHDL.
>
> I used library virtex.component.all
> When I use it as a component and port map it accordingly.
>
> I get an error saying that the library is not mapped to the current
> directory.
> I am confused.
>
> Thanks
> -Sreedhar
>


Article: 22105
Subject: Re: Virtex-E and LVDS
From: "Gary Watson" <gary@nexsan.sex>
Date: Mon, 24 Apr 2000 11:26:19 +0100
Links: << >>  << T >>  << A >>
<steve@sk-tech.com> wrote in message
news:3900a40c.168130437@client.sw.news.psi.net...
> Hello all,
> Does anyone know if the LDVS I/O on the Virtex-E family is compatible
> with LVD Ultra2 SCSI? They are close, and LVD is derived from EIA-644
> but I'm not quite sure if they are 100% compatible.

The SCSI version of LVD started life as compatible with LVDS, but they have
made at least one change.  The SCSI LVD drivers are not symmetrical.  I was
in the room when this discussion was taking place at a SCSI committee WG
meeting, but I wasn't paying close enough attention and can't remember why
this was done.  I suppose it reduces the average power consumption, since
statistically the drivers are off more than on, but they are tristate more
often than not, so it doesn't seem a good enough reason to invent another
I/O pad.

At a casual glance, the signals look close enough to work at low
frequencies, so I'm planning to make an experimental board which will be
used for diagnostic testing of complex SCSI boards.

One thing, though, LVD drivers are supposed to switch to single-ended
operation if the DIFFSENS line goes to ground, and should go tristate in
response to the level being illegal or set to HVD.  I don't see how the
Virtex can do this.

--

Gary Watson
gary@nexsan.sex  (Change dot sex to dot com to reply!!!)
Nexsan Technologies Ltd.
Derby DE21 7BF  ENGLAND
http://www.nexsan.com





Article: 22106
Subject: Re: Virtex-E and LVDS
From: steve@sk-tech.com
Date: Mon, 24 Apr 2000 14:11:11 GMT
Links: << >>  << T >>  << A >>
Thank you very much to all for the info.

Steve

On Mon, 24 Apr 2000 11:26:19 +0100, "Gary Watson" <gary@nexsan.sex>
wrote:

><steve@sk-tech.com> wrote in message
>news:3900a40c.168130437@client.sw.news.psi.net...
>> Hello all,
>> Does anyone know if the LDVS I/O on the Virtex-E family is compatible
>> with LVD Ultra2 SCSI? They are close, and LVD is derived from EIA-644
>> but I'm not quite sure if they are 100% compatible.
>
>The SCSI version of LVD started life as compatible with LVDS, but they have
>made at least one change.  The SCSI LVD drivers are not symmetrical.  I was
>in the room when this discussion was taking place at a SCSI committee WG
>meeting, but I wasn't paying close enough attention and can't remember why
>this was done.  I suppose it reduces the average power consumption, since
>statistically the drivers are off more than on, but they are tristate more
>often than not, so it doesn't seem a good enough reason to invent another
>I/O pad.
>
>At a casual glance, the signals look close enough to work at low
>frequencies, so I'm planning to make an experimental board which will be
>used for diagnostic testing of complex SCSI boards.
>
>One thing, though, LVD drivers are supposed to switch to single-ended
>operation if the DIFFSENS line goes to ground, and should go tristate in
>response to the level being illegal or set to HVD.  I don't see how the
>Virtex can do this.
>
>--
>
>Gary Watson
>gary@nexsan.sex  (Change dot sex to dot com to reply!!!)
>Nexsan Technologies Ltd.
>Derby DE21 7BF  ENGLAND
>http://www.nexsan.com
>
>
>
>
>

Article: 22107
Subject: Re: Virtex-E and LVDS
From: Greg Neff <gregneff@my-deja.com>
Date: Mon, 24 Apr 2000 14:13:16 GMT
Links: << >>  << T >>  << A >>
In article <dbWM4.7276$jj.1064002@news-west.usenetserver.com>,
  "Gary Watson" <gary@nexsan.sex> wrote:
>
> The SCSI version of LVD started life as compatible with LVDS, but
they have
> made at least one change.  The SCSI LVD drivers are not symmetrical.
I was
> in the room when this discussion was taking place at a SCSI committee
WG
> meeting, but I wasn't paying close enough attention and can't
remember why
> this was done.

This was done because LVD SCSI uses biased differential termination.
The asymetrical drivers compensate for this, providing some additional
assertion current to overcome the terminator bias current.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


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Before you buy.
Article: 22108
Subject: Any good third-party place and route tools?
From: Chris Plachta <cplachta@usa.alcatel.com>
Date: Mon, 24 Apr 2000 11:21:45 -0700
Links: << >>  << T >>  << A >>
SGksDQoNCkkgd2FzIHdvbmRlcmluZyBpZiB0aGVyZSBhcmUgYW55IGdvb2QgdGhpcmQtcGFy
dHkgcGxhY2UgYW5kIHJvdXRlIHRvb2xzDQpmb3IgRlBHQXMgb3V0IHRoZXJlLg0KDQpTcGVj
aWZpY2FsbHksIEkgYW0gbG9va2luZyBmb3IgYSB0b29sIHRoYXQgcHJlc2VydmVzIHRoZSBo
aWVyYXJjaHkgYW5kDQpuZXQgbmFtZXMgaW4gdGhlIHBvc3Qtcm91dGUgZGF0YWJhc2UuIEkg
anVzdCBmaW5pc2hlZCBhbiBBbHRlcmEgZGVzaWduDQp0aGF0IGhhZCBwb3N0LXJvdXRlIHRp
bWluZyBwcm9ibGVtcywgYW5kIHdlIGhhZCBubyB3YXkgb2YgcGVyZm9ybWluZyBhDQpnb29k
IHN0YXRpYyB0aW1pbmcgYW5hbHlzaXMgb3IgcG9zdC1yb3V0ZSBzaW11bGF0aW9uIHNpbmNl
IGFsbCBvZiB0aGUNCnJlZ2lzdGVycyBhbmQgbmV0cyB3ZXJlIHJlbmFtZWQgYnkgdGhlIEFs
dGVyYSB0b29sLCBhbmQgdGhlcmUgaXMgbm8NCmtub3duIG1hcHBpbmcgYmFjayB0byB0aGUg
b3JpZ2luYWwgc291cmNlIGNvZGUuIFdlIGhhZCB0byBkZWJ1ZyB0aGUNCnByb2JsZW0gaW4g
dGhlIGxhYi4NCg0KVGhhbmtzLg0KDQotLQ0KQ2hyaXMgUGxhY2h0YQ0KQWxjYXRlbCBVU0EN
ClBob25lOiA3MDctNzkyLTcyNzENCkZBWDogICA3MDctNzkyLTYzMTANCg0KDQo=
Article: 22109
Subject: xilinx --> altera vhdl
From: Tobin Fricke <tobin@cory.eecs.berkeley.edu>
Date: Mon, 24 Apr 2000 22:28:12 GMT
Links: << >>  << T >>  << A >>
Hello,
I have a VHDL model written for a xilinx environment which uses the
"vlbit" and "vlbit_1d" types, as well as operators such as "vld2int" and
"addum".  I'd like to port this over to an altera environment (maxplus)
and use IEEE standard logic, but I'm not sure what the analogous
operations are for stdlogic and stdlogic_vector.  Could anyone help me
out or point me in the right direction?  I found this question asked a
couple times in the past on dejanews, but no solutions.

Thanks,
Tobin <tobin@cory.eecs.berkeley.edu>
Article: 22110
Subject: Quartus "clock skew excedes data delay" error
From: qaz <johnsNOjoSPAM@condoreng.com.invalid>
Date: Mon, 24 Apr 2000 15:56:27 -0700
Links: << >>  << T >>  << A >>
Has anyone else experienced the "clock skew excedes data delay"
error" reported by Quartus? If so, has anyone found a way around
it WITHOUT utilizing an on chip PLL? How? Apparently the problem
exists in the timing analyzer software, not in the actual
silicon.

---John S.

* Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
The fastest and easiest way to search and participate in Usenet - Free!

Article: 22111
Subject: Segregation between synthesis code and simulation code
From: #YEO WEE KWONG# <P7102672H@ntu.edu.sg>
Date: Tue, 25 Apr 2000 10:15:14 +0800
Links: << >>  << T >>  << A >>
Hi,

Anyone can render some asst. over how to segregate the code between
synthesis and simulation code. My requirement is :

1)	Allow those assert and only simulation code to be present
without causing an error or warning during synthesis. What is the best
approach without incurring too much inconvenience in masking and
unmasking code

	I currently use the technique of :
2)	masking and unmasking code but cumbersome techniques
3)	Used pragma as in pragma synthesis - apprently looks ok but I
run into problem with  simulation code only library eg.library
mypackage; 
            use mypackage.all;   <-- Cause mapping problem with DC

Anyone can help to suggest better ways to do it. Thanks a million.

Yeo Wee Kwong, Sky (Mr) 

Article: 22112
Subject: ****Easy Money****
From: Jeff Piper <clandm@home.com>
Date: Tue, 25 Apr 2000 03:55:49 GMT
Links: << >>  << T >>  << A >>
Ever wonder what "Pay to Surf" programs actually work?

Well, visit the link below for your chance to learn what ones to signup
with and which ones to stay away from!

I have found one that pays minimum $20 / hr upto $120 an hour.

http://www.geocities.com/phreecash/

Thanks,

CDN.Bacon

Article: 22113
Subject: Any free design of 80C186 ??
From: David <ecmvandfNOecSPAM@worldnet.fr.invalid>
Date: Tue, 25 Apr 2000 05:15:18 -0700
Links: << >>  << T >>  << A >>
Is there any free design of Intel 80C186 on the net ???


* Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping.  Smart is Beautiful
Article: 22114
Subject: Re: which pci board?
From: "Nikolay Rognlien" <nikolayr@acte.no>
Date: Tue, 25 Apr 2000 15:53:13 +0200
Links: << >>  << T >>  << A >>
PLD applications have some PCI boards with Altera FPGA's. Maybe they can
help?
http://www.plda.com/

-Nikolay

Frederic Magniette <magniett@lri.fr> wrote in message
news:3900C386.F2BA900B@lri.fr...
> Dear gentle persons,
> I'm searching for a PCI board to make material accelerators for Linux.
> Do you know some of this kind of board?
> I thank you by advance
> frederic
>


Article: 22115
Subject: Re: PCI Bridge to Xilinx XCV*E
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 25 Apr 2000 09:59:34 -0400
Links: << >>  << T >>  << A >>
Utku Ozcan wrote:
> 
> Sorry for the mistake in my very first mail. Actually on the
>   board there will be BOTH the 860 and 8240 processors.
> 
>   The reason why we have chosen both of these is backward
>   compatibility. That Virtex-E devices don't have PCI interfaces
>   at a first glance is also because of backward compatibility.
> 
>   Keith, thank you very much for the site you have given me.
> 
>   But although the backward compatibility makes our mind busy,
>   PCI core also seems to be attractive. We are paying attention
>   to experiences around.
> 
>   Utku
> 
> --
> I feel better than James Brown.

Sorry for the late response, but have you looked at parts other than the
ones from Xilinx? Lucent makes a few FPGAs (which are similar to the
Xilinx parts) that include a PCI interface in dedicated hardware. This
uses much less space on the chip than a PCI core would. But the proof of
the pudding... I have not priced any of these OR3T+ chips. They would
only be an advantage if they end up being cheaper for the number of
gates you will need. But then you also have to include the cost of the
core.


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22116
Subject: Re: xilinx --> altera vhdl
From: mench@mench.com
Date: 25 Apr 2000 11:25:41 -0400
Links: << >>  << T >>  << A >>
On Mon, 24 Apr 2000 22:28:12 GMT, in comp.lang.vhdl Tobin Fricke
<tobin@cory.eecs.berkeley.edu> wrote in article
<3904CA7C.DEF02B0@cory.eecs.berkeley.edu>:

> I have a VHDL model written for a xilinx environment which uses the
> "vlbit" and "vlbit_1d" types, as well as operators such as "vld2int"
> and "addum".  I'd like to port this over to an altera environment
> (maxplus) and use IEEE standard logic, but I'm not sure what the
> analogous operations are for stdlogic and stdlogic_vector.  Could
> anyone help me out or point me in the right direction?  I found this
> question asked a couple times in the past on dejanews, but no
> solutions.

The type vlbit is part of a type system promulgated by ViewLogic.  It's
been a while, but IIRC, the type was:

	type vlbit is ('X', '0', '1', 'Z');

It should be analogous to std_ulogic.

IIRC, vlbit_1d is:

	type vlbit_1d is array(Natural range <>) of vlbit;

The analogous type is std_(u)logic_vector.  (I can't recall what they
did, if anything, about resolution.)

vld2int is presumably a function that converts a vlbit_1d to a
natural, assuming an unsigned magnitude reprensentation of the
vlbit_1d.  The corresponding operations need stuff from numeric_std,
but would be along the lines of:

	Y := to_integer( unsigned( X ));

where
	X is a std_(u)logic_vector to be treated as an unsigned
	  magnitude integer, and

	Y is the resulting (natural) integer.

Hope this helps,

Paul

-- 
Paul Menchini         |  "Outside of a dog, a book is probably man's
Menchini & Associates |   best friend, and inside of a dog, it's too
mench@mench.com       |   dark to read."
www.mench.com         |       --Groucho Marx
Article: 22117
Subject: Re: Is there any DSP and FPGA based board suitable to motor drive
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 25 Apr 2000 12:36:05 -0400
Links: << >>  << T >>  << A >>
Hi Jack,

We have a DSP board with FPGA IO which may do the job you need. On our
board, the FPGAs are in the path for all IO and can be programmed to
work autonomously. 

We have not designed specific IO for motor control, but our IO is done
through modules we call AIO modules. These are small daughterboards
which can connect the FPGAs to the outside world through level
translators or other types of interface conversion such as ADC/DAC. 

You can take a look at our TMS320C31 based board at
http://www.arius.com/pc104c31.html. It can be used on the PC/104 bus or
will operate as a stand alone unit. It provides two channels of serial
IO with RS-232, RS-422 or RS-485 interfaces. With two AIO daughterboard
sites, you can select different IO types to work simultaneously.

If you have any other questions, please contact me directly. 




"Jack D. Ma" wrote:
> 
> Hi, friends,
> 
> Does anyone know is there any commercial DSP and FPGA based general
> purpose control board suitable to motor drive control? FPGA takes care
> of the A/D, D/A and gating and DSP takes care of the calculation part.
> 
> Thanks
> 
> Jack


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22118
Subject: Re: Segregation between synthesis code and simulation code
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Tue, 25 Apr 2000 09:40:09 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Sounds like you are using Design Compiler.  If so, you can use the
following pragma's in your code to mask out non-synthesizable code:

- - pragma translate_off

Non-synthesizable code here

- - pragma translate_on


This works for simulation library mappings as well as anything else you
may not want the synthesis tool to see.  Most simulators simply ignore
these pragma's and read the code.

You need to be sure that you have the following variable set in order to
use this pragma:

hdlin_translate_off_skip_text = true

I usually just set this in my .synopsys_dc.setup file and forget it.


--  Brian



#YEO WEE KWONG# wrote:

> Hi,
>
> Anyone can render some asst. over how to segregate the code between
> synthesis and simulation code. My requirement is :
>
> 1)      Allow those assert and only simulation code to be present
> without causing an error or warning during synthesis. What is the best
> approach without incurring too much inconvenience in masking and
> unmasking code
>
>         I currently use the technique of :
> 2)      masking and unmasking code but cumbersome techniques
> 3)      Used pragma as in pragma synthesis - apprently looks ok but I
> run into problem with  simulation code only library eg.library
> mypackage;
>             use mypackage.all;   <-- Cause mapping problem with DC
>
> Anyone can help to suggest better ways to do it. Thanks a million.
>
> Yeo Wee Kwong, Sky (Mr)

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begin:vcard 
n:Philofsky;Brian
tel;work:1-800-255-7778
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url:http://www.xilinx.com
org:Xilinx, Inc.;Software Marketing
adr:;;2100 Logic Dr.;San Jose;CA;95124;USA
version:2.1
email;internet:brianp@xilinx.com
title:Technical Marketing Engineer
fn:Brian Philofsky
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--------------05C39CD56362209BD3F41663--

Article: 22119
Subject: Re: Segregation between synthesis code and simulation code
From: husby@fnal.gov (Don Husby)
Date: Tue, 25 Apr 2000 18:47:59 GMT
Links: << >>  << T >>  << A >>
#YEO WEE KWONG# <P7102672H@ntu.edu.sg> wrote:
> Anyone can render some asst. over how to segregate the code between
> synthesis and simulation code. My requirement is :

Lack of conditional compilation is one of the many "features" of VHDL

Here is a short program that I use for switching between sim and synth.
All you have to do is tag each line that is needed for simulation with --$
and each line needed for synthesis with --#.

for example:
================
library "mylib"
  use "mylib.synth.all";   --# This is used only for synthesis
  use "mylib.sim.all";     --$ This is used only for simulation 
================

You need to run the preprocessor to convert files before compiling.
This code compiles under MS Visual C 6.0 for Windows NT.
It probably works OK for a Unix system, but check it before running it
on your VHDL files to make sure it doesn't trash them.

---------------------------------------------------
#include <stdlib.h>
#include <io.h>
#include <stdio.h>

char *Usage="\
Usage:              \n\
  vpp [-h] <files>  \n\
  Use the -h (hardware) switch to convert code for synthesis.\n\
  Use no switch to convert for simulation.\n\
                    \n\
  This program preprocesses VHDL source code for simulation or synthesis.\n\
  It does this by commenting and uncommenting lines of VHDL code that are marked\n\
  by the user.  A line that contains '--$' is a simulation line and is un-commented\n\
  for simulation.  A line that contains '--#' is a synthesis line and is un-commented\n\
  for synthesis.";

int main(int ArgC, char *ArgV[])
{ int   Hard=0;             // Hardware flag: 0:sim  1:synth
  int   A;                  // Current argument
  char  L[1024];            // Input line
  char  *P;
  int   C;                  // flag
  FILE  *In, *Out;
  struct _finddata_t Fdata; // Used by file find
  long  F;

  if (ArgC==1) { puts(Usage); return(-1); }

  if (ArgV[1][0]=='-' && (ArgV[1][1]|32)=='h') Hard=1;

  for (A=Hard; ++A<ArgC;)
  { if ((F= _findfirst(ArgV[A], &Fdata)) == -1)                 // Find file names that match ARG
    { printf("vpp: Unable to open [%s] for input\n",ArgV[A]);   // No match
      continue; }

    do
    { if ((In= fopen(Fdata.name,"r")) == 0)                     // Open input file
      { printf("vpp: Unable to open [%s] for input\n",Fdata.name);
        continue; }

      if ((Out= fopen("vpp.tmp","w")) == 0)                     // Open output file
      { printf("vpp: Can't create output file [vpp.tmp] -- exiting\n");
        exit(-1); }

      printf("Processing %s\n",Fdata.name);
      while (fgets(L,1024,In))                       // Get line
      { for (P=L; *P; ++P)                           // Scan line for "--$" or "--#"
        { if (P[0] != '-' || P[1] != '-') continue;
          if ((C=P[2]) != '#' && C != '$') continue;   

          C= (C=='#') ? 1 : 0;                           // Determine type of line ($ or #)
          if (C==Hard)                                   // Remove comments
          { if (L[0]=='-' && L[1]=='-') L[0]=L[1]=' ';   //  only if line is commented.
          }
          else if (L[0]!='-' || L[1]!='-')               // Add comment if not already commented
          { if (L[0]==' ' && L[1]==' ') L[0]=L[1]='-';   // Replace spaces
            else fputs("--",Out);                        // or add to beginning of line
          }
          break;                                         // Stop scanning line
        }
        fputs(L,Out);
      }

      fclose(In); fclose(Out);
      if (remove(Fdata.name)) printf("vpp: failed to remove file [%s]\n",Fdata.name);
      if (rename("vpp.tmp",Fdata.name)) printf("vpp: unable to rename vpp.tmp to [%s]\n",Fdata.name);

    } while (_findnext(F, &Fdata) == 0);   // Next match to ArgV[A]
    _findclose(F);
  }                                        // Next ArgV
  return(0);
}

-----------------------------------------------------------------


--
Don Husby <husby@fnal.gov>             http://www-ese.fnal.gov/people/husby
Fermi National Accelerator Lab                          Phone: 630-840-3668
Batavia, IL 60510                                         Fax: 630-840-5406
Article: 22120
Subject: Buy FPGA
From: Florindo Santoro <flosan@tin.it>
Date: Wed, 26 Apr 2000 00:01:01 +0200
Links: << >>  << T >>  << A >>
Where can I Buy the FPGAs chip ?(On line)
Article: 22121
Subject: Xilinx Virtex problem (schematic)
From: "Dan Kuechle" <dan_kuechle@i-tech.com>
Date: Tue, 25 Apr 2000 23:15:08 GMT
Links: << >>  << T >>  << A >>
I'm trying to use an IBUF and an IFD on an input signal on a single pin.
I know this is ok in the 4000 series, but I'm getting errors in Virtex:
"ERROR:NgdHelpers:342 - input pad net "A_IN" drives multiple buffers".
If I go into fpga editor it seems like I should be able to do this.
Is this a S/W bug or is there a reason why I can't use both the IBUF
and the IDF of an input pin?  I'm running F2.1I  on a PC.

Thanks
Article: 22122
Subject: Running the Xilinx Alliance Tools under Linux
From: "Paul S. Graham" <grahamp@ee.byu.edu>
Date: Tue, 25 Apr 2000 21:29:08 -0600
Links: << >>  << T >>  << A >>
Here at Brigham Young University, we have been using Linux PCs and Wine
to run the Windows versions of the Xilinx Alliance 2.1i tools for
several months now.  We have had very good results for XC4000 designs
and found that this setup also works with many Virtex designs.  Some
Virtex designs do cause problems with Wine, but we are using version
991212 of Wine, so things may have improved (or gotten worse) since
then.  We have been using service pack 3 for the Windows tools and the
environment has been fairly stable; we are currently using service pack
6, but we cannot say much about the stability quite yet.

Several people has asked us for information on how we did this, so I
have created a web page describing the process.  The URL for the
information is: 

http://splish.ee.byu.edu/tutorials/linux-m2/linux-m2.html

Neither Xilinx nor BYU will provide support for running the Xilinx tools
under Linux using Wine, but we at BYU would be glad to answer questions
and help out *as time permits*.  

Considering the cost effectiveness of using speedy PCs as opposed to
expensive workstations for executing the Xilinx Alliance tools, we think
it would be nice to see Linux versions of at least the Xilinx Alliance
command-line tools (xnf2ngd, edif2ngd, ngdbuild, map, par, trce, bitgen,
xdl, etc.) sometime in the near future; the port of these command-line
tools shouldn't be very hard.  Though I am sure Xilinx would hate to
support yet another platform, making unsupported or partially supported
Linux tools would be a great boon for us and many others.

Hope you find the information helpful,

Paul Graham
===========
grahamp@ee.byu.edu
Article: 22123
Subject: Re: Xilinx Virtex problem (schematic)
From: Johnny <>
Date: Tue, 25 Apr 2000 23:38:21 -0700
Links: << >>  << T >>  << A >>
Hello Dan,

This is not a bug in the software.  The IFD is connected to an IPAD or an IOPAD (without using an IBUF).  This information is in the Libraries Guide which can be viewed at http://toolbox.xilinx.com/docsan/2_1i/data/common/lib/lib.htm

Best Regards,
Johnny
Xilinx Customer Applications
Article: 22124
Subject: Re: Virtex bitstreams wanted for compression study
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Wed, 26 Apr 2000 09:14:43 GMT
Links: << >>  << T >>  << A >>
On Wed, 29 Mar 2000 02:32:36 GMT,
allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman) wrote:

[snip]

Thanks for the bitstreams I received to help with my compression
study.

However, I am just about to change jobs, and I won't get a chance to
finish the study.

Sorry about that,
Allan.


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