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Messages from 15825

Article: 15825
Subject: Re: Illegal States in 1 Hot State Machines
From: ems@riverside-machines.com.NOSPAM
Date: Thu, 15 Apr 1999 20:33:42 GMT
Links: << >>  << T >>  << A >>
On Mon, 12 Apr 1999 19:44:25 GMT, ems@riverside-machines.com.NOSPAM
wrote:

>The amount of logic required to detect an illegal state isn't really
>the problem.
> yada

i've been away a few days, and I got a couple of mails in response to
this pointing out that the error detector could be pipelined, since it
may not matter how long the fsm takes to recover, which is a good
point.

evan

Article: 15826
Subject: High speed reconfigurability
From: Mark <mkinsley@xs4all.nl>
Date: Fri, 16 Apr 1999 00:41:08 +0200
Links: << >>  << T >>  << A >>
I like to possibilities offered by reconfigurable FPGAs, but it seems
most of the devices around are designed to be loaded once on power up,
and maybe reconfigured to do something different if the designer is
being really ingenuitive.  

I've heard talk of some new FPGAs from Xilinx which alow partial
reconfigurability (6000 series?), but i don't see these as being
particularly more useful.... ? Anyone disagree here ?

What i think would be really interesting, is being able to re-configure
an entire FPGA really quickly (say 1 system clock period ideally).  This
translates into the idea of having 'layers' of FPGA config data which
can be latched into the FPGA config area.  The inactive 'layers' being
updated or replaced while not in use -> pretty much like a video display
where an image is built up in the off screen buffer before the active
video buffer is toggled. 

The implications of such an architecture are of course ghastly amounts
of configuration data flying around and a squadron of PentiumIV's
working overtime trying to place, route and load all this into our
liquid cooled UltraFPGA.  But if applied to a pretty small block of
reconfigurable logic i think the creative designer could do some really
neat things.

....any comments ?

Are there any such devices out there already ?

Regds,
Mark K.

-- Life is about wanting what you don't know you don't want. --
Article: 15827
Subject: subscribe
From: Jim Lyke <lyke@plk.af.mil>
Date: Thu, 15 Apr 1999 16:58:38 -0600
Links: << >>  << T >>  << A >>



Article: 15828
Subject: Intelliflow question: ORD files?
From: ekuria01@kepler.poly.edu
Date: Fri, 16 Apr 1999 00:51:02 GMT
Links: << >>  << T >>  << A >>


Hello,
       I just want to first thank everyone who wrote back to my earilier
enquiries. I have one more.

  I am using the FPGA express package from synopsys to do my synthesis. I
used the intelliflow program they have to try to synthesize a design. When I
bring my design into intelliflow, it checks my design to make sure that it is
synthesizable, and it passes the checks. When I then run the routing and
placement routines after targeting a device, they also work fine. But, the
program gets stuck in the process of generating a board level symbol. This
symbol I guess would show me the schematic of how the CLBs are actualyl wired
toghether. The program stalls on the ORD file generation method which has to
be completed before a board level symbol can be generated.

ANy help is greatly appreciated.

--
Eldho Kuriakose
Nature Photography
http://kepler.poly.edu/~ekuria01/

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 15829
Subject: Re: Viewlogic FPGA Express vs Xilinx FPGA Express....any difference?
From: rk <stellare@erols.com.NOSPAM>
Date: Thu, 15 Apr 1999 21:49:29 -0400
Links: << >>  << T >>  << A >>
hi,

you're correct ... viewlogic was spun back off (minus a piece or two) and is
back as an independent company.

rk

Austin Franklin wrote:

> Though true a little while ago, I believe that has recently changed and
> Viewlogic is a separate company.
>
> Thanks,
>
> Austin
>
> APS <resp@associatedpro.com> wrote in article
> <3712ACB8.65695A01@associatedpro.com>...
> > Synopsys owns Viewlogic. They are the same. XILINX may be a rev back.
> > Also the viewlogic can do multiple vendors.
> >
> > Austin Franklin wrote:
> >
> > > Anyone know of any differences between the Viewlogic offering of FPGA
> > > Express and the Xilinx offering of FPGA Express?
> > >
> > > Thanks,
> > >
> > > Austin Franklin
> > > austin@darkroom.com
> >
> > --
> > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
> >
> > Richard Schwarz, President              EDA & Engineering Tools
> > Associated Professional Systems (APS)   http://www.associatedpro.com
> > 3003 Latrobe Court                      richard@associatedpro.com
> > Abingdon, Maryland 21009
> > Phone: 410.569.5897                     Fax:410.661.2760
> >
> > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
> >
> >
> >



Article: 15830
Subject: I NEED AN FAQ!!!!!!!!!!!! NOW!!!!!
From: David <calvin1@hopper.net>
Date: Thu, 15 Apr 1999 23:20:30 -0500
Links: << >>  << T >>  << A >>
Actually, it is not that urgent, I just want to get the "you will be
flamed to death if you ask these" questions so I know what's going on. 
I am new to this, and have no formal training, so an FAQ would be mighty
useful :)
Thanx
David
Article: 15831
Subject: Re: Allowed logic functions in Virtex LE
From: David <calvin1@hopper.net>
Date: Thu, 15 Apr 1999 23:28:21 -0500
Links: << >>  << T >>  << A >>
sounds like satisfiability to me.
It is NP complete :)
If you solve the problem generally, let me know, don't tell anyone else,
and I will get the Nobel Prize :)

All Hail Alan Turing!
David
Article: 15832
Subject: Zero power gals won't wake up on slow input transitions?
From: aimsir@hotmail.com
Date: Fri, 16 Apr 1999 08:11:08 GMT
Links: << >>  << T >>  << A >>
I'm using a 16v8Z gal from AMD/ VANTIS. Its a zero-power device - sleeping
when no input activity is sensed(50ns timeout) and waking up when any input
transition is detected.

After a few days trying to debug some inexplicable behaviour shown by a
straightforward bit of combinational logic in it - basically during some
system states certain input transitions were not 'coming through' to  the
outputs - I am now beginning to think that during the zero power mode this
device will not reliably respond (ie wakeup and 'turn-on' the logic) to an
input with a slow rise-time (say >200ns).

The slow rise was from the o/p of a voltage comparator. I was able to speed up
its rise-time  to c100ns and found that the mis-behaviour was noticeably less
frequent.

I contacted the manufacturer and after a long wait got a less than explicit
affirmation of this. For example they wouldn't say what was a suitable
'wakeup' rise time. Rien ca change.

Maybe this 'phenomenon' is old hat but I have never seen any mention of it in
the data sheets or app. notes. Yet one would think that it is a real caveat
when interfacing these devices to comparators - hardly a rare
application.

Anyone else seen similar behaviour?

regds
Mike


-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 15833
Subject: Re: Some FPGA questions
From: Richard Schwarz <rick@apsfpga.com>
Date: Fri, 16 Apr 1999 04:20:42 -0400
Links: << >>  << T >>  << A >>
Be sure that you are not doing a process or two using both clock edges (positive
and negative). For example two processes, one using the positive clk edge and
another using the negative clk edge and operating on the same signal. That won't
work.

ekuria01@kepler.poly.edu wrote:

> Hello, I am trying to synthesize a pretty simple interface board using Xilinx
> xc4000 series and Fpga express. I am having some trouble.
>
> 1. When I go into FPGA express and load my code (a simple vhdl file with 1
> entity and 1 behavioral arch), it compiles fine. I see that the icon that
> represents my code has a green check on it. When i clik on this icon, i get a
> yellow box with a pic of an or gate on it. Now, I click on FPGA express
> "create implimentation". This gives me an error saying that my negative clock
> edge triggered event will not work.
>
> Error: This use of clock edge specification not supported
>         in routine QSM1 line 129 in file 'C:/din/qsm1.vhd'  (HDL-109)
>
> this is line 129
> 129:    if (ext_clk'event and ext_clk ='0') then -- and so on..
>
> I know that teh xc4000 can do neg clock edges from looking at its CLB
> architechture. Any ideas on why this is so ?  Thanks a lot for any help.
> --
> Eldho Kuriakose
> Nature Photography
> http://kepler.poly.edu/~ekuria01/
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

    Richard Schwarz, President
    Associated Professional Systems Inc. (APS)
    email: richard@associatedpro.com
    web site: http://www.associatedpro.com
    Phone: 410-569-5897
    Fax:   410-661-2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 15834
Subject: How to write BIDIR IO in MAXPLUS2 VHDL ?
From: Alois HAHN <alois.hahn@neuroth.co.at>
Date: Fri, 16 Apr 1999 10:21:45 +0200
Links: << >>  << T >>  << A >>
Hi, 
does anybody know how to implement a bidirectional FPGA port
using MAXPLUSII VHDL tools ?

I tried following construct:

------------------------------------------------

entity datamux is
        port (
             DATA     : inout std_logic_vector (15 downto 0);
             OE_n     : in std_logic;
             OUT_DATA : in std_logic_vector (15 downto 0);
             TEST_OUT : out std_logic_vector (15 downto 0)
             );
end datamux;

architecture rtl of datamux is
begin
	-- put OUT_DATA to FPGA pin when enabled with OE_n
        --  this statement is synthesized correct
        DATA <=  OUT_DATA when (OE_n = '0') else
                (others => 'Z');

        -- here i want to read the FPGA input
        --   this does not work with  ALTERA MAXPLUS Synthesizer
        --   same works with e.g. Compass ASIC Synthesizer
        TEST_OUT <= DATA;
end rtl;

----------------------------------------------------------

Thanx
Alois
Article: 15835
Subject: Re: craig
From: Achim Gratz <gratz@ite.inf.tu-dresden.de>
Date: 16 Apr 1999 10:26:22 +0200
Links: << >>  << T >>  << A >>
Brad Taylor <blt@cmln.com> writes:

> Oooops! Big mistake here. I somehow sent this message to the news group
> here instead of my co-worker. (I can't explain how, but I must have been
> browsing the newsgroup when I started up the message). I guess it could
> have been much worse. Does anyone know how to get a message off this
> newsgroup?  This isn't the first time I've wanted to retract a post, but
> this is the first time I've had an excuse.

You need to find out how to CANCEL articles (your newsreader should
support this).  The milk is still spilled, as the CANCEL has to follow
your message before it can erase them.  The message is thus seen by
fewer people and possibly doesn't propagate as far in UseNet, but you
never know if it wasn't archived by someone already.  So better check
next time what you send out and where to.


Achim Gratz.

--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW:    http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone:  +49 351 463 - 8325
Article: 15836
Subject: Re: How to write BIDIR IO in MAXPLUS2 VHDL ?
From: Thomas Hellerforth <hellerforth@amo.de>
Date: Fri, 16 Apr 1999 09:44:39 +0100
Links: << >>  << T >>  << A >>
This one should work:

library IEEE;
use IEEE.std_logic_1164.all;


entity bidir is
 PORT (in_data : IN STD_LOGIC;
   data_oe: IN STD_LOGIC;
   out_data: OUT STD_LOGIC;
   bi_data: inout std_ulogic);
end bidir;

architecture bidir_arch of bidir is

begin

 process (in_data, data_oe, bi_data)
 begin
  if data_oe='1' then
   bi_data <= in_data;
   out_data <= bi_data;
  else
   bi_data <= 'Z';
   out_data <= bi_data;
  end if;
 end process;

end bidir_arch;


--
____________________________
Thomas Hellerforth, AMO GmbH
mailto: hellerforth@amo.de


Article: 15837
Subject: FS: Ariel dual DSP cards $300.00 two 320-C31-40 and 2megs of ram
From: "Norman Gillaspie" <norman@pcseng.com>
Date: Fri, 16 Apr 1999 02:12:21 -0700
Links: << >>  << T >>  << A >>
I have a qty of 10 Ariel ARUBA DSP cards.

Here is some basic info.

ISA board carries two C31 floating-point DSPs. The PC-C31 Aruba is a $2495
ISA bus PC-expansion card with two 40-MHz TMS320C31 floating-point DSPs, 2
Mbytes of zero-wait-state SRAM, and two high-speed RS-422 serial ports. The
SRAM is split into asymmetric banks, one per DSP. One bank contains 1.5
Mbytes; the
other contains 512 kbytes. In addition, each DSP can access a dual-ported,
8-kbyte RAM.

norman@pcseng.com


Article: 15838
Subject: Re: How to write BIDIR IO in MAXPLUS2 VHDL ?
From: Alois HAHN <alois.hahn@neuroth.co.at>
Date: Fri, 16 Apr 1999 11:53:08 +0200
Links: << >>  << T >>  << A >>
Thanks Thomas,
The code is now accepted by the MAXPLUS synthesizer.
But ... Simulation of the resulting netlist shows that 
the block does not work as I expected.

I want to have a birectional IO Pad, whose logic state can be
read inside the chip (at 'out_data').
In your example the synthesizer places at tristate buffer
to 'out_data'. So 'outdata' becomes High-Z exactly at the 
time I want to use the input function.

Any ideas ?
Alois 

 
Thomas Hellerforth wrote:
> 
> This one should work:
> 
> library IEEE;
> use IEEE.std_logic_1164.all;
> 
> entity bidir is
>  PORT (in_data : IN STD_LOGIC;
>    data_oe: IN STD_LOGIC;
>    out_data: OUT STD_LOGIC;
>    bi_data: inout std_ulogic);
> end bidir;
> .........

-- 
                             __    __
+-------------------------- |_ \  /  \ ------------------------+
| Alois HAHN                 _\ \ \  | Thomas NEUROTH GmbH     |
| alois.hahn@neuroth.co.at  | |\ \ | | Hietzinger Hauptstr. 22 |
| Tel.: (+43/1) 8775645-51  | | \ \| |                         |
| Fax.: (+43/1) 8764920     |  \ \ | | A-1130 Vienna/Austria   |
+-------------------------- |__/  \__| ------------------------+
http://www.neuroth.co.at
Article: 15839
Subject: Re: High speed reconfigurability
From: Michael Barr <mbarr@netrino.com>
Date: Fri, 16 Apr 1999 14:18:44 GMT
Links: << >>  << T >>  << A >>
Mark,

I don't know of any such devices.  I have used the Xilinx 6200 series
parts and played around with my thoughts for an appropriate swapping
architecture for hardware.  The best ideas seemed to come from the
theory of memory paging.  I presented a paper on this at DesignCon98
that you may be interested in reading.  Follow the link below and go
to the "Reconfigurable Computing" section.

	http://www.netrino.com/Publications/

Cheers,
	Michael
Article: 15840
Subject: Re: I NEED AN FAQ!!!!!!!!!!!! NOW!!!!!
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Fri, 16 Apr 1999 08:52:09 -0700
Links: << >>  << T >>  << A >>
You may find the FAQ on The Programmable Logic Jump Station of some use (see
http://www.optimagic.com/faq.html).  Also, the entire jump station is packed
with info on devices, software, boards, books, etc.--all about programmable
logic.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

David wrote in message <3716BA8E.58C5@hopper.net>...
>Actually, it is not that urgent, I just want to get the "you will be
>flamed to death if you ask these" questions so I know what's going on.
>I am new to this, and have no formal training, so an FAQ would be mighty
>useful :)
>Thanx
>David


Article: 15841
Subject: Wire-AND in longline of 4000 series?
From: Ken Chung <ckchung@cse.cuhk.edu.hk>
Date: 16 Apr 1999 16:05:13 GMT
Links: << >>  << T >>  << A >>
Hi,
	I would like to ask how can I make use of the wire-AND
property in the longline of Xilinx XC4000 series? Can I write 
VHDL code to describe it? or I can only do it by manual routing?
Any advice is much appreciated.

Regards,
Ken
Article: 15842
Subject: Re: What's the best way to learn about fpga's?
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Fri, 16 Apr 1999 09:23:03 -0700
Links: << >>  << T >>  << A >>
You can find lots of information on FPGAs and other kinds of programmable
logic on The Programmable Logic Jump Station at http://www.optimagic.com.

There is a Xilinx Student Edition, which includes development software.
There is also a companion Student Lab Book.  Both are list at
http://www.optimagic.com/books.html#Xilinx.

Other FPGA and CPLD companies provide free or low-cost versions of their
software, some available for download over the web.  See
http://www.optimagic.com/lowcost.shtml.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

Vic Lopez wrote in message <7f3qfd$43b$1@news.chatlink.com>...
>Hi everyone,
>     Has been dissapointing not to get any responses to my question. So
I'll
>pose it again. What is the best way to learn about fpga's, specially
XILINX?
>I want to be able to get my hands dirty with them, since I think they are
>becoming an important trend in logic design. Schools don't do a good job,
so
>I want to know what's available ( student editions maybe?) for people like
>me that want to learn about this subject. Thanks in advanced. Vic Lopez.
>
>


Article: 15843
Subject: std_logic_arith
From: Pieter Op De Beeck <pieter.opdebeeck@esat.kuleuven.ac.be>
Date: Fri, 16 Apr 1999 18:44:01 +0200
Links: << >>  << T >>  << A >>
Hi,

I was wondering what the following slice of code is all about (it is
from the std_logic_arith package in the IEEE library) :

in function CONV_INTEGER (line 2045 :) )
...
assert ARG'length <= 32
  report "ARG is too large in CONV_INTEGER"
  severity FAILURE;
...

my question : should the 'smaller than or equal' sign not be a 'larger'
sign?
If not, could you please explain?

greetings,
Pieter
Article: 15844
Subject: Benchmark Specialist Wanted For Printer/Software Solutions and Applications Testing-San Diego, CA
From: hradvisors1@home.com (HR Cybrarian)
Date: Fri, 16 Apr 1999 16:52:12 GMT
Links: << >>  << T >>  << A >>
Hi Guys,
	My name is Dimitrios and I am a Cybrarian at HR Advisors in
Laguna Beach Ca.  I have used usenet for years for my own personal
interests but I have just started to tap it's usefulness as a tool to
find smart technical guys like you. As you saw in the header we are
looking to fill a benchmarking position at ENCAD in San Diego. 
See the job description below. Please send your resume directly to me
with job code ENCAD-85 in the subject header to
dkhradvise@hotmail.com.

Thanks,

Dimitrios  ;-)

. 
Job Description:

Encad, Inc. is a fast-growing leading innovator of
digital imaging and inkjet digital imaging, located in
San Diego

Design and perform comprehensive technical testing of in-house and
competitive printer/software solutions as well as a wide variety of
applications testing. 

Required:
Bachelor's degree in related field or equivalent and a minimum of 3
years of relevant experience in a high tech, fast-paced marketing or
sales environment. Must possess a solid understanding of scientific
methods, as well the ability to write and produce comprehensive
reports.  A demonstrated success working with cross-functional teams
and third-party relationships is critical. Computer knowledge of
Microsoft Office including Word, Excel, PowerPoint.  Strong
communication skills and experience giving professional presentations.
Will require occasional domestic and international travel.


Preferred:
In-depth knowledge of digital imaging technology and marketplace.
Product development & management experience with a high tech product.
Knowledge of color inkjet printers and software RIPs.

Article: 15845
Subject: Altera 10K and High Density FLASH Memory
From: "Paul Venginickal" <pvegnin@REMOVEccf.nrl.navy.mil>
Date: 16 Apr 1999 17:08:57 GMT
Links: << >>  << T >>  << A >>
I am trying to develop a system that uses an Altera 10K and ~ 32M x 16 of
Flash memory.  All the flash products I have found either are too small
(density) or require an enormous amount of control and configuration, which
is fine for a microprocessor or a microcontroller.  But when you try and
incorporate all that into an FPGA, you loose most of your gates to the
initial setup.

Are there any Flash product that have a TAP (JTAG) port on the chip?  This
way I could program it externally and just read using the Altera.

Has anybody seen a canned JTAG interface for the 10K series?  ie, can you
embed a TAP programmer and use that to program the Flash from the Altera. 
I know you can program the 10K itself with its built in JTAG port, but can
you use that interface through the 10K to program something else.

Should I be looking at some other method of non volatile memory to
interface to the 10K?

Thanks.
Paul

Article: 15846
Subject: Newsletter: Embedded Design Bulletin
From: Todd Peterson <toddp@sprintmail.com>
Date: Fri, 16 Apr 1999 12:43:54 -0500
Links: << >>  << T >>  << A >>
E-Lab Digital Engineering, Inc. announces the commencement of The
Embedded Design Bulletin, a quarterly newsletter overviewing current
embedded electronics design topics.  Geared toward microcontroller
circuit designers and other embedded design engineers, it contains
recent press releases, frequently-asked questions & how-to's on current
design topics, as well as cost-saving design techniques every designer
can benefit from.  We encourage you to offer your comments, tips,
suggestions, and circuit design know-how to share with our readers.

If you'd like to be on our mailing list (free of charge) just visit

http://www.elabinc.com/newsletr.htm and enter your mailing information
(you can select postal or e-mail delivery).  In addition, you can also
download a copy of the current Embedded Design Bulletin (Acrobat PDF
format) from that page.

We hope you find the Embedded Design Bulletin of interest now and in the
years ahead.

Thank you,

  Todd Peterson
  E-Lab Digital Engineering, Inc.
    (816) 257-9954
    FAX: (816) 257-9945
  http://www.elabinc.com

Article: 15847
Subject: Top Down FPGA Hands On Workshop
From: mike@rtp-nc.mentorg.com (Mike Walsh)
Date: 16 Apr 1999 18:05:29 GMT
Links: << >>  << T >>  << A >>
Mentor Graphics is pleased to offer Top Down Hands On workshops in several
cities in the Southeast United States.  These workshops allow the attendee
to spend some hands on time with Renoir, ModelSim, and LeonardoSpectrum,
Mentor Graphics integrated FPGA design flow.

Workshops are being offered in Tampa, Florida on April 27th and in the
Ft. Lauderdale are on May 12th.  A workshop in Research Triangle Park, North
Carolina is tentatively scheduled for May 18th as well.  If you would like
more information, check out the detailed information on Mentor's web site
at:  http://www.mentor.com/region/SE/Workshops/index.html


-- 
...Mike

+--------------------------------------------------------------+
| Michael P. Walsh                     mike@rtp-nc.mentorg.com |
|                                       mike_walsh@mentorg.com |
| Applications Engineering Manager                             |
| Mentor Graphics Corporation                 V:(919) 484-2505 |
| 2525 Meridian Parkway, Suite 260            F:(919) 544-0701 |
| Research Triangle Park, North Carolina 27713                 |
+--------------------------------------------------------------+


Article: 15848
Subject: Re: High speed reconfigurability
From: "John L. Smith" <jsmith@visicom.com>
Date: Fri, 16 Apr 1999 15:50:37 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------0052CFBE47E837A6B079C3D2
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

There were a couple of papers presented at FPGA'98
conference:
Steve Trimberger- "Scheduling Designs into a Time-Multiplexed FPGA"
Chang, Marek-Sadowska - "Partitioning Sequential Circuits on Dynamically
   Reconfigurable FPGAs"
FPGA conference is sponsored by ACM, you may be able to get copies
through them.

Steve's paper concentrated on an FPGA with 8 configuration layers,
the other talked more generally on partitioning issues.

I don't know if any of these type devices have actually been
fabricated yet, I think efficiency and tools issues are still
being investigated.

- John

Mark wrote:
> 
> I like to possibilities offered by reconfigurable FPGAs, but it seems
> most of the devices around are designed to be loaded once on power up,
> and maybe reconfigured to do something different if the designer is
> being really ingenuitive.
> 
> I've heard talk of some new FPGAs from Xilinx which alow partial
> reconfigurability (6000 series?), but i don't see these as being
> particularly more useful.... ? Anyone disagree here ?
> 
> What i think would be really interesting, is being able to re-configure
> an entire FPGA really quickly (say 1 system clock period ideally).  This
> translates into the idea of having 'layers' of FPGA config data which
> can be latched into the FPGA config area.  The inactive 'layers' being
> updated or replaced while not in use -> pretty much like a video display
> where an image is built up in the off screen buffer before the active
> video buffer is toggled.
> 
> The implications of such an architecture are of course ghastly amounts
> of configuration data flying around and a squadron of PentiumIV's
> working overtime trying to place, route and load all this into our
> liquid cooled UltraFPGA.  But if applied to a pretty small block of
> reconfigurable logic i think the creative designer could do some really
> neat things.
> 
> ....any comments ?
> 
> Are there any such devices out there already ?

> Regds,
> Mark K.
> 
> -- Life is about wanting what you don't know you don't want. --
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--------------0052CFBE47E837A6B079C3D2--

Article: 15849
Subject: Re: High speed reconfigurability
From: Steve Casselman <sc@vcc.com>
Date: Fri, 16 Apr 1999 13:20:03 -0700
Links: << >>  << T >>  << A >>
Mark wrote:

> I like to possibilities offered by reconfigurable FPGAs, but it seems
> most of the devices around are designed to be loaded once on power up,
> and maybe reconfigured to do something different if the designer is
> being really ingenuitive.
>
> I've heard talk of some new FPGAs from Xilinx which alow partial
> reconfigurability (6000 series?), but i don't see these as being
> particularly more useful.... ? Anyone disagree here ?

Yes, Lots of work was done with the 6200. In my opinonbeing able to access the configuration store through
a ram style interface (address,data pairs) was extreamly
powerful and allowed you to conveniently change very small
portions of the design very quickly. The map and mask
registers were really innovative structures that allowed
all sorts of interesting behavior.

>
>
> What i think would be really interesting, is being able to re-configure
> an entire FPGA really quickly (say 1 system clock period ideally).  This
> translates into the idea of having 'layers' of FPGA config data which
> can be latched into the FPGA config area.  The inactive 'layers' being
> updated or replaced while not in use -> pretty much like a video display
> where an image is built up in the off screen buffer before the active
> video buffer is toggled.

You have to look at Andre DeHons DPGA (someone help with net pointerif one exists) and Xilinx has a patent on such a
device.  Lockheed-Sanders
go a DRAPA contract to do such a device but I'm not sure how that worked
out.  There has been some amount of work in the area.

>
>
> The implications of such an architecture are of course ghastly amounts
> of configuration data flying around and a squadron of PentiumIV's
> working overtime trying to place, route and load all this into our
> liquid cooled UltraFPGA.  But if applied to a pretty small block of
> reconfigurable logic i think the creative designer could do some really
> neat things.
>
>

If your UltraFPGA is so cool why not just have it do theplace and route???

Remember "The Software IS the Computer"



--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com




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